PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 10 Gigabit PCI Express Linux driver |
| 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include <linux/pci.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/sched.h> |
| 31 | |
| 32 | #include "ixgbe.h" |
| 33 | #include "ixgbe_phy.h" |
| 34 | |
| 35 | #define IXGBE_82599_MAX_TX_QUEUES 128 |
| 36 | #define IXGBE_82599_MAX_RX_QUEUES 128 |
| 37 | #define IXGBE_82599_RAR_ENTRIES 128 |
| 38 | #define IXGBE_82599_MC_TBL_SIZE 128 |
| 39 | #define IXGBE_82599_VFT_TBL_SIZE 128 |
| 40 | |
| 41 | s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, |
| 42 | ixgbe_link_speed *speed, |
| 43 | bool *autoneg); |
| 44 | enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); |
| 45 | s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw); |
| 46 | s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw, |
| 47 | ixgbe_link_speed speed, bool autoneg, |
| 48 | bool autoneg_wait_to_complete); |
| 49 | s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw); |
| 50 | s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, |
| 51 | ixgbe_link_speed *speed, |
| 52 | bool *link_up, bool link_up_wait_to_complete); |
| 53 | s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw, |
| 54 | ixgbe_link_speed speed, |
| 55 | bool autoneg, |
| 56 | bool autoneg_wait_to_complete); |
| 57 | static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw, |
| 58 | ixgbe_link_speed *speed, |
| 59 | bool *autoneg); |
| 60 | static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw); |
| 61 | static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw, |
| 62 | ixgbe_link_speed speed, |
| 63 | bool autoneg, |
| 64 | bool autoneg_wait_to_complete); |
| 65 | s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw); |
| 66 | s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq); |
| 67 | s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq); |
| 68 | s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, |
| 69 | u32 vind, bool vlan_on); |
| 70 | s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 71 | s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw); |
| 72 | s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val); |
| 73 | s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 74 | s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw); |
| 75 | s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw); |
| 76 | u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 77 | static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 78 | |
| 79 | void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) |
| 80 | { |
| 81 | struct ixgbe_mac_info *mac = &hw->mac; |
| 82 | if (hw->phy.multispeed_fiber) { |
| 83 | /* Set up dual speed SFP+ support */ |
| 84 | mac->ops.setup_link = |
| 85 | &ixgbe_setup_mac_link_multispeed_fiber; |
| 86 | mac->ops.setup_link_speed = |
| 87 | &ixgbe_setup_mac_link_speed_multispeed_fiber; |
| 88 | } else { |
| 89 | mac->ops.setup_link = |
| 90 | &ixgbe_setup_mac_link_82599; |
| 91 | mac->ops.setup_link_speed = |
| 92 | &ixgbe_setup_mac_link_speed_82599; |
| 93 | } |
| 94 | } |
| 95 | |
| 96 | s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) |
| 97 | { |
| 98 | s32 ret_val = 0; |
| 99 | u16 list_offset, data_offset, data_value; |
| 100 | |
| 101 | if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { |
| 102 | ixgbe_init_mac_link_ops_82599(hw); |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 103 | |
| 104 | hw->phy.ops.reset = NULL; |
| 105 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 106 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, |
| 107 | &data_offset); |
| 108 | |
| 109 | if (ret_val != 0) |
| 110 | goto setup_sfp_out; |
| 111 | |
Peter P Waskiewicz Jr | aa5aec8 | 2009-05-19 09:18:34 +0000 | [diff] [blame] | 112 | /* PHY config will finish before releasing the semaphore */ |
| 113 | ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); |
| 114 | if (ret_val != 0) { |
| 115 | ret_val = IXGBE_ERR_SWFW_SYNC; |
| 116 | goto setup_sfp_out; |
| 117 | } |
| 118 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 119 | hw->eeprom.ops.read(hw, ++data_offset, &data_value); |
| 120 | while (data_value != 0xffff) { |
| 121 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); |
| 122 | IXGBE_WRITE_FLUSH(hw); |
| 123 | hw->eeprom.ops.read(hw, ++data_offset, &data_value); |
| 124 | } |
Peter P Waskiewicz Jr | 1479ad4 | 2009-06-04 11:10:17 +0000 | [diff] [blame] | 125 | /* Now restart DSP by setting Restart_AN */ |
| 126 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, |
| 127 | (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART)); |
Peter P Waskiewicz Jr | aa5aec8 | 2009-05-19 09:18:34 +0000 | [diff] [blame] | 128 | |
| 129 | /* Release the semaphore */ |
| 130 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); |
| 131 | /* Delay obtaining semaphore again to allow FW access */ |
| 132 | msleep(hw->eeprom.semaphore_delay); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | setup_sfp_out: |
| 136 | return ret_val; |
| 137 | } |
| 138 | |
| 139 | /** |
| 140 | * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count |
| 141 | * @hw: pointer to hardware structure |
| 142 | * |
| 143 | * Read PCIe configuration space, and get the MSI-X vector count from |
| 144 | * the capabilities table. |
| 145 | **/ |
| 146 | u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw) |
| 147 | { |
| 148 | struct ixgbe_adapter *adapter = hw->back; |
| 149 | u16 msix_count; |
| 150 | pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS, |
| 151 | &msix_count); |
| 152 | msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; |
| 153 | |
| 154 | /* MSI-X count is zero-based in HW, so increment to give proper value */ |
| 155 | msix_count++; |
| 156 | |
| 157 | return msix_count; |
| 158 | } |
| 159 | |
| 160 | static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) |
| 161 | { |
| 162 | struct ixgbe_mac_info *mac = &hw->mac; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 163 | |
| 164 | ixgbe_init_mac_link_ops_82599(hw); |
| 165 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 166 | mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; |
| 167 | mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; |
| 168 | mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; |
| 169 | mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; |
| 170 | mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; |
| 171 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw); |
| 172 | |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 173 | return 0; |
| 174 | } |
| 175 | |
| 176 | /** |
| 177 | * ixgbe_init_phy_ops_82599 - PHY/SFP specific init |
| 178 | * @hw: pointer to hardware structure |
| 179 | * |
| 180 | * Initialize any function pointers that were not able to be |
| 181 | * set during get_invariants because the PHY/SFP type was |
| 182 | * not known. Perform the SFP init if necessary. |
| 183 | * |
| 184 | **/ |
| 185 | s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) |
| 186 | { |
| 187 | struct ixgbe_mac_info *mac = &hw->mac; |
| 188 | struct ixgbe_phy_info *phy = &hw->phy; |
| 189 | s32 ret_val = 0; |
| 190 | |
| 191 | /* Identify the PHY or SFP module */ |
| 192 | ret_val = phy->ops.identify(hw); |
| 193 | |
| 194 | /* Setup function pointers based on detected SFP module and speeds */ |
| 195 | ixgbe_init_mac_link_ops_82599(hw); |
| 196 | |
| 197 | /* If copper media, overwrite with copper function pointers */ |
| 198 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { |
| 199 | mac->ops.setup_link = &ixgbe_setup_copper_link_82599; |
| 200 | mac->ops.setup_link_speed = |
| 201 | &ixgbe_setup_copper_link_speed_82599; |
| 202 | mac->ops.get_link_capabilities = |
| 203 | &ixgbe_get_copper_link_capabilities_82599; |
| 204 | } |
| 205 | |
| 206 | /* Set necessary function pointers based on phy type */ |
| 207 | switch (hw->phy.type) { |
| 208 | case ixgbe_phy_tn: |
| 209 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; |
| 210 | phy->ops.get_firmware_version = |
| 211 | &ixgbe_get_phy_firmware_version_tnx; |
| 212 | break; |
| 213 | default: |
| 214 | break; |
| 215 | } |
| 216 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 217 | return ret_val; |
| 218 | } |
| 219 | |
| 220 | /** |
| 221 | * ixgbe_get_link_capabilities_82599 - Determines link capabilities |
| 222 | * @hw: pointer to hardware structure |
| 223 | * @speed: pointer to link speed |
| 224 | * @negotiation: true when autoneg or autotry is enabled |
| 225 | * |
| 226 | * Determines the link capabilities by reading the AUTOC register. |
| 227 | **/ |
| 228 | s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, |
| 229 | ixgbe_link_speed *speed, |
| 230 | bool *negotiation) |
| 231 | { |
| 232 | s32 status = 0; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 233 | u32 autoc = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 234 | |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 235 | /* |
| 236 | * Determine link capabilities based on the stored value of AUTOC, |
| 237 | * which represents EEPROM defaults. If AUTOC value has not been |
| 238 | * stored, use the current register value. |
| 239 | */ |
| 240 | if (hw->mac.orig_link_settings_stored) |
| 241 | autoc = hw->mac.orig_autoc; |
| 242 | else |
| 243 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 244 | |
| 245 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 246 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
| 247 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 248 | *negotiation = false; |
| 249 | break; |
| 250 | |
| 251 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
| 252 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 253 | *negotiation = false; |
| 254 | break; |
| 255 | |
| 256 | case IXGBE_AUTOC_LMS_1G_AN: |
| 257 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 258 | *negotiation = true; |
| 259 | break; |
| 260 | |
| 261 | case IXGBE_AUTOC_LMS_10G_SERIAL: |
| 262 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 263 | *negotiation = false; |
| 264 | break; |
| 265 | |
| 266 | case IXGBE_AUTOC_LMS_KX4_KX_KR: |
| 267 | case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: |
| 268 | *speed = IXGBE_LINK_SPEED_UNKNOWN; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 269 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 270 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 271 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 272 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 273 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 274 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 275 | *negotiation = true; |
| 276 | break; |
| 277 | |
| 278 | case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: |
| 279 | *speed = IXGBE_LINK_SPEED_100_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 280 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 281 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 282 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 283 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 284 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 285 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 286 | *negotiation = true; |
| 287 | break; |
| 288 | |
| 289 | case IXGBE_AUTOC_LMS_SGMII_1G_100M: |
| 290 | *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; |
| 291 | *negotiation = false; |
| 292 | break; |
| 293 | |
| 294 | default: |
| 295 | status = IXGBE_ERR_LINK_SETUP; |
| 296 | goto out; |
| 297 | break; |
| 298 | } |
| 299 | |
| 300 | if (hw->phy.multispeed_fiber) { |
| 301 | *speed |= IXGBE_LINK_SPEED_10GB_FULL | |
| 302 | IXGBE_LINK_SPEED_1GB_FULL; |
| 303 | *negotiation = true; |
| 304 | } |
| 305 | |
| 306 | out: |
| 307 | return status; |
| 308 | } |
| 309 | |
| 310 | /** |
| 311 | * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities |
| 312 | * @hw: pointer to hardware structure |
| 313 | * @speed: pointer to link speed |
| 314 | * @autoneg: boolean auto-negotiation value |
| 315 | * |
| 316 | * Determines the link capabilities by reading the AUTOC register. |
| 317 | **/ |
| 318 | static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw, |
| 319 | ixgbe_link_speed *speed, |
| 320 | bool *autoneg) |
| 321 | { |
| 322 | s32 status = IXGBE_ERR_LINK_SETUP; |
| 323 | u16 speed_ability; |
| 324 | |
| 325 | *speed = 0; |
| 326 | *autoneg = true; |
| 327 | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 328 | status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 329 | &speed_ability); |
| 330 | |
| 331 | if (status == 0) { |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 332 | if (speed_ability & MDIO_SPEED_10G) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 333 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 334 | if (speed_ability & MDIO_PMA_SPEED_1000) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 335 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 336 | } |
| 337 | |
| 338 | return status; |
| 339 | } |
| 340 | |
| 341 | /** |
| 342 | * ixgbe_get_media_type_82599 - Get media type |
| 343 | * @hw: pointer to hardware structure |
| 344 | * |
| 345 | * Returns the media type (fiber, copper, backplane) |
| 346 | **/ |
| 347 | enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) |
| 348 | { |
| 349 | enum ixgbe_media_type media_type; |
| 350 | |
| 351 | /* Detect if there is a copper PHY attached. */ |
| 352 | if (hw->phy.type == ixgbe_phy_cu_unknown || |
| 353 | hw->phy.type == ixgbe_phy_tn) { |
| 354 | media_type = ixgbe_media_type_copper; |
| 355 | goto out; |
| 356 | } |
| 357 | |
| 358 | switch (hw->device_id) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 359 | case IXGBE_DEV_ID_82599_KX4: |
Peter P Waskiewicz Jr | 1fcf03e | 2009-05-17 20:58:04 +0000 | [diff] [blame] | 360 | case IXGBE_DEV_ID_82599_XAUI_LOM: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 361 | /* Default device ID is mezzanine card KX/KX4 */ |
| 362 | media_type = ixgbe_media_type_backplane; |
| 363 | break; |
| 364 | case IXGBE_DEV_ID_82599_SFP: |
| 365 | media_type = ixgbe_media_type_fiber; |
| 366 | break; |
| 367 | default: |
| 368 | media_type = ixgbe_media_type_unknown; |
| 369 | break; |
| 370 | } |
| 371 | out: |
| 372 | return media_type; |
| 373 | } |
| 374 | |
| 375 | /** |
| 376 | * ixgbe_setup_mac_link_82599 - Setup MAC link settings |
| 377 | * @hw: pointer to hardware structure |
| 378 | * |
| 379 | * Configures link settings based on values in the ixgbe_hw struct. |
| 380 | * Restarts the link. Performs autonegotiation if needed. |
| 381 | **/ |
| 382 | s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw) |
| 383 | { |
| 384 | u32 autoc_reg; |
| 385 | u32 links_reg; |
| 386 | u32 i; |
| 387 | s32 status = 0; |
| 388 | |
| 389 | /* Restart link */ |
| 390 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 391 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
| 392 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); |
| 393 | |
| 394 | /* Only poll for autoneg to complete if specified to do so */ |
| 395 | if (hw->phy.autoneg_wait_to_complete) { |
| 396 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 397 | IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 398 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 399 | IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 400 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 401 | IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
| 402 | links_reg = 0; /* Just in case Autoneg time = 0 */ |
| 403 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { |
| 404 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 405 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) |
| 406 | break; |
| 407 | msleep(100); |
| 408 | } |
| 409 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { |
| 410 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; |
| 411 | hw_dbg(hw, "Autoneg did not complete.\n"); |
| 412 | } |
| 413 | } |
| 414 | } |
| 415 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 416 | /* Add delay to filter out noises during initial link setup */ |
| 417 | msleep(50); |
| 418 | |
| 419 | return status; |
| 420 | } |
| 421 | |
| 422 | /** |
| 423 | * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings |
| 424 | * @hw: pointer to hardware structure |
| 425 | * |
| 426 | * Configures link settings based on values in the ixgbe_hw struct. |
| 427 | * Restarts the link for multi-speed fiber at 1G speed, if link |
| 428 | * fails at 10G. |
| 429 | * Performs autonegotiation if needed. |
| 430 | **/ |
| 431 | s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw) |
| 432 | { |
| 433 | s32 status = 0; |
| 434 | ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG; |
Jesse Brandeburg | 4df1046 | 2009-03-13 22:15:31 +0000 | [diff] [blame] | 435 | status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 436 | true, true); |
| 437 | return status; |
| 438 | } |
| 439 | |
| 440 | /** |
| 441 | * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed |
| 442 | * @hw: pointer to hardware structure |
| 443 | * @speed: new link speed |
| 444 | * @autoneg: true if autonegotiation enabled |
| 445 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
| 446 | * |
| 447 | * Set the link speed in the AUTOC register and restarts link. |
| 448 | **/ |
| 449 | s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw, |
| 450 | ixgbe_link_speed speed, |
| 451 | bool autoneg, |
| 452 | bool autoneg_wait_to_complete) |
| 453 | { |
| 454 | s32 status = 0; |
| 455 | ixgbe_link_speed phy_link_speed; |
| 456 | ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; |
| 457 | u32 speedcnt = 0; |
| 458 | u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); |
| 459 | bool link_up = false; |
| 460 | bool negotiation; |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 461 | int i; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 462 | |
| 463 | /* Mask off requested but non-supported speeds */ |
| 464 | hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation); |
| 465 | speed &= phy_link_speed; |
| 466 | |
Mallikarjuna R Chilakala | 7476601 | 2009-06-04 11:11:34 +0000 | [diff] [blame] | 467 | /* Set autoneg_advertised value based on input link speed */ |
| 468 | hw->phy.autoneg_advertised = 0; |
| 469 | |
| 470 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
| 471 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; |
| 472 | |
| 473 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 474 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; |
| 475 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 476 | /* |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 477 | * When the driver changes the link speeds that it can support, |
| 478 | * it sets autotry_restart to true to indicate that we need to |
| 479 | * initiate a new autotry session with the link partner. To do |
| 480 | * so, we set the speed then disable and re-enable the tx laser, to |
| 481 | * alert the link partner that it also needs to restart autotry on its |
| 482 | * end. This is consistent with true clause 37 autoneg, which also |
| 483 | * involves a loss of signal. |
| 484 | */ |
| 485 | |
| 486 | /* |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 487 | * Try each speed one by one, highest priority first. We do this in |
| 488 | * software because 10gb fiber doesn't support speed autonegotiation. |
| 489 | */ |
| 490 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { |
| 491 | speedcnt++; |
| 492 | highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 493 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 494 | /* If we already have link at this speed, just jump out */ |
| 495 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); |
| 496 | |
| 497 | if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) |
| 498 | goto out; |
| 499 | |
| 500 | /* Set the module link speed */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 501 | esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); |
| 502 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 503 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 504 | /* Allow module to change analog characteristics (1G->10G) */ |
| 505 | msleep(40); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 506 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 507 | status = ixgbe_setup_mac_link_speed_82599(hw, |
| 508 | IXGBE_LINK_SPEED_10GB_FULL, |
| 509 | autoneg, |
| 510 | autoneg_wait_to_complete); |
| 511 | if (status != 0) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 512 | goto out; |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 513 | |
| 514 | /* Flap the tx laser if it has not already been done */ |
| 515 | if (hw->mac.autotry_restart) { |
| 516 | /* Disable tx laser; allow 100us to go dark per spec */ |
| 517 | esdp_reg |= IXGBE_ESDP_SDP3; |
| 518 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 519 | udelay(100); |
| 520 | |
| 521 | /* Enable tx laser; allow 2ms to light up per spec */ |
| 522 | esdp_reg &= ~IXGBE_ESDP_SDP3; |
| 523 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 524 | msleep(2); |
| 525 | |
| 526 | hw->mac.autotry_restart = false; |
| 527 | } |
| 528 | |
| 529 | /* The controller may take up to 500ms at 10g to acquire link */ |
| 530 | for (i = 0; i < 5; i++) { |
| 531 | /* Wait for the link partner to also set speed */ |
| 532 | msleep(100); |
| 533 | |
| 534 | /* If we have link, just jump out */ |
| 535 | hw->mac.ops.check_link(hw, &phy_link_speed, |
| 536 | &link_up, false); |
| 537 | if (link_up) |
| 538 | goto out; |
| 539 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 540 | } |
| 541 | |
| 542 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { |
| 543 | speedcnt++; |
| 544 | if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) |
| 545 | highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 546 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 547 | /* If we already have link at this speed, just jump out */ |
| 548 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); |
| 549 | |
| 550 | if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) |
| 551 | goto out; |
| 552 | |
| 553 | /* Set the module link speed */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 554 | esdp_reg &= ~IXGBE_ESDP_SDP5; |
| 555 | esdp_reg |= IXGBE_ESDP_SDP5_DIR; |
| 556 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 557 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 558 | /* Allow module to change analog characteristics (10G->1G) */ |
| 559 | msleep(40); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 560 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 561 | status = ixgbe_setup_mac_link_speed_82599(hw, |
| 562 | IXGBE_LINK_SPEED_1GB_FULL, |
| 563 | autoneg, |
| 564 | autoneg_wait_to_complete); |
| 565 | if (status != 0) |
| 566 | goto out; |
| 567 | |
| 568 | /* Flap the tx laser if it has not already been done */ |
| 569 | if (hw->mac.autotry_restart) { |
| 570 | /* Disable tx laser; allow 100us to go dark per spec */ |
| 571 | esdp_reg |= IXGBE_ESDP_SDP3; |
| 572 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 573 | udelay(100); |
| 574 | |
| 575 | /* Enable tx laser; allow 2ms to light up per spec */ |
| 576 | esdp_reg &= ~IXGBE_ESDP_SDP3; |
| 577 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 578 | msleep(2); |
| 579 | |
| 580 | hw->mac.autotry_restart = false; |
| 581 | } |
| 582 | |
| 583 | /* Wait for the link partner to also set speed */ |
| 584 | msleep(100); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 585 | |
| 586 | /* If we have link, just jump out */ |
| 587 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); |
| 588 | if (link_up) |
| 589 | goto out; |
| 590 | } |
| 591 | |
| 592 | /* |
| 593 | * We didn't get link. Configure back to the highest speed we tried, |
| 594 | * (if there was more than one). We call ourselves back with just the |
| 595 | * single highest speed that the user requested. |
| 596 | */ |
| 597 | if (speedcnt > 1) |
| 598 | status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, |
| 599 | highest_link_speed, |
| 600 | autoneg, |
| 601 | autoneg_wait_to_complete); |
| 602 | |
| 603 | out: |
| 604 | return status; |
| 605 | } |
| 606 | |
| 607 | /** |
| 608 | * ixgbe_check_mac_link_82599 - Determine link and speed status |
| 609 | * @hw: pointer to hardware structure |
| 610 | * @speed: pointer to link speed |
| 611 | * @link_up: true when link is up |
| 612 | * @link_up_wait_to_complete: bool used to wait for link up or not |
| 613 | * |
| 614 | * Reads the links register to determine if link is up and the current speed |
| 615 | **/ |
| 616 | s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed, |
| 617 | bool *link_up, bool link_up_wait_to_complete) |
| 618 | { |
| 619 | u32 links_reg; |
| 620 | u32 i; |
| 621 | |
| 622 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 623 | if (link_up_wait_to_complete) { |
| 624 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { |
| 625 | if (links_reg & IXGBE_LINKS_UP) { |
| 626 | *link_up = true; |
| 627 | break; |
| 628 | } else { |
| 629 | *link_up = false; |
| 630 | } |
| 631 | msleep(100); |
| 632 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 633 | } |
| 634 | } else { |
| 635 | if (links_reg & IXGBE_LINKS_UP) |
| 636 | *link_up = true; |
| 637 | else |
| 638 | *link_up = false; |
| 639 | } |
| 640 | |
| 641 | if ((links_reg & IXGBE_LINKS_SPEED_82599) == |
| 642 | IXGBE_LINKS_SPEED_10G_82599) |
| 643 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 644 | else if ((links_reg & IXGBE_LINKS_SPEED_82599) == |
| 645 | IXGBE_LINKS_SPEED_1G_82599) |
| 646 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 647 | else |
| 648 | *speed = IXGBE_LINK_SPEED_100_FULL; |
| 649 | |
Mallikarjuna R Chilakala | 620fa03 | 2009-06-04 11:11:13 +0000 | [diff] [blame] | 650 | /* if link is down, zero out the current_mode */ |
| 651 | if (*link_up == false) { |
| 652 | hw->fc.current_mode = ixgbe_fc_none; |
| 653 | hw->fc.fc_was_autonegged = false; |
| 654 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 655 | |
| 656 | return 0; |
| 657 | } |
| 658 | |
| 659 | /** |
| 660 | * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed |
| 661 | * @hw: pointer to hardware structure |
| 662 | * @speed: new link speed |
| 663 | * @autoneg: true if autonegotiation enabled |
| 664 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
| 665 | * |
| 666 | * Set the link speed in the AUTOC register and restarts link. |
| 667 | **/ |
| 668 | s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw, |
| 669 | ixgbe_link_speed speed, bool autoneg, |
| 670 | bool autoneg_wait_to_complete) |
| 671 | { |
| 672 | s32 status = 0; |
| 673 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 674 | u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 675 | u32 start_autoc = autoc; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 676 | u32 orig_autoc = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 677 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; |
| 678 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; |
| 679 | u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; |
| 680 | u32 links_reg; |
| 681 | u32 i; |
| 682 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; |
| 683 | |
| 684 | /* Check to see if speed passed in is supported. */ |
| 685 | hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg); |
| 686 | speed &= link_capabilities; |
| 687 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 688 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) { |
| 689 | status = IXGBE_ERR_LINK_SETUP; |
| 690 | goto out; |
| 691 | } |
| 692 | |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 693 | /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ |
| 694 | if (hw->mac.orig_link_settings_stored) |
| 695 | orig_autoc = hw->mac.orig_autoc; |
| 696 | else |
| 697 | orig_autoc = autoc; |
| 698 | |
| 699 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 700 | if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 701 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 702 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 703 | /* Set KX4/KX/KR support according to speed requested */ |
| 704 | autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); |
| 705 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 706 | if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 707 | autoc |= IXGBE_AUTOC_KX4_SUPP; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 708 | if (orig_autoc & IXGBE_AUTOC_KR_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 709 | autoc |= IXGBE_AUTOC_KR_SUPP; |
| 710 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 711 | autoc |= IXGBE_AUTOC_KX_SUPP; |
| 712 | } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && |
| 713 | (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || |
| 714 | link_mode == IXGBE_AUTOC_LMS_1G_AN)) { |
| 715 | /* Switch from 1G SFI to 10G SFI if requested */ |
| 716 | if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && |
| 717 | (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { |
| 718 | autoc &= ~IXGBE_AUTOC_LMS_MASK; |
| 719 | autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; |
| 720 | } |
| 721 | } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && |
| 722 | (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { |
| 723 | /* Switch from 10G SFI to 1G SFI if requested */ |
| 724 | if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && |
| 725 | (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { |
| 726 | autoc &= ~IXGBE_AUTOC_LMS_MASK; |
| 727 | if (autoneg) |
| 728 | autoc |= IXGBE_AUTOC_LMS_1G_AN; |
| 729 | else |
| 730 | autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; |
| 731 | } |
| 732 | } |
| 733 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 734 | if (autoc != start_autoc) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 735 | /* Restart link */ |
| 736 | autoc |= IXGBE_AUTOC_AN_RESTART; |
| 737 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); |
| 738 | |
| 739 | /* Only poll for autoneg to complete if specified to do so */ |
| 740 | if (autoneg_wait_to_complete) { |
| 741 | if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 742 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 743 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
| 744 | links_reg = 0; /*Just in case Autoneg time=0*/ |
| 745 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { |
| 746 | links_reg = |
| 747 | IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 748 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) |
| 749 | break; |
| 750 | msleep(100); |
| 751 | } |
| 752 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { |
| 753 | status = |
| 754 | IXGBE_ERR_AUTONEG_NOT_COMPLETE; |
| 755 | hw_dbg(hw, "Autoneg did not " |
| 756 | "complete.\n"); |
| 757 | } |
| 758 | } |
| 759 | } |
| 760 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 761 | /* Add delay to filter out noises during initial link setup */ |
| 762 | msleep(50); |
| 763 | } |
| 764 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 765 | out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 766 | return status; |
| 767 | } |
| 768 | |
| 769 | /** |
| 770 | * ixgbe_setup_copper_link_82599 - Setup copper link settings |
| 771 | * @hw: pointer to hardware structure |
| 772 | * |
| 773 | * Restarts the link on PHY and then MAC. Performs autonegotiation if needed. |
| 774 | **/ |
| 775 | static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw) |
| 776 | { |
| 777 | s32 status; |
| 778 | |
| 779 | /* Restart autonegotiation on PHY */ |
| 780 | status = hw->phy.ops.setup_link(hw); |
| 781 | |
| 782 | /* Set up MAC */ |
| 783 | ixgbe_setup_mac_link_82599(hw); |
| 784 | |
| 785 | return status; |
| 786 | } |
| 787 | |
| 788 | /** |
| 789 | * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field |
| 790 | * @hw: pointer to hardware structure |
| 791 | * @speed: new link speed |
| 792 | * @autoneg: true if autonegotiation enabled |
| 793 | * @autoneg_wait_to_complete: true if waiting is needed to complete |
| 794 | * |
| 795 | * Restarts link on PHY and MAC based on settings passed in. |
| 796 | **/ |
| 797 | static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw, |
| 798 | ixgbe_link_speed speed, |
| 799 | bool autoneg, |
| 800 | bool autoneg_wait_to_complete) |
| 801 | { |
| 802 | s32 status; |
| 803 | |
| 804 | /* Setup the PHY according to input speed */ |
| 805 | status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, |
| 806 | autoneg_wait_to_complete); |
| 807 | /* Set up MAC */ |
| 808 | ixgbe_setup_mac_link_82599(hw); |
| 809 | |
| 810 | return status; |
| 811 | } |
| 812 | |
| 813 | /** |
| 814 | * ixgbe_reset_hw_82599 - Perform hardware reset |
| 815 | * @hw: pointer to hardware structure |
| 816 | * |
| 817 | * Resets the hardware by resetting the transmit and receive units, masks |
| 818 | * and clears all interrupts, perform a PHY reset, and perform a link (MAC) |
| 819 | * reset. |
| 820 | **/ |
| 821 | s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) |
| 822 | { |
| 823 | s32 status = 0; |
| 824 | u32 ctrl, ctrl_ext; |
| 825 | u32 i; |
| 826 | u32 autoc; |
| 827 | u32 autoc2; |
| 828 | |
| 829 | /* Call adapter stop to disable tx/rx and clear interrupts */ |
| 830 | hw->mac.ops.stop_adapter(hw); |
| 831 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 832 | /* PHY ops must be identified and initialized prior to reset */ |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 833 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 834 | /* Init PHY and function pointers, perform SFP setup */ |
| 835 | status = hw->phy.ops.init(hw); |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 836 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 837 | if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) |
| 838 | goto reset_hw_out; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 839 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 840 | /* Setup SFP module if there is one present. */ |
| 841 | if (hw->phy.sfp_setup_needed) { |
| 842 | status = hw->mac.ops.setup_sfp(hw); |
| 843 | hw->phy.sfp_setup_needed = false; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 844 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 845 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 846 | /* Reset PHY */ |
| 847 | if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) |
| 848 | hw->phy.ops.reset(hw); |
| 849 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 850 | /* |
| 851 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master |
| 852 | * access and verify no pending requests before reset |
| 853 | */ |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 854 | status = ixgbe_disable_pcie_master(hw); |
| 855 | if (status != 0) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 856 | status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
| 857 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); |
| 858 | } |
| 859 | |
| 860 | /* |
| 861 | * Issue global reset to the MAC. This needs to be a SW reset. |
| 862 | * If link reset is used, it might reset the MAC when mng is using it |
| 863 | */ |
| 864 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 865 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); |
| 866 | IXGBE_WRITE_FLUSH(hw); |
| 867 | |
| 868 | /* Poll for reset bit to self-clear indicating reset is complete */ |
| 869 | for (i = 0; i < 10; i++) { |
| 870 | udelay(1); |
| 871 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 872 | if (!(ctrl & IXGBE_CTRL_RST)) |
| 873 | break; |
| 874 | } |
| 875 | if (ctrl & IXGBE_CTRL_RST) { |
| 876 | status = IXGBE_ERR_RESET_FAILED; |
| 877 | hw_dbg(hw, "Reset polling failed to complete.\n"); |
| 878 | } |
| 879 | /* Clear PF Reset Done bit so PF/VF Mail Ops can work */ |
| 880 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); |
| 881 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; |
| 882 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); |
| 883 | |
| 884 | msleep(50); |
| 885 | |
| 886 | |
| 887 | |
| 888 | /* |
| 889 | * Store the original AUTOC/AUTOC2 values if they have not been |
| 890 | * stored off yet. Otherwise restore the stored original |
| 891 | * values since the reset operation sets back to defaults. |
| 892 | */ |
| 893 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 894 | autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
| 895 | if (hw->mac.orig_link_settings_stored == false) { |
| 896 | hw->mac.orig_autoc = autoc; |
| 897 | hw->mac.orig_autoc2 = autoc2; |
| 898 | hw->mac.orig_link_settings_stored = true; |
Jesse Brandeburg | 4df1046 | 2009-03-13 22:15:31 +0000 | [diff] [blame] | 899 | } else { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 900 | if (autoc != hw->mac.orig_autoc) |
| 901 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | |
| 902 | IXGBE_AUTOC_AN_RESTART)); |
| 903 | |
| 904 | if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != |
| 905 | (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { |
| 906 | autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; |
| 907 | autoc2 |= (hw->mac.orig_autoc2 & |
| 908 | IXGBE_AUTOC2_UPPER_MASK); |
| 909 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); |
| 910 | } |
| 911 | } |
| 912 | |
Waskiewicz Jr, Peter P | aca6bee | 2009-05-17 12:32:48 +0000 | [diff] [blame] | 913 | /* |
| 914 | * Store MAC address from RAR0, clear receive address registers, and |
| 915 | * clear the multicast table. Also reset num_rar_entries to 128, |
| 916 | * since we modify this value when programming the SAN MAC address. |
| 917 | */ |
| 918 | hw->mac.num_rar_entries = 128; |
| 919 | hw->mac.ops.init_rx_addrs(hw); |
| 920 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 921 | /* Store the permanent mac address */ |
| 922 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); |
| 923 | |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 924 | /* Store the permanent SAN mac address */ |
| 925 | hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); |
| 926 | |
Waskiewicz Jr, Peter P | aca6bee | 2009-05-17 12:32:48 +0000 | [diff] [blame] | 927 | /* Add the SAN MAC address to the RAR only if it's a valid address */ |
| 928 | if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { |
| 929 | hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, |
| 930 | hw->mac.san_addr, 0, IXGBE_RAH_AV); |
| 931 | |
| 932 | /* Reserve the last RAR for the SAN MAC address */ |
| 933 | hw->mac.num_rar_entries--; |
| 934 | } |
| 935 | |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 936 | reset_hw_out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 937 | return status; |
| 938 | } |
| 939 | |
| 940 | /** |
| 941 | * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address |
| 942 | * @hw: pointer to hardware struct |
| 943 | * @rar: receive address register index to disassociate |
| 944 | * @vmdq: VMDq pool index to remove from the rar |
| 945 | **/ |
| 946 | s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq) |
| 947 | { |
| 948 | u32 mpsar_lo, mpsar_hi; |
| 949 | u32 rar_entries = hw->mac.num_rar_entries; |
| 950 | |
| 951 | if (rar < rar_entries) { |
| 952 | mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); |
| 953 | mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); |
| 954 | |
| 955 | if (!mpsar_lo && !mpsar_hi) |
| 956 | goto done; |
| 957 | |
| 958 | if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { |
| 959 | if (mpsar_lo) { |
| 960 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); |
| 961 | mpsar_lo = 0; |
| 962 | } |
| 963 | if (mpsar_hi) { |
| 964 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); |
| 965 | mpsar_hi = 0; |
| 966 | } |
| 967 | } else if (vmdq < 32) { |
| 968 | mpsar_lo &= ~(1 << vmdq); |
| 969 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); |
| 970 | } else { |
| 971 | mpsar_hi &= ~(1 << (vmdq - 32)); |
| 972 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); |
| 973 | } |
| 974 | |
| 975 | /* was that the last pool using this rar? */ |
| 976 | if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) |
| 977 | hw->mac.ops.clear_rar(hw, rar); |
| 978 | } else { |
| 979 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); |
| 980 | } |
| 981 | |
| 982 | done: |
| 983 | return 0; |
| 984 | } |
| 985 | |
| 986 | /** |
| 987 | * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address |
| 988 | * @hw: pointer to hardware struct |
| 989 | * @rar: receive address register index to associate with a VMDq index |
| 990 | * @vmdq: VMDq pool index |
| 991 | **/ |
| 992 | s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq) |
| 993 | { |
| 994 | u32 mpsar; |
| 995 | u32 rar_entries = hw->mac.num_rar_entries; |
| 996 | |
| 997 | if (rar < rar_entries) { |
| 998 | if (vmdq < 32) { |
| 999 | mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); |
| 1000 | mpsar |= 1 << vmdq; |
| 1001 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); |
| 1002 | } else { |
| 1003 | mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); |
| 1004 | mpsar |= 1 << (vmdq - 32); |
| 1005 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); |
| 1006 | } |
| 1007 | } else { |
| 1008 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); |
| 1009 | } |
| 1010 | return 0; |
| 1011 | } |
| 1012 | |
| 1013 | /** |
| 1014 | * ixgbe_set_vfta_82599 - Set VLAN filter table |
| 1015 | * @hw: pointer to hardware structure |
| 1016 | * @vlan: VLAN id to write to VLAN filter |
| 1017 | * @vind: VMDq output index that maps queue to VLAN id in VFVFB |
| 1018 | * @vlan_on: boolean flag to turn on/off VLAN in VFVF |
| 1019 | * |
| 1020 | * Turn on/off specified VLAN in the VLAN filter table. |
| 1021 | **/ |
| 1022 | s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
| 1023 | bool vlan_on) |
| 1024 | { |
| 1025 | u32 regindex; |
| 1026 | u32 bitindex; |
| 1027 | u32 bits; |
| 1028 | u32 first_empty_slot; |
| 1029 | |
| 1030 | if (vlan > 4095) |
| 1031 | return IXGBE_ERR_PARAM; |
| 1032 | |
| 1033 | /* |
| 1034 | * this is a 2 part operation - first the VFTA, then the |
| 1035 | * VLVF and VLVFB if vind is set |
| 1036 | */ |
| 1037 | |
| 1038 | /* Part 1 |
| 1039 | * The VFTA is a bitstring made up of 128 32-bit registers |
| 1040 | * that enable the particular VLAN id, much like the MTA: |
| 1041 | * bits[11-5]: which register |
| 1042 | * bits[4-0]: which bit in the register |
| 1043 | */ |
| 1044 | regindex = (vlan >> 5) & 0x7F; |
| 1045 | bitindex = vlan & 0x1F; |
| 1046 | bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); |
| 1047 | if (vlan_on) |
| 1048 | bits |= (1 << bitindex); |
| 1049 | else |
| 1050 | bits &= ~(1 << bitindex); |
| 1051 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); |
| 1052 | |
| 1053 | |
| 1054 | /* Part 2 |
| 1055 | * If the vind is set |
| 1056 | * Either vlan_on |
| 1057 | * make sure the vlan is in VLVF |
| 1058 | * set the vind bit in the matching VLVFB |
| 1059 | * Or !vlan_on |
| 1060 | * clear the pool bit and possibly the vind |
| 1061 | */ |
| 1062 | if (vind) { |
| 1063 | /* find the vlanid or the first empty slot */ |
| 1064 | first_empty_slot = 0; |
| 1065 | |
| 1066 | for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { |
| 1067 | bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); |
| 1068 | if (!bits && !first_empty_slot) |
| 1069 | first_empty_slot = regindex; |
| 1070 | else if ((bits & 0x0FFF) == vlan) |
| 1071 | break; |
| 1072 | } |
| 1073 | |
| 1074 | if (regindex >= IXGBE_VLVF_ENTRIES) { |
| 1075 | if (first_empty_slot) |
| 1076 | regindex = first_empty_slot; |
| 1077 | else { |
| 1078 | hw_dbg(hw, "No space in VLVF.\n"); |
| 1079 | goto out; |
| 1080 | } |
| 1081 | } |
| 1082 | |
| 1083 | if (vlan_on) { |
| 1084 | /* set the pool bit */ |
| 1085 | if (vind < 32) { |
| 1086 | bits = IXGBE_READ_REG(hw, |
| 1087 | IXGBE_VLVFB(regindex * 2)); |
| 1088 | bits |= (1 << vind); |
| 1089 | IXGBE_WRITE_REG(hw, |
| 1090 | IXGBE_VLVFB(regindex * 2), bits); |
| 1091 | } else { |
| 1092 | bits = IXGBE_READ_REG(hw, |
| 1093 | IXGBE_VLVFB((regindex * 2) + 1)); |
| 1094 | bits |= (1 << vind); |
| 1095 | IXGBE_WRITE_REG(hw, |
| 1096 | IXGBE_VLVFB((regindex * 2) + 1), bits); |
| 1097 | } |
| 1098 | } else { |
| 1099 | /* clear the pool bit */ |
| 1100 | if (vind < 32) { |
| 1101 | bits = IXGBE_READ_REG(hw, |
| 1102 | IXGBE_VLVFB(regindex * 2)); |
| 1103 | bits &= ~(1 << vind); |
| 1104 | IXGBE_WRITE_REG(hw, |
| 1105 | IXGBE_VLVFB(regindex * 2), bits); |
| 1106 | bits |= IXGBE_READ_REG(hw, |
| 1107 | IXGBE_VLVFB((regindex * 2) + 1)); |
| 1108 | } else { |
| 1109 | bits = IXGBE_READ_REG(hw, |
| 1110 | IXGBE_VLVFB((regindex * 2) + 1)); |
| 1111 | bits &= ~(1 << vind); |
| 1112 | IXGBE_WRITE_REG(hw, |
| 1113 | IXGBE_VLVFB((regindex * 2) + 1), bits); |
| 1114 | bits |= IXGBE_READ_REG(hw, |
| 1115 | IXGBE_VLVFB(regindex * 2)); |
| 1116 | } |
| 1117 | } |
| 1118 | |
| 1119 | if (bits) |
| 1120 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), |
| 1121 | (IXGBE_VLVF_VIEN | vlan)); |
| 1122 | else |
| 1123 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0); |
| 1124 | } |
| 1125 | |
| 1126 | out: |
| 1127 | return 0; |
| 1128 | } |
| 1129 | |
| 1130 | /** |
| 1131 | * ixgbe_clear_vfta_82599 - Clear VLAN filter table |
| 1132 | * @hw: pointer to hardware structure |
| 1133 | * |
| 1134 | * Clears the VLAN filer table, and the VMDq index associated with the filter |
| 1135 | **/ |
| 1136 | s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw) |
| 1137 | { |
| 1138 | u32 offset; |
| 1139 | |
| 1140 | for (offset = 0; offset < hw->mac.vft_size; offset++) |
| 1141 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); |
| 1142 | |
| 1143 | for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { |
| 1144 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); |
| 1145 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); |
| 1146 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); |
| 1147 | } |
| 1148 | |
| 1149 | return 0; |
| 1150 | } |
| 1151 | |
| 1152 | /** |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1153 | * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array |
| 1154 | * @hw: pointer to hardware structure |
| 1155 | **/ |
| 1156 | s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw) |
| 1157 | { |
| 1158 | int i; |
| 1159 | hw_dbg(hw, " Clearing UTA\n"); |
| 1160 | |
| 1161 | for (i = 0; i < 128; i++) |
| 1162 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); |
| 1163 | |
| 1164 | return 0; |
| 1165 | } |
| 1166 | |
| 1167 | /** |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1168 | * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. |
| 1169 | * @hw: pointer to hardware structure |
| 1170 | **/ |
| 1171 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) |
| 1172 | { |
| 1173 | int i; |
| 1174 | u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); |
| 1175 | fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; |
| 1176 | |
| 1177 | /* |
| 1178 | * Before starting reinitialization process, |
| 1179 | * FDIRCMD.CMD must be zero. |
| 1180 | */ |
| 1181 | for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { |
| 1182 | if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & |
| 1183 | IXGBE_FDIRCMD_CMD_MASK)) |
| 1184 | break; |
| 1185 | udelay(10); |
| 1186 | } |
| 1187 | if (i >= IXGBE_FDIRCMD_CMD_POLL) { |
| 1188 | hw_dbg(hw ,"Flow Director previous command isn't complete, " |
| 1189 | "aborting table re-initialization. \n"); |
| 1190 | return IXGBE_ERR_FDIR_REINIT_FAILED; |
| 1191 | } |
| 1192 | |
| 1193 | IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); |
| 1194 | IXGBE_WRITE_FLUSH(hw); |
| 1195 | /* |
| 1196 | * 82599 adapters flow director init flow cannot be restarted, |
| 1197 | * Workaround 82599 silicon errata by performing the following steps |
| 1198 | * before re-writing the FDIRCTRL control register with the same value. |
| 1199 | * - write 1 to bit 8 of FDIRCMD register & |
| 1200 | * - write 0 to bit 8 of FDIRCMD register |
| 1201 | */ |
| 1202 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, |
| 1203 | (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | |
| 1204 | IXGBE_FDIRCMD_CLEARHT)); |
| 1205 | IXGBE_WRITE_FLUSH(hw); |
| 1206 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, |
| 1207 | (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & |
| 1208 | ~IXGBE_FDIRCMD_CLEARHT)); |
| 1209 | IXGBE_WRITE_FLUSH(hw); |
| 1210 | /* |
| 1211 | * Clear FDIR Hash register to clear any leftover hashes |
| 1212 | * waiting to be programmed. |
| 1213 | */ |
| 1214 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); |
| 1215 | IXGBE_WRITE_FLUSH(hw); |
| 1216 | |
| 1217 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); |
| 1218 | IXGBE_WRITE_FLUSH(hw); |
| 1219 | |
| 1220 | /* Poll init-done after we write FDIRCTRL register */ |
| 1221 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { |
| 1222 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & |
| 1223 | IXGBE_FDIRCTRL_INIT_DONE) |
| 1224 | break; |
| 1225 | udelay(10); |
| 1226 | } |
| 1227 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) { |
| 1228 | hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); |
| 1229 | return IXGBE_ERR_FDIR_REINIT_FAILED; |
| 1230 | } |
| 1231 | |
| 1232 | /* Clear FDIR statistics registers (read to clear) */ |
| 1233 | IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); |
| 1234 | IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); |
| 1235 | IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
| 1236 | IXGBE_READ_REG(hw, IXGBE_FDIRMISS); |
| 1237 | IXGBE_READ_REG(hw, IXGBE_FDIRLEN); |
| 1238 | |
| 1239 | return 0; |
| 1240 | } |
| 1241 | |
| 1242 | /** |
| 1243 | * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters |
| 1244 | * @hw: pointer to hardware structure |
| 1245 | * @pballoc: which mode to allocate filters with |
| 1246 | **/ |
| 1247 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) |
| 1248 | { |
| 1249 | u32 fdirctrl = 0; |
| 1250 | u32 pbsize; |
| 1251 | int i; |
| 1252 | |
| 1253 | /* |
| 1254 | * Before enabling Flow Director, the Rx Packet Buffer size |
| 1255 | * must be reduced. The new value is the current size minus |
| 1256 | * flow director memory usage size. |
| 1257 | */ |
| 1258 | pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); |
| 1259 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), |
| 1260 | (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); |
| 1261 | |
| 1262 | /* |
| 1263 | * The defaults in the HW for RX PB 1-7 are not zero and so should be |
| 1264 | * intialized to zero for non DCB mode otherwise actual total RX PB |
| 1265 | * would be bigger than programmed and filter space would run into |
| 1266 | * the PB 0 region. |
| 1267 | */ |
| 1268 | for (i = 1; i < 8; i++) |
| 1269 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); |
| 1270 | |
| 1271 | /* Send interrupt when 64 filters are left */ |
| 1272 | fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; |
| 1273 | |
| 1274 | /* Set the maximum length per hash bucket to 0xA filters */ |
| 1275 | fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT; |
| 1276 | |
| 1277 | switch (pballoc) { |
| 1278 | case IXGBE_FDIR_PBALLOC_64K: |
| 1279 | /* 8k - 1 signature filters */ |
| 1280 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; |
| 1281 | break; |
| 1282 | case IXGBE_FDIR_PBALLOC_128K: |
| 1283 | /* 16k - 1 signature filters */ |
| 1284 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; |
| 1285 | break; |
| 1286 | case IXGBE_FDIR_PBALLOC_256K: |
| 1287 | /* 32k - 1 signature filters */ |
| 1288 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; |
| 1289 | break; |
| 1290 | default: |
| 1291 | /* bad value */ |
| 1292 | return IXGBE_ERR_CONFIG; |
| 1293 | }; |
| 1294 | |
| 1295 | /* Move the flexible bytes to use the ethertype - shift 6 words */ |
| 1296 | fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); |
| 1297 | |
| 1298 | fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; |
| 1299 | |
| 1300 | /* Prime the keys for hashing */ |
| 1301 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, |
| 1302 | htonl(IXGBE_ATR_BUCKET_HASH_KEY)); |
| 1303 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, |
| 1304 | htonl(IXGBE_ATR_SIGNATURE_HASH_KEY)); |
| 1305 | |
| 1306 | /* |
| 1307 | * Poll init-done after we write the register. Estimated times: |
| 1308 | * 10G: PBALLOC = 11b, timing is 60us |
| 1309 | * 1G: PBALLOC = 11b, timing is 600us |
| 1310 | * 100M: PBALLOC = 11b, timing is 6ms |
| 1311 | * |
| 1312 | * Multiple these timings by 4 if under full Rx load |
| 1313 | * |
| 1314 | * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for |
| 1315 | * 1 msec per poll time. If we're at line rate and drop to 100M, then |
| 1316 | * this might not finish in our poll time, but we can live with that |
| 1317 | * for now. |
| 1318 | */ |
| 1319 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); |
| 1320 | IXGBE_WRITE_FLUSH(hw); |
| 1321 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { |
| 1322 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & |
| 1323 | IXGBE_FDIRCTRL_INIT_DONE) |
| 1324 | break; |
| 1325 | msleep(1); |
| 1326 | } |
| 1327 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) |
| 1328 | hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); |
| 1329 | |
| 1330 | return 0; |
| 1331 | } |
| 1332 | |
| 1333 | /** |
| 1334 | * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters |
| 1335 | * @hw: pointer to hardware structure |
| 1336 | * @pballoc: which mode to allocate filters with |
| 1337 | **/ |
| 1338 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc) |
| 1339 | { |
| 1340 | u32 fdirctrl = 0; |
| 1341 | u32 pbsize; |
| 1342 | int i; |
| 1343 | |
| 1344 | /* |
| 1345 | * Before enabling Flow Director, the Rx Packet Buffer size |
| 1346 | * must be reduced. The new value is the current size minus |
| 1347 | * flow director memory usage size. |
| 1348 | */ |
| 1349 | pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); |
| 1350 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), |
| 1351 | (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); |
| 1352 | |
| 1353 | /* |
| 1354 | * The defaults in the HW for RX PB 1-7 are not zero and so should be |
| 1355 | * intialized to zero for non DCB mode otherwise actual total RX PB |
| 1356 | * would be bigger than programmed and filter space would run into |
| 1357 | * the PB 0 region. |
| 1358 | */ |
| 1359 | for (i = 1; i < 8; i++) |
| 1360 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); |
| 1361 | |
| 1362 | /* Send interrupt when 64 filters are left */ |
| 1363 | fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; |
| 1364 | |
| 1365 | switch (pballoc) { |
| 1366 | case IXGBE_FDIR_PBALLOC_64K: |
| 1367 | /* 2k - 1 perfect filters */ |
| 1368 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; |
| 1369 | break; |
| 1370 | case IXGBE_FDIR_PBALLOC_128K: |
| 1371 | /* 4k - 1 perfect filters */ |
| 1372 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; |
| 1373 | break; |
| 1374 | case IXGBE_FDIR_PBALLOC_256K: |
| 1375 | /* 8k - 1 perfect filters */ |
| 1376 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; |
| 1377 | break; |
| 1378 | default: |
| 1379 | /* bad value */ |
| 1380 | return IXGBE_ERR_CONFIG; |
| 1381 | }; |
| 1382 | |
| 1383 | /* Turn perfect match filtering on */ |
| 1384 | fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH; |
| 1385 | fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; |
| 1386 | |
| 1387 | /* Move the flexible bytes to use the ethertype - shift 6 words */ |
| 1388 | fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); |
| 1389 | |
| 1390 | /* Prime the keys for hashing */ |
| 1391 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, |
| 1392 | htonl(IXGBE_ATR_BUCKET_HASH_KEY)); |
| 1393 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, |
| 1394 | htonl(IXGBE_ATR_SIGNATURE_HASH_KEY)); |
| 1395 | |
| 1396 | /* |
| 1397 | * Poll init-done after we write the register. Estimated times: |
| 1398 | * 10G: PBALLOC = 11b, timing is 60us |
| 1399 | * 1G: PBALLOC = 11b, timing is 600us |
| 1400 | * 100M: PBALLOC = 11b, timing is 6ms |
| 1401 | * |
| 1402 | * Multiple these timings by 4 if under full Rx load |
| 1403 | * |
| 1404 | * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for |
| 1405 | * 1 msec per poll time. If we're at line rate and drop to 100M, then |
| 1406 | * this might not finish in our poll time, but we can live with that |
| 1407 | * for now. |
| 1408 | */ |
| 1409 | |
| 1410 | /* Set the maximum length per hash bucket to 0xA filters */ |
| 1411 | fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT); |
| 1412 | |
| 1413 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); |
| 1414 | IXGBE_WRITE_FLUSH(hw); |
| 1415 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { |
| 1416 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & |
| 1417 | IXGBE_FDIRCTRL_INIT_DONE) |
| 1418 | break; |
| 1419 | msleep(1); |
| 1420 | } |
| 1421 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) |
| 1422 | hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n"); |
| 1423 | |
| 1424 | return 0; |
| 1425 | } |
| 1426 | |
| 1427 | |
| 1428 | /** |
| 1429 | * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR |
| 1430 | * @stream: input bitstream to compute the hash on |
| 1431 | * @key: 32-bit hash key |
| 1432 | **/ |
| 1433 | u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, u32 key) |
| 1434 | { |
| 1435 | /* |
| 1436 | * The algorithm is as follows: |
| 1437 | * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350 |
| 1438 | * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n] |
| 1439 | * and A[n] x B[n] is bitwise AND between same length strings |
| 1440 | * |
| 1441 | * K[n] is 16 bits, defined as: |
| 1442 | * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15] |
| 1443 | * for n modulo 32 < 15, K[n] = |
| 1444 | * K[(n % 32:0) | (31:31 - (14 - (n % 32)))] |
| 1445 | * |
| 1446 | * S[n] is 16 bits, defined as: |
| 1447 | * for n >= 15, S[n] = S[n:n - 15] |
| 1448 | * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))] |
| 1449 | * |
| 1450 | * To simplify for programming, the algorithm is implemented |
| 1451 | * in software this way: |
| 1452 | * |
| 1453 | * Key[31:0], Stream[335:0] |
| 1454 | * |
| 1455 | * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times |
| 1456 | * int_key[350:0] = tmp_key[351:1] |
| 1457 | * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321] |
| 1458 | * |
| 1459 | * hash[15:0] = 0; |
| 1460 | * for (i = 0; i < 351; i++) { |
| 1461 | * if (int_key[i]) |
| 1462 | * hash ^= int_stream[(i + 15):i]; |
| 1463 | * } |
| 1464 | */ |
| 1465 | |
| 1466 | union { |
| 1467 | u64 fill[6]; |
| 1468 | u32 key[11]; |
| 1469 | u8 key_stream[44]; |
| 1470 | } tmp_key; |
| 1471 | |
| 1472 | u8 *stream = (u8 *)atr_input; |
| 1473 | u8 int_key[44]; /* upper-most bit unused */ |
| 1474 | u8 hash_str[46]; /* upper-most 2 bits unused */ |
| 1475 | u16 hash_result = 0; |
| 1476 | int i, j, k, h; |
| 1477 | |
| 1478 | /* |
| 1479 | * Initialize the fill member to prevent warnings |
| 1480 | * on some compilers |
| 1481 | */ |
| 1482 | tmp_key.fill[0] = 0; |
| 1483 | |
| 1484 | /* First load the temporary key stream */ |
| 1485 | for (i = 0; i < 6; i++) { |
| 1486 | u64 fillkey = ((u64)key << 32) | key; |
| 1487 | tmp_key.fill[i] = fillkey; |
| 1488 | } |
| 1489 | |
| 1490 | /* |
| 1491 | * Set the interim key for the hashing. Bit 352 is unused, so we must |
| 1492 | * shift and compensate when building the key. |
| 1493 | */ |
| 1494 | |
| 1495 | int_key[0] = tmp_key.key_stream[0] >> 1; |
| 1496 | for (i = 1, j = 0; i < 44; i++) { |
| 1497 | unsigned int this_key = tmp_key.key_stream[j] << 7; |
| 1498 | j++; |
| 1499 | int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1)); |
| 1500 | } |
| 1501 | |
| 1502 | /* |
| 1503 | * Set the interim bit string for the hashing. Bits 368 and 367 are |
| 1504 | * unused, so shift and compensate when building the string. |
| 1505 | */ |
| 1506 | hash_str[0] = (stream[40] & 0x7f) >> 1; |
| 1507 | for (i = 1, j = 40; i < 46; i++) { |
| 1508 | unsigned int this_str = stream[j] << 7; |
| 1509 | j++; |
| 1510 | if (j > 41) |
| 1511 | j = 0; |
| 1512 | hash_str[i] = (u8)(this_str | (stream[j] >> 1)); |
| 1513 | } |
| 1514 | |
| 1515 | /* |
| 1516 | * Now compute the hash. i is the index into hash_str, j is into our |
| 1517 | * key stream, k is counting the number of bits, and h interates within |
| 1518 | * each byte. |
| 1519 | */ |
| 1520 | for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) { |
| 1521 | for (h = 0; h < 8 && k < 351; h++, k++) { |
| 1522 | if (int_key[j] & (1 << h)) { |
| 1523 | /* |
| 1524 | * Key bit is set, XOR in the current 16-bit |
| 1525 | * string. Example of processing: |
| 1526 | * h = 0, |
| 1527 | * tmp = (hash_str[i - 2] & 0 << 16) | |
| 1528 | * (hash_str[i - 1] & 0xff << 8) | |
| 1529 | * (hash_str[i] & 0xff >> 0) |
| 1530 | * So tmp = hash_str[15 + k:k], since the |
| 1531 | * i + 2 clause rolls off the 16-bit value |
| 1532 | * h = 7, |
| 1533 | * tmp = (hash_str[i - 2] & 0x7f << 9) | |
| 1534 | * (hash_str[i - 1] & 0xff << 1) | |
| 1535 | * (hash_str[i] & 0x80 >> 7) |
| 1536 | */ |
| 1537 | int tmp = (hash_str[i] >> h); |
| 1538 | tmp |= (hash_str[i - 1] << (8 - h)); |
| 1539 | tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1)) |
| 1540 | << (16 - h); |
| 1541 | hash_result ^= (u16)tmp; |
| 1542 | } |
| 1543 | } |
| 1544 | } |
| 1545 | |
| 1546 | return hash_result; |
| 1547 | } |
| 1548 | |
| 1549 | /** |
| 1550 | * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream |
| 1551 | * @input: input stream to modify |
| 1552 | * @vlan: the VLAN id to load |
| 1553 | **/ |
| 1554 | s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan) |
| 1555 | { |
| 1556 | input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8; |
| 1557 | input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff; |
| 1558 | |
| 1559 | return 0; |
| 1560 | } |
| 1561 | |
| 1562 | /** |
| 1563 | * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address |
| 1564 | * @input: input stream to modify |
| 1565 | * @src_addr: the IP address to load |
| 1566 | **/ |
| 1567 | s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr) |
| 1568 | { |
| 1569 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24; |
| 1570 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] = |
| 1571 | (src_addr >> 16) & 0xff; |
| 1572 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] = |
| 1573 | (src_addr >> 8) & 0xff; |
| 1574 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff; |
| 1575 | |
| 1576 | return 0; |
| 1577 | } |
| 1578 | |
| 1579 | /** |
| 1580 | * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address |
| 1581 | * @input: input stream to modify |
| 1582 | * @dst_addr: the IP address to load |
| 1583 | **/ |
| 1584 | s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr) |
| 1585 | { |
| 1586 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24; |
| 1587 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] = |
| 1588 | (dst_addr >> 16) & 0xff; |
| 1589 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] = |
| 1590 | (dst_addr >> 8) & 0xff; |
| 1591 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff; |
| 1592 | |
| 1593 | return 0; |
| 1594 | } |
| 1595 | |
| 1596 | /** |
| 1597 | * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address |
| 1598 | * @input: input stream to modify |
| 1599 | * @src_addr_1: the first 4 bytes of the IP address to load |
| 1600 | * @src_addr_2: the second 4 bytes of the IP address to load |
| 1601 | * @src_addr_3: the third 4 bytes of the IP address to load |
| 1602 | * @src_addr_4: the fourth 4 bytes of the IP address to load |
| 1603 | **/ |
| 1604 | s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input, |
| 1605 | u32 src_addr_1, u32 src_addr_2, |
| 1606 | u32 src_addr_3, u32 src_addr_4) |
| 1607 | { |
| 1608 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff; |
| 1609 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] = |
| 1610 | (src_addr_4 >> 8) & 0xff; |
| 1611 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] = |
| 1612 | (src_addr_4 >> 16) & 0xff; |
| 1613 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24; |
| 1614 | |
| 1615 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff; |
| 1616 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] = |
| 1617 | (src_addr_3 >> 8) & 0xff; |
| 1618 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] = |
| 1619 | (src_addr_3 >> 16) & 0xff; |
| 1620 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24; |
| 1621 | |
| 1622 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff; |
| 1623 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] = |
| 1624 | (src_addr_2 >> 8) & 0xff; |
| 1625 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] = |
| 1626 | (src_addr_2 >> 16) & 0xff; |
| 1627 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24; |
| 1628 | |
| 1629 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff; |
| 1630 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] = |
| 1631 | (src_addr_1 >> 8) & 0xff; |
| 1632 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] = |
| 1633 | (src_addr_1 >> 16) & 0xff; |
| 1634 | input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24; |
| 1635 | |
| 1636 | return 0; |
| 1637 | } |
| 1638 | |
| 1639 | /** |
| 1640 | * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address |
| 1641 | * @input: input stream to modify |
| 1642 | * @dst_addr_1: the first 4 bytes of the IP address to load |
| 1643 | * @dst_addr_2: the second 4 bytes of the IP address to load |
| 1644 | * @dst_addr_3: the third 4 bytes of the IP address to load |
| 1645 | * @dst_addr_4: the fourth 4 bytes of the IP address to load |
| 1646 | **/ |
| 1647 | s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input, |
| 1648 | u32 dst_addr_1, u32 dst_addr_2, |
| 1649 | u32 dst_addr_3, u32 dst_addr_4) |
| 1650 | { |
| 1651 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff; |
| 1652 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] = |
| 1653 | (dst_addr_4 >> 8) & 0xff; |
| 1654 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] = |
| 1655 | (dst_addr_4 >> 16) & 0xff; |
| 1656 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24; |
| 1657 | |
| 1658 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff; |
| 1659 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] = |
| 1660 | (dst_addr_3 >> 8) & 0xff; |
| 1661 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] = |
| 1662 | (dst_addr_3 >> 16) & 0xff; |
| 1663 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24; |
| 1664 | |
| 1665 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff; |
| 1666 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] = |
| 1667 | (dst_addr_2 >> 8) & 0xff; |
| 1668 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] = |
| 1669 | (dst_addr_2 >> 16) & 0xff; |
| 1670 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24; |
| 1671 | |
| 1672 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff; |
| 1673 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] = |
| 1674 | (dst_addr_1 >> 8) & 0xff; |
| 1675 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] = |
| 1676 | (dst_addr_1 >> 16) & 0xff; |
| 1677 | input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24; |
| 1678 | |
| 1679 | return 0; |
| 1680 | } |
| 1681 | |
| 1682 | /** |
| 1683 | * ixgbe_atr_set_src_port_82599 - Sets the source port |
| 1684 | * @input: input stream to modify |
| 1685 | * @src_port: the source port to load |
| 1686 | **/ |
| 1687 | s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port) |
| 1688 | { |
| 1689 | input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8; |
| 1690 | input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff; |
| 1691 | |
| 1692 | return 0; |
| 1693 | } |
| 1694 | |
| 1695 | /** |
| 1696 | * ixgbe_atr_set_dst_port_82599 - Sets the destination port |
| 1697 | * @input: input stream to modify |
| 1698 | * @dst_port: the destination port to load |
| 1699 | **/ |
| 1700 | s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port) |
| 1701 | { |
| 1702 | input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8; |
| 1703 | input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff; |
| 1704 | |
| 1705 | return 0; |
| 1706 | } |
| 1707 | |
| 1708 | /** |
| 1709 | * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes |
| 1710 | * @input: input stream to modify |
| 1711 | * @flex_bytes: the flexible bytes to load |
| 1712 | **/ |
| 1713 | s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte) |
| 1714 | { |
| 1715 | input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8; |
| 1716 | input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff; |
| 1717 | |
| 1718 | return 0; |
| 1719 | } |
| 1720 | |
| 1721 | /** |
| 1722 | * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool |
| 1723 | * @input: input stream to modify |
| 1724 | * @vm_pool: the Virtual Machine pool to load |
| 1725 | **/ |
| 1726 | s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input, u8 vm_pool) |
| 1727 | { |
| 1728 | input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool; |
| 1729 | |
| 1730 | return 0; |
| 1731 | } |
| 1732 | |
| 1733 | /** |
| 1734 | * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type |
| 1735 | * @input: input stream to modify |
| 1736 | * @l4type: the layer 4 type value to load |
| 1737 | **/ |
| 1738 | s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type) |
| 1739 | { |
| 1740 | input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type; |
| 1741 | |
| 1742 | return 0; |
| 1743 | } |
| 1744 | |
| 1745 | /** |
| 1746 | * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream |
| 1747 | * @input: input stream to search |
| 1748 | * @vlan: the VLAN id to load |
| 1749 | **/ |
| 1750 | s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan) |
| 1751 | { |
| 1752 | *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET]; |
| 1753 | *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8; |
| 1754 | |
| 1755 | return 0; |
| 1756 | } |
| 1757 | |
| 1758 | /** |
| 1759 | * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address |
| 1760 | * @input: input stream to search |
| 1761 | * @src_addr: the IP address to load |
| 1762 | **/ |
| 1763 | s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input, u32 *src_addr) |
| 1764 | { |
| 1765 | *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET]; |
| 1766 | *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8; |
| 1767 | *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16; |
| 1768 | *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24; |
| 1769 | |
| 1770 | return 0; |
| 1771 | } |
| 1772 | |
| 1773 | /** |
| 1774 | * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address |
| 1775 | * @input: input stream to search |
| 1776 | * @dst_addr: the IP address to load |
| 1777 | **/ |
| 1778 | s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 *dst_addr) |
| 1779 | { |
| 1780 | *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET]; |
| 1781 | *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8; |
| 1782 | *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16; |
| 1783 | *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24; |
| 1784 | |
| 1785 | return 0; |
| 1786 | } |
| 1787 | |
| 1788 | /** |
| 1789 | * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address |
| 1790 | * @input: input stream to search |
| 1791 | * @src_addr_1: the first 4 bytes of the IP address to load |
| 1792 | * @src_addr_2: the second 4 bytes of the IP address to load |
| 1793 | * @src_addr_3: the third 4 bytes of the IP address to load |
| 1794 | * @src_addr_4: the fourth 4 bytes of the IP address to load |
| 1795 | **/ |
| 1796 | s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input, |
| 1797 | u32 *src_addr_1, u32 *src_addr_2, |
| 1798 | u32 *src_addr_3, u32 *src_addr_4) |
| 1799 | { |
| 1800 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12]; |
| 1801 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8; |
| 1802 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16; |
| 1803 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24; |
| 1804 | |
| 1805 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8]; |
| 1806 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8; |
| 1807 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16; |
| 1808 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24; |
| 1809 | |
| 1810 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4]; |
| 1811 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8; |
| 1812 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16; |
| 1813 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24; |
| 1814 | |
| 1815 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET]; |
| 1816 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8; |
| 1817 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16; |
| 1818 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24; |
| 1819 | |
| 1820 | return 0; |
| 1821 | } |
| 1822 | |
| 1823 | /** |
| 1824 | * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address |
| 1825 | * @input: input stream to search |
| 1826 | * @dst_addr_1: the first 4 bytes of the IP address to load |
| 1827 | * @dst_addr_2: the second 4 bytes of the IP address to load |
| 1828 | * @dst_addr_3: the third 4 bytes of the IP address to load |
| 1829 | * @dst_addr_4: the fourth 4 bytes of the IP address to load |
| 1830 | **/ |
| 1831 | s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input, |
| 1832 | u32 *dst_addr_1, u32 *dst_addr_2, |
| 1833 | u32 *dst_addr_3, u32 *dst_addr_4) |
| 1834 | { |
| 1835 | *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12]; |
| 1836 | *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8; |
| 1837 | *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16; |
| 1838 | *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24; |
| 1839 | |
| 1840 | *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8]; |
| 1841 | *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8; |
| 1842 | *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16; |
| 1843 | *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24; |
| 1844 | |
| 1845 | *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4]; |
| 1846 | *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8; |
| 1847 | *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16; |
| 1848 | *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24; |
| 1849 | |
| 1850 | *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET]; |
| 1851 | *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8; |
| 1852 | *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16; |
| 1853 | *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24; |
| 1854 | |
| 1855 | return 0; |
| 1856 | } |
| 1857 | |
| 1858 | /** |
| 1859 | * ixgbe_atr_get_src_port_82599 - Gets the source port |
| 1860 | * @input: input stream to modify |
| 1861 | * @src_port: the source port to load |
| 1862 | * |
| 1863 | * Even though the input is given in big-endian, the FDIRPORT registers |
| 1864 | * expect the ports to be programmed in little-endian. Hence the need to swap |
| 1865 | * endianness when retrieving the data. This can be confusing since the |
| 1866 | * internal hash engine expects it to be big-endian. |
| 1867 | **/ |
| 1868 | s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, u16 *src_port) |
| 1869 | { |
| 1870 | *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8; |
| 1871 | *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1]; |
| 1872 | |
| 1873 | return 0; |
| 1874 | } |
| 1875 | |
| 1876 | /** |
| 1877 | * ixgbe_atr_get_dst_port_82599 - Gets the destination port |
| 1878 | * @input: input stream to modify |
| 1879 | * @dst_port: the destination port to load |
| 1880 | * |
| 1881 | * Even though the input is given in big-endian, the FDIRPORT registers |
| 1882 | * expect the ports to be programmed in little-endian. Hence the need to swap |
| 1883 | * endianness when retrieving the data. This can be confusing since the |
| 1884 | * internal hash engine expects it to be big-endian. |
| 1885 | **/ |
| 1886 | s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input, u16 *dst_port) |
| 1887 | { |
| 1888 | *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8; |
| 1889 | *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1]; |
| 1890 | |
| 1891 | return 0; |
| 1892 | } |
| 1893 | |
| 1894 | /** |
| 1895 | * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes |
| 1896 | * @input: input stream to modify |
| 1897 | * @flex_bytes: the flexible bytes to load |
| 1898 | **/ |
| 1899 | s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input, u16 *flex_byte) |
| 1900 | { |
| 1901 | *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET]; |
| 1902 | *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8; |
| 1903 | |
| 1904 | return 0; |
| 1905 | } |
| 1906 | |
| 1907 | /** |
| 1908 | * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool |
| 1909 | * @input: input stream to modify |
| 1910 | * @vm_pool: the Virtual Machine pool to load |
| 1911 | **/ |
| 1912 | s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input, u8 *vm_pool) |
| 1913 | { |
| 1914 | *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET]; |
| 1915 | |
| 1916 | return 0; |
| 1917 | } |
| 1918 | |
| 1919 | /** |
| 1920 | * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type |
| 1921 | * @input: input stream to modify |
| 1922 | * @l4type: the layer 4 type value to load |
| 1923 | **/ |
| 1924 | s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input, u8 *l4type) |
| 1925 | { |
| 1926 | *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET]; |
| 1927 | |
| 1928 | return 0; |
| 1929 | } |
| 1930 | |
| 1931 | /** |
| 1932 | * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter |
| 1933 | * @hw: pointer to hardware structure |
| 1934 | * @stream: input bitstream |
| 1935 | * @queue: queue index to direct traffic to |
| 1936 | **/ |
| 1937 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, |
| 1938 | struct ixgbe_atr_input *input, |
| 1939 | u8 queue) |
| 1940 | { |
| 1941 | u64 fdirhashcmd; |
| 1942 | u64 fdircmd; |
| 1943 | u32 fdirhash; |
| 1944 | u16 bucket_hash, sig_hash; |
| 1945 | u8 l4type; |
| 1946 | |
| 1947 | bucket_hash = ixgbe_atr_compute_hash_82599(input, |
| 1948 | IXGBE_ATR_BUCKET_HASH_KEY); |
| 1949 | |
| 1950 | /* bucket_hash is only 15 bits */ |
| 1951 | bucket_hash &= IXGBE_ATR_HASH_MASK; |
| 1952 | |
| 1953 | sig_hash = ixgbe_atr_compute_hash_82599(input, |
| 1954 | IXGBE_ATR_SIGNATURE_HASH_KEY); |
| 1955 | |
| 1956 | /* Get the l4type in order to program FDIRCMD properly */ |
| 1957 | /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */ |
| 1958 | ixgbe_atr_get_l4type_82599(input, &l4type); |
| 1959 | |
| 1960 | /* |
| 1961 | * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits |
| 1962 | * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. |
| 1963 | */ |
| 1964 | fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; |
| 1965 | |
| 1966 | fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | |
| 1967 | IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN); |
| 1968 | |
| 1969 | switch (l4type & IXGBE_ATR_L4TYPE_MASK) { |
| 1970 | case IXGBE_ATR_L4TYPE_TCP: |
| 1971 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; |
| 1972 | break; |
| 1973 | case IXGBE_ATR_L4TYPE_UDP: |
| 1974 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; |
| 1975 | break; |
| 1976 | case IXGBE_ATR_L4TYPE_SCTP: |
| 1977 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; |
| 1978 | break; |
| 1979 | default: |
| 1980 | hw_dbg(hw, "Error on l4type input\n"); |
| 1981 | return IXGBE_ERR_CONFIG; |
| 1982 | } |
| 1983 | |
| 1984 | if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) |
| 1985 | fdircmd |= IXGBE_FDIRCMD_IPV6; |
| 1986 | |
| 1987 | fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT); |
| 1988 | fdirhashcmd = ((fdircmd << 32) | fdirhash); |
| 1989 | |
| 1990 | IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); |
| 1991 | |
| 1992 | return 0; |
| 1993 | } |
| 1994 | |
| 1995 | /** |
| 1996 | * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter |
| 1997 | * @hw: pointer to hardware structure |
| 1998 | * @input: input bitstream |
| 1999 | * @queue: queue index to direct traffic to |
| 2000 | * |
| 2001 | * Note that the caller to this function must lock before calling, since the |
| 2002 | * hardware writes must be protected from one another. |
| 2003 | **/ |
| 2004 | s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, |
| 2005 | struct ixgbe_atr_input *input, |
| 2006 | u16 soft_id, |
| 2007 | u8 queue) |
| 2008 | { |
| 2009 | u32 fdircmd = 0; |
| 2010 | u32 fdirhash; |
| 2011 | u32 src_ipv4, dst_ipv4; |
| 2012 | u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4; |
| 2013 | u16 src_port, dst_port, vlan_id, flex_bytes; |
| 2014 | u16 bucket_hash; |
| 2015 | u8 l4type; |
| 2016 | |
| 2017 | /* Get our input values */ |
| 2018 | ixgbe_atr_get_l4type_82599(input, &l4type); |
| 2019 | |
| 2020 | /* |
| 2021 | * Check l4type formatting, and bail out before we touch the hardware |
| 2022 | * if there's a configuration issue |
| 2023 | */ |
| 2024 | switch (l4type & IXGBE_ATR_L4TYPE_MASK) { |
| 2025 | case IXGBE_ATR_L4TYPE_TCP: |
| 2026 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; |
| 2027 | break; |
| 2028 | case IXGBE_ATR_L4TYPE_UDP: |
| 2029 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; |
| 2030 | break; |
| 2031 | case IXGBE_ATR_L4TYPE_SCTP: |
| 2032 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; |
| 2033 | break; |
| 2034 | default: |
| 2035 | hw_dbg(hw, "Error on l4type input\n"); |
| 2036 | return IXGBE_ERR_CONFIG; |
| 2037 | } |
| 2038 | |
| 2039 | bucket_hash = ixgbe_atr_compute_hash_82599(input, |
| 2040 | IXGBE_ATR_BUCKET_HASH_KEY); |
| 2041 | |
| 2042 | /* bucket_hash is only 15 bits */ |
| 2043 | bucket_hash &= IXGBE_ATR_HASH_MASK; |
| 2044 | |
| 2045 | ixgbe_atr_get_vlan_id_82599(input, &vlan_id); |
| 2046 | ixgbe_atr_get_src_port_82599(input, &src_port); |
| 2047 | ixgbe_atr_get_dst_port_82599(input, &dst_port); |
| 2048 | ixgbe_atr_get_flex_byte_82599(input, &flex_bytes); |
| 2049 | |
| 2050 | fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; |
| 2051 | |
| 2052 | /* Now figure out if we're IPv4 or IPv6 */ |
| 2053 | if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) { |
| 2054 | /* IPv6 */ |
| 2055 | ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2, |
| 2056 | &src_ipv6_3, &src_ipv6_4); |
| 2057 | |
| 2058 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1); |
| 2059 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2); |
| 2060 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3); |
| 2061 | /* The last 4 bytes is the same register as IPv4 */ |
| 2062 | IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4); |
| 2063 | |
| 2064 | fdircmd |= IXGBE_FDIRCMD_IPV6; |
| 2065 | fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH; |
| 2066 | } else { |
| 2067 | /* IPv4 */ |
| 2068 | ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4); |
| 2069 | IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4); |
| 2070 | |
| 2071 | } |
| 2072 | |
| 2073 | ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4); |
| 2074 | IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4); |
| 2075 | |
| 2076 | IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id | |
| 2077 | (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT))); |
| 2078 | IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port | |
| 2079 | (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT))); |
| 2080 | |
| 2081 | fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW; |
| 2082 | fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE; |
| 2083 | fdircmd |= IXGBE_FDIRCMD_LAST; |
| 2084 | fdircmd |= IXGBE_FDIRCMD_QUEUE_EN; |
| 2085 | fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; |
| 2086 | |
| 2087 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); |
| 2088 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); |
| 2089 | |
| 2090 | return 0; |
| 2091 | } |
| 2092 | /** |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2093 | * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register |
| 2094 | * @hw: pointer to hardware structure |
| 2095 | * @reg: analog register to read |
| 2096 | * @val: read value |
| 2097 | * |
| 2098 | * Performs read operation to Omer analog register specified. |
| 2099 | **/ |
| 2100 | s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) |
| 2101 | { |
| 2102 | u32 core_ctl; |
| 2103 | |
| 2104 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | |
| 2105 | (reg << 8)); |
| 2106 | IXGBE_WRITE_FLUSH(hw); |
| 2107 | udelay(10); |
| 2108 | core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); |
| 2109 | *val = (u8)core_ctl; |
| 2110 | |
| 2111 | return 0; |
| 2112 | } |
| 2113 | |
| 2114 | /** |
| 2115 | * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register |
| 2116 | * @hw: pointer to hardware structure |
| 2117 | * @reg: atlas register to write |
| 2118 | * @val: value to write |
| 2119 | * |
| 2120 | * Performs write operation to Omer analog register specified. |
| 2121 | **/ |
| 2122 | s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) |
| 2123 | { |
| 2124 | u32 core_ctl; |
| 2125 | |
| 2126 | core_ctl = (reg << 8) | val; |
| 2127 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); |
| 2128 | IXGBE_WRITE_FLUSH(hw); |
| 2129 | udelay(10); |
| 2130 | |
| 2131 | return 0; |
| 2132 | } |
| 2133 | |
| 2134 | /** |
| 2135 | * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx |
| 2136 | * @hw: pointer to hardware structure |
| 2137 | * |
| 2138 | * Starts the hardware using the generic start_hw function. |
| 2139 | * Then performs device-specific: |
| 2140 | * Clears the rate limiter registers. |
| 2141 | **/ |
| 2142 | s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) |
| 2143 | { |
| 2144 | u32 q_num; |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 2145 | s32 ret_val; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2146 | |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 2147 | ret_val = ixgbe_start_hw_generic(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2148 | |
| 2149 | /* Clear the rate limiters */ |
| 2150 | for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) { |
| 2151 | IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num); |
| 2152 | IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); |
| 2153 | } |
| 2154 | IXGBE_WRITE_FLUSH(hw); |
| 2155 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 2156 | /* We need to run link autotry after the driver loads */ |
| 2157 | hw->mac.autotry_restart = true; |
| 2158 | |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 2159 | if (ret_val == 0) |
| 2160 | ret_val = ixgbe_verify_fw_version_82599(hw); |
| 2161 | |
| 2162 | return ret_val; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2163 | } |
| 2164 | |
| 2165 | /** |
| 2166 | * ixgbe_identify_phy_82599 - Get physical layer module |
| 2167 | * @hw: pointer to hardware structure |
| 2168 | * |
| 2169 | * Determines the physical layer module found on the current adapter. |
| 2170 | **/ |
| 2171 | s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) |
| 2172 | { |
| 2173 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; |
| 2174 | status = ixgbe_identify_phy_generic(hw); |
| 2175 | if (status != 0) |
| 2176 | status = ixgbe_identify_sfp_module_generic(hw); |
| 2177 | return status; |
| 2178 | } |
| 2179 | |
| 2180 | /** |
| 2181 | * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type |
| 2182 | * @hw: pointer to hardware structure |
| 2183 | * |
| 2184 | * Determines physical layer capabilities of the current configuration. |
| 2185 | **/ |
| 2186 | u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) |
| 2187 | { |
| 2188 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2189 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 2190 | u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
| 2191 | u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; |
| 2192 | u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; |
| 2193 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; |
| 2194 | u16 ext_ability = 0; |
PJ Waskiewicz | 1339b9e | 2009-03-13 22:12:29 +0000 | [diff] [blame] | 2195 | u8 comp_codes_10g = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2196 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2197 | hw->phy.ops.identify(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2198 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2199 | if (hw->phy.type == ixgbe_phy_tn || |
| 2200 | hw->phy.type == ixgbe_phy_cu_unknown) { |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 2201 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, |
| 2202 | &ext_ability); |
| 2203 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2204 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 2205 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2206 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 2207 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2208 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
| 2209 | goto out; |
| 2210 | } |
| 2211 | |
| 2212 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
| 2213 | case IXGBE_AUTOC_LMS_1G_AN: |
| 2214 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
| 2215 | if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { |
| 2216 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | |
| 2217 | IXGBE_PHYSICAL_LAYER_1000BASE_BX; |
| 2218 | goto out; |
| 2219 | } else |
| 2220 | /* SFI mode so read SFP module */ |
| 2221 | goto sfp_check; |
| 2222 | break; |
| 2223 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
| 2224 | if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) |
| 2225 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; |
| 2226 | else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) |
| 2227 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; |
Peter P Waskiewicz Jr | 1fcf03e | 2009-05-17 20:58:04 +0000 | [diff] [blame] | 2228 | else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) |
| 2229 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2230 | goto out; |
| 2231 | break; |
| 2232 | case IXGBE_AUTOC_LMS_10G_SERIAL: |
| 2233 | if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { |
| 2234 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; |
| 2235 | goto out; |
| 2236 | } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) |
| 2237 | goto sfp_check; |
| 2238 | break; |
| 2239 | case IXGBE_AUTOC_LMS_KX4_KX_KR: |
| 2240 | case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: |
| 2241 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
| 2242 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; |
| 2243 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
| 2244 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; |
| 2245 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
| 2246 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; |
| 2247 | goto out; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2248 | break; |
| 2249 | default: |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2250 | goto out; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2251 | break; |
| 2252 | } |
| 2253 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2254 | sfp_check: |
| 2255 | /* SFP check must be done last since DA modules are sometimes used to |
| 2256 | * test KR mode - we need to id KR mode correctly before SFP module. |
| 2257 | * Call identify_sfp because the pluggable module may have changed */ |
| 2258 | hw->phy.ops.identify_sfp(hw); |
| 2259 | if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) |
| 2260 | goto out; |
| 2261 | |
| 2262 | switch (hw->phy.type) { |
| 2263 | case ixgbe_phy_tw_tyco: |
| 2264 | case ixgbe_phy_tw_unknown: |
| 2265 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; |
| 2266 | break; |
| 2267 | case ixgbe_phy_sfp_avago: |
| 2268 | case ixgbe_phy_sfp_ftl: |
| 2269 | case ixgbe_phy_sfp_intel: |
| 2270 | case ixgbe_phy_sfp_unknown: |
| 2271 | hw->phy.ops.read_i2c_eeprom(hw, |
| 2272 | IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); |
| 2273 | if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) |
| 2274 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; |
| 2275 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) |
| 2276 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; |
| 2277 | break; |
| 2278 | default: |
| 2279 | break; |
| 2280 | } |
| 2281 | |
| 2282 | out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2283 | return physical_layer; |
| 2284 | } |
| 2285 | |
| 2286 | /** |
| 2287 | * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 |
| 2288 | * @hw: pointer to hardware structure |
| 2289 | * @regval: register value to write to RXCTRL |
| 2290 | * |
| 2291 | * Enables the Rx DMA unit for 82599 |
| 2292 | **/ |
| 2293 | s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) |
| 2294 | { |
| 2295 | #define IXGBE_MAX_SECRX_POLL 30 |
| 2296 | int i; |
| 2297 | int secrxreg; |
| 2298 | |
| 2299 | /* |
| 2300 | * Workaround for 82599 silicon errata when enabling the Rx datapath. |
| 2301 | * If traffic is incoming before we enable the Rx unit, it could hang |
| 2302 | * the Rx DMA unit. Therefore, make sure the security engine is |
| 2303 | * completely disabled prior to enabling the Rx unit. |
| 2304 | */ |
| 2305 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); |
| 2306 | secrxreg |= IXGBE_SECRXCTRL_RX_DIS; |
| 2307 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); |
| 2308 | for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { |
| 2309 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); |
| 2310 | if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) |
| 2311 | break; |
| 2312 | else |
| 2313 | udelay(10); |
| 2314 | } |
| 2315 | |
| 2316 | /* For informational purposes only */ |
| 2317 | if (i >= IXGBE_MAX_SECRX_POLL) |
| 2318 | hw_dbg(hw, "Rx unit being enabled before security " |
| 2319 | "path fully disabled. Continuing with init.\n"); |
| 2320 | |
| 2321 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); |
| 2322 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); |
| 2323 | secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; |
| 2324 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); |
| 2325 | IXGBE_WRITE_FLUSH(hw); |
| 2326 | |
| 2327 | return 0; |
| 2328 | } |
| 2329 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2330 | /** |
| 2331 | * ixgbe_get_device_caps_82599 - Get additional device capabilities |
| 2332 | * @hw: pointer to hardware structure |
| 2333 | * @device_caps: the EEPROM word with the extra device capabilities |
| 2334 | * |
| 2335 | * This function will read the EEPROM location for the device capabilities, |
| 2336 | * and return the word through device_caps. |
| 2337 | **/ |
| 2338 | s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps) |
| 2339 | { |
| 2340 | hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); |
| 2341 | |
| 2342 | return 0; |
| 2343 | } |
| 2344 | |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 2345 | /** |
| 2346 | * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599 |
| 2347 | * @hw: pointer to hardware structure |
| 2348 | * @san_mac_offset: SAN MAC address offset |
| 2349 | * |
| 2350 | * This function will read the EEPROM location for the SAN MAC address |
| 2351 | * pointer, and returns the value at that location. This is used in both |
| 2352 | * get and set mac_addr routines. |
| 2353 | **/ |
| 2354 | s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw, |
| 2355 | u16 *san_mac_offset) |
| 2356 | { |
| 2357 | /* |
| 2358 | * First read the EEPROM pointer to see if the MAC addresses are |
| 2359 | * available. |
| 2360 | */ |
| 2361 | hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); |
| 2362 | |
| 2363 | return 0; |
| 2364 | } |
| 2365 | |
| 2366 | /** |
| 2367 | * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599 |
| 2368 | * @hw: pointer to hardware structure |
| 2369 | * @san_mac_addr: SAN MAC address |
| 2370 | * |
| 2371 | * Reads the SAN MAC address from the EEPROM, if it's available. This is |
| 2372 | * per-port, so set_lan_id() must be called before reading the addresses. |
| 2373 | * set_lan_id() is called by identify_sfp(), but this cannot be relied |
| 2374 | * upon for non-SFP connections, so we must call it here. |
| 2375 | **/ |
| 2376 | s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr) |
| 2377 | { |
| 2378 | u16 san_mac_data, san_mac_offset; |
| 2379 | u8 i; |
| 2380 | |
| 2381 | /* |
| 2382 | * First read the EEPROM pointer to see if the MAC addresses are |
| 2383 | * available. If they're not, no point in calling set_lan_id() here. |
| 2384 | */ |
| 2385 | ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset); |
| 2386 | |
| 2387 | if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { |
| 2388 | /* |
| 2389 | * No addresses available in this EEPROM. It's not an |
| 2390 | * error though, so just wipe the local address and return. |
| 2391 | */ |
| 2392 | for (i = 0; i < 6; i++) |
| 2393 | san_mac_addr[i] = 0xFF; |
| 2394 | |
| 2395 | goto san_mac_addr_out; |
| 2396 | } |
| 2397 | |
| 2398 | /* make sure we know which port we need to program */ |
| 2399 | hw->mac.ops.set_lan_id(hw); |
| 2400 | /* apply the port offset to the address offset */ |
| 2401 | (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : |
| 2402 | (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); |
| 2403 | for (i = 0; i < 3; i++) { |
| 2404 | hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); |
| 2405 | san_mac_addr[i * 2] = (u8)(san_mac_data); |
| 2406 | san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); |
| 2407 | san_mac_offset++; |
| 2408 | } |
| 2409 | |
| 2410 | san_mac_addr_out: |
| 2411 | return 0; |
| 2412 | } |
| 2413 | |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 2414 | /** |
| 2415 | * ixgbe_verify_fw_version_82599 - verify fw version for 82599 |
| 2416 | * @hw: pointer to hardware structure |
| 2417 | * |
| 2418 | * Verifies that installed the firmware version is 0.6 or higher |
| 2419 | * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. |
| 2420 | * |
| 2421 | * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or |
| 2422 | * if the FW version is not supported. |
| 2423 | **/ |
| 2424 | static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) |
| 2425 | { |
| 2426 | s32 status = IXGBE_ERR_EEPROM_VERSION; |
| 2427 | u16 fw_offset, fw_ptp_cfg_offset; |
| 2428 | u16 fw_version = 0; |
| 2429 | |
| 2430 | /* firmware check is only necessary for SFI devices */ |
| 2431 | if (hw->phy.media_type != ixgbe_media_type_fiber) { |
| 2432 | status = 0; |
| 2433 | goto fw_version_out; |
| 2434 | } |
| 2435 | |
| 2436 | /* get the offset to the Firmware Module block */ |
| 2437 | hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); |
| 2438 | |
| 2439 | if ((fw_offset == 0) || (fw_offset == 0xFFFF)) |
| 2440 | goto fw_version_out; |
| 2441 | |
| 2442 | /* get the offset to the Pass Through Patch Configuration block */ |
| 2443 | hw->eeprom.ops.read(hw, (fw_offset + |
| 2444 | IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), |
| 2445 | &fw_ptp_cfg_offset); |
| 2446 | |
| 2447 | if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) |
| 2448 | goto fw_version_out; |
| 2449 | |
| 2450 | /* get the firmware version */ |
| 2451 | hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + |
| 2452 | IXGBE_FW_PATCH_VERSION_4), |
| 2453 | &fw_version); |
| 2454 | |
| 2455 | if (fw_version > 0x5) |
| 2456 | status = 0; |
| 2457 | |
| 2458 | fw_version_out: |
| 2459 | return status; |
| 2460 | } |
| 2461 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2462 | static struct ixgbe_mac_operations mac_ops_82599 = { |
| 2463 | .init_hw = &ixgbe_init_hw_generic, |
| 2464 | .reset_hw = &ixgbe_reset_hw_82599, |
| 2465 | .start_hw = &ixgbe_start_hw_82599, |
| 2466 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
| 2467 | .get_media_type = &ixgbe_get_media_type_82599, |
| 2468 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, |
| 2469 | .enable_rx_dma = &ixgbe_enable_rx_dma_82599, |
| 2470 | .get_mac_addr = &ixgbe_get_mac_addr_generic, |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 2471 | .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599, |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2472 | .get_device_caps = &ixgbe_get_device_caps_82599, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2473 | .stop_adapter = &ixgbe_stop_adapter_generic, |
| 2474 | .get_bus_info = &ixgbe_get_bus_info_generic, |
| 2475 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, |
| 2476 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, |
| 2477 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, |
| 2478 | .setup_link = &ixgbe_setup_mac_link_82599, |
| 2479 | .setup_link_speed = &ixgbe_setup_mac_link_speed_82599, |
| 2480 | .check_link = &ixgbe_check_mac_link_82599, |
| 2481 | .get_link_capabilities = &ixgbe_get_link_capabilities_82599, |
| 2482 | .led_on = &ixgbe_led_on_generic, |
| 2483 | .led_off = &ixgbe_led_off_generic, |
PJ Waskiewicz | 87c1201 | 2009-04-08 13:20:31 +0000 | [diff] [blame] | 2484 | .blink_led_start = &ixgbe_blink_led_start_generic, |
| 2485 | .blink_led_stop = &ixgbe_blink_led_stop_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2486 | .set_rar = &ixgbe_set_rar_generic, |
| 2487 | .clear_rar = &ixgbe_clear_rar_generic, |
| 2488 | .set_vmdq = &ixgbe_set_vmdq_82599, |
| 2489 | .clear_vmdq = &ixgbe_clear_vmdq_82599, |
| 2490 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, |
| 2491 | .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, |
| 2492 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, |
| 2493 | .enable_mc = &ixgbe_enable_mc_generic, |
| 2494 | .disable_mc = &ixgbe_disable_mc_generic, |
| 2495 | .clear_vfta = &ixgbe_clear_vfta_82599, |
| 2496 | .set_vfta = &ixgbe_set_vfta_82599, |
Mallikarjuna R Chilakala | 620fa03 | 2009-06-04 11:11:13 +0000 | [diff] [blame] | 2497 | .fc_enable = &ixgbe_fc_enable_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2498 | .init_uta_tables = &ixgbe_init_uta_tables_82599, |
| 2499 | .setup_sfp = &ixgbe_setup_sfp_modules_82599, |
| 2500 | }; |
| 2501 | |
| 2502 | static struct ixgbe_eeprom_operations eeprom_ops_82599 = { |
| 2503 | .init_params = &ixgbe_init_eeprom_params_generic, |
| 2504 | .read = &ixgbe_read_eeprom_generic, |
| 2505 | .write = &ixgbe_write_eeprom_generic, |
| 2506 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, |
| 2507 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, |
| 2508 | }; |
| 2509 | |
| 2510 | static struct ixgbe_phy_operations phy_ops_82599 = { |
| 2511 | .identify = &ixgbe_identify_phy_82599, |
| 2512 | .identify_sfp = &ixgbe_identify_sfp_module_generic, |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 2513 | .init = &ixgbe_init_phy_ops_82599, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2514 | .reset = &ixgbe_reset_phy_generic, |
| 2515 | .read_reg = &ixgbe_read_phy_reg_generic, |
| 2516 | .write_reg = &ixgbe_write_phy_reg_generic, |
| 2517 | .setup_link = &ixgbe_setup_phy_link_generic, |
| 2518 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, |
| 2519 | .read_i2c_byte = &ixgbe_read_i2c_byte_generic, |
| 2520 | .write_i2c_byte = &ixgbe_write_i2c_byte_generic, |
| 2521 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, |
| 2522 | .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, |
| 2523 | }; |
| 2524 | |
| 2525 | struct ixgbe_info ixgbe_82599_info = { |
| 2526 | .mac = ixgbe_mac_82599EB, |
| 2527 | .get_invariants = &ixgbe_get_invariants_82599, |
| 2528 | .mac_ops = &mac_ops_82599, |
| 2529 | .eeprom_ops = &eeprom_ops_82599, |
| 2530 | .phy_ops = &phy_ops_82599, |
| 2531 | }; |