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viresh kumar986435e2010-04-01 12:30:49 +01001/*
2 * arch/arm/plat-spear/time.c
3 *
Shiraz Hashim5c881d92011-02-16 07:40:32 +01004 * Copyright (C) 2010 ST Microelectronics
Viresh Kumar9cc23682014-04-18 15:07:16 -07005 * Shiraz Hashim<shiraz.linux.kernel@gmail.com>
viresh kumar986435e2010-04-01 12:30:49 +01006 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/clockchips.h>
14#include <linux/clocksource.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
Arnd Bergmann5019f0b2012-04-11 17:30:11 +000018#include <linux/ioport.h>
viresh kumar986435e2010-04-01 12:30:49 +010019#include <linux/io.h>
20#include <linux/kernel.h>
Viresh Kumar30551c02012-04-21 13:15:37 +053021#include <linux/of_irq.h>
22#include <linux/of_address.h>
viresh kumar986435e2010-04-01 12:30:49 +010023#include <linux/time.h>
24#include <linux/irq.h>
25#include <asm/mach/time.h>
Arnd Bergmann2b9c6132012-12-02 15:49:04 +010026#include "generic.h"
viresh kumar986435e2010-04-01 12:30:49 +010027
28/*
29 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
30 * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
31 * they share same functional clock. Any change in one's functional clock will
32 * also affect other timer.
33 */
34
35#define CLKEVT 0 /* gpt0, channel0 as clockevent */
36#define CLKSRC 1 /* gpt0, channel1 as clocksource */
37
38/* Register offsets, x is channel number */
39#define CR(x) ((x) * 0x80 + 0x80)
40#define IR(x) ((x) * 0x80 + 0x84)
41#define LOAD(x) ((x) * 0x80 + 0x88)
42#define COUNT(x) ((x) * 0x80 + 0x8C)
43
44/* Reg bit definitions */
45#define CTRL_INT_ENABLE 0x0100
46#define CTRL_ENABLE 0x0020
47#define CTRL_ONE_SHOT 0x0010
48
49#define CTRL_PRESCALER1 0x0
50#define CTRL_PRESCALER2 0x1
51#define CTRL_PRESCALER4 0x2
52#define CTRL_PRESCALER8 0x3
53#define CTRL_PRESCALER16 0x4
54#define CTRL_PRESCALER32 0x5
55#define CTRL_PRESCALER64 0x6
56#define CTRL_PRESCALER128 0x7
57#define CTRL_PRESCALER256 0x8
58
59#define INT_STATUS 0x1
60
Linus Walleij4bd48942010-07-19 20:55:46 +010061/*
62 * Minimum clocksource/clockevent timer range in seconds
63 */
64#define SPEAR_MIN_RANGE 4
65
viresh kumar986435e2010-04-01 12:30:49 +010066static __iomem void *gpt_base;
67static struct clk *gpt_clk;
68
viresh kumar986435e2010-04-01 12:30:49 +010069static int clockevent_next_event(unsigned long evt,
70 struct clock_event_device *clk_event_dev);
71
Alex Elder1be5f692014-04-09 09:01:12 -050072static void __init spear_clocksource_init(void)
viresh kumar986435e2010-04-01 12:30:49 +010073{
74 u32 tick_rate;
75 u16 val;
76
77 /* program the prescaler (/256)*/
78 writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
79
80 /* find out actual clock driving Timer */
81 tick_rate = clk_get_rate(gpt_clk);
82 tick_rate >>= CTRL_PRESCALER256;
83
84 writew(0xFFFF, gpt_base + LOAD(CLKSRC));
85
86 val = readw(gpt_base + CR(CLKSRC));
87 val &= ~CTRL_ONE_SHOT; /* autoreload mode */
88 val |= CTRL_ENABLE ;
89 writew(val, gpt_base + CR(CLKSRC));
90
viresh kumar986435e2010-04-01 12:30:49 +010091 /* register the clocksource */
Russell Kingd6e15d72011-05-08 17:10:14 +010092 clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
93 200, 16, clocksource_mmio_readw_up);
viresh kumar986435e2010-04-01 12:30:49 +010094}
95
Viresh Kumar7639c0b2015-02-27 13:39:52 +053096static inline void timer_shutdown(struct clock_event_device *evt)
97{
98 u16 val = readw(gpt_base + CR(CLKEVT));
viresh kumar986435e2010-04-01 12:30:49 +010099
Viresh Kumar7639c0b2015-02-27 13:39:52 +0530100 /* stop the timer */
101 val &= ~CTRL_ENABLE;
102 writew(val, gpt_base + CR(CLKEVT));
103}
104
105static int spear_shutdown(struct clock_event_device *evt)
106{
107 timer_shutdown(evt);
108
109 return 0;
110}
111
112static int spear_set_oneshot(struct clock_event_device *evt)
113{
114 u16 val;
115
116 /* stop the timer */
117 timer_shutdown(evt);
118
119 val = readw(gpt_base + CR(CLKEVT));
120 val |= CTRL_ONE_SHOT;
121 writew(val, gpt_base + CR(CLKEVT));
122
123 return 0;
124}
125
126static int spear_set_periodic(struct clock_event_device *evt)
viresh kumar986435e2010-04-01 12:30:49 +0100127{
128 u32 period;
129 u16 val;
130
131 /* stop the timer */
Viresh Kumar7639c0b2015-02-27 13:39:52 +0530132 timer_shutdown(evt);
133
134 period = clk_get_rate(gpt_clk) / HZ;
135 period >>= CTRL_PRESCALER16;
136 writew(period, gpt_base + LOAD(CLKEVT));
137
viresh kumar986435e2010-04-01 12:30:49 +0100138 val = readw(gpt_base + CR(CLKEVT));
Viresh Kumar7639c0b2015-02-27 13:39:52 +0530139 val &= ~CTRL_ONE_SHOT;
140 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
viresh kumar986435e2010-04-01 12:30:49 +0100141 writew(val, gpt_base + CR(CLKEVT));
142
Viresh Kumar7639c0b2015-02-27 13:39:52 +0530143 return 0;
viresh kumar986435e2010-04-01 12:30:49 +0100144}
145
Viresh Kumar7639c0b2015-02-27 13:39:52 +0530146static struct clock_event_device clkevt = {
147 .name = "tmr0",
148 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
149 .set_state_shutdown = spear_shutdown,
150 .set_state_periodic = spear_set_periodic,
151 .set_state_oneshot = spear_set_oneshot,
152 .tick_resume = spear_shutdown,
153 .set_next_event = clockevent_next_event,
154 .shift = 0, /* to be computed */
155};
156
viresh kumar986435e2010-04-01 12:30:49 +0100157static int clockevent_next_event(unsigned long cycles,
158 struct clock_event_device *clk_event_dev)
159{
Gilles Chanteperdrix12021372012-02-24 22:50:50 +0100160 u16 val = readw(gpt_base + CR(CLKEVT));
161
162 if (val & CTRL_ENABLE)
163 writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
viresh kumar986435e2010-04-01 12:30:49 +0100164
165 writew(cycles, gpt_base + LOAD(CLKEVT));
166
viresh kumar986435e2010-04-01 12:30:49 +0100167 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
168 writew(val, gpt_base + CR(CLKEVT));
169
170 return 0;
171}
172
173static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
174{
175 struct clock_event_device *evt = &clkevt;
176
177 writew(INT_STATUS, gpt_base + IR(CLKEVT));
178
179 evt->event_handler(evt);
180
181 return IRQ_HANDLED;
182}
183
184static struct irqaction spear_timer_irq = {
185 .name = "timer",
Michael Opdenacker49710fa2014-03-04 22:09:18 +0100186 .flags = IRQF_TIMER,
viresh kumar986435e2010-04-01 12:30:49 +0100187 .handler = spear_timer_interrupt
188};
189
Arnd Bergmann5019f0b2012-04-11 17:30:11 +0000190static void __init spear_clockevent_init(int irq)
viresh kumar986435e2010-04-01 12:30:49 +0100191{
192 u32 tick_rate;
193
194 /* program the prescaler */
195 writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
196
197 tick_rate = clk_get_rate(gpt_clk);
198 tick_rate >>= CTRL_PRESCALER16;
199
viresh kumar986435e2010-04-01 12:30:49 +0100200 clkevt.cpumask = cpumask_of(0);
201
Shawn Guo838a2ae2013-01-12 11:50:05 +0000202 clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
viresh kumar986435e2010-04-01 12:30:49 +0100203
Arnd Bergmann5019f0b2012-04-11 17:30:11 +0000204 setup_irq(irq, &spear_timer_irq);
viresh kumar986435e2010-04-01 12:30:49 +0100205}
206
Nicolas Pitre19c233b2015-07-27 18:27:52 -0400207static const struct of_device_id const timer_of_match[] __initconst = {
Viresh Kumar30551c02012-04-21 13:15:37 +0530208 { .compatible = "st,spear-timer", },
209 { },
210};
viresh kumar986435e2010-04-01 12:30:49 +0100211
Viresh Kumar30551c02012-04-21 13:15:37 +0530212void __init spear_setup_of_timer(void)
213{
214 struct device_node *np;
215 int irq, ret;
216
217 np = of_find_matching_node(NULL, timer_of_match);
218 if (!np) {
219 pr_err("%s: No timer passed via DT\n", __func__);
viresh kumar986435e2010-04-01 12:30:49 +0100220 return;
221 }
222
Viresh Kumar30551c02012-04-21 13:15:37 +0530223 irq = irq_of_parse_and_map(np, 0);
224 if (!irq) {
225 pr_err("%s: No irq passed for timer via DT\n", __func__);
226 return;
227 }
228
229 gpt_base = of_iomap(np, 0);
viresh kumar986435e2010-04-01 12:30:49 +0100230 if (!gpt_base) {
Viresh Kumar30551c02012-04-21 13:15:37 +0530231 pr_err("%s: of iomap failed\n", __func__);
232 return;
viresh kumar986435e2010-04-01 12:30:49 +0100233 }
234
235 gpt_clk = clk_get_sys("gpt0", NULL);
236 if (!gpt_clk) {
237 pr_err("%s:couldn't get clk for gpt\n", __func__);
238 goto err_iomap;
239 }
240
Viresh Kumarf8abc082012-04-16 13:56:18 +0530241 ret = clk_prepare_enable(gpt_clk);
Shiraz Hashim5c881d92011-02-16 07:40:32 +0100242 if (ret < 0) {
Viresh Kumarf8abc082012-04-16 13:56:18 +0530243 pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
244 goto err_prepare_enable_clk;
viresh kumar986435e2010-04-01 12:30:49 +0100245 }
246
Arnd Bergmann5019f0b2012-04-11 17:30:11 +0000247 spear_clockevent_init(irq);
viresh kumar986435e2010-04-01 12:30:49 +0100248 spear_clocksource_init();
249
250 return;
251
Viresh Kumarf8abc082012-04-16 13:56:18 +0530252err_prepare_enable_clk:
Shiraz Hashim5c881d92011-02-16 07:40:32 +0100253 clk_put(gpt_clk);
viresh kumar986435e2010-04-01 12:30:49 +0100254err_iomap:
255 iounmap(gpt_base);
viresh kumar986435e2010-04-01 12:30:49 +0100256}