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Maxime Ripardb2ac5d72012-11-12 15:07:50 +01001/*
2 * Allwinner A1X SoCs timer handling.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code from
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * Benn Huang <benn@allwinnertech.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqreturn.h>
Maxime Ripard137c6b32013-07-16 16:45:37 +020022#include <linux/sched_clock.h>
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010023#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010026
Maxime Ripard04981732013-03-10 17:03:46 +010027#define TIMER_IRQ_EN_REG 0x00
Maxime Ripard40777642013-07-16 16:45:37 +020028#define TIMER_IRQ_EN(val) BIT(val)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010029#define TIMER_IRQ_ST_REG 0x04
Maxime Ripard04981732013-03-10 17:03:46 +010030#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
Maxime Ripard40777642013-07-16 16:45:37 +020031#define TIMER_CTL_ENABLE BIT(0)
Maxime Ripard9eded232013-07-16 16:45:37 +020032#define TIMER_CTL_RELOAD BIT(1)
Maxime Riparda2c49e72013-07-16 16:45:38 +020033#define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2)
34#define TIMER_CTL_CLK_SRC_OSC24M (1)
35#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
Maxime Ripard40777642013-07-16 16:45:37 +020036#define TIMER_CTL_ONESHOT BIT(7)
Maxime Ripardbb008b92013-07-16 16:45:37 +020037#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
38#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010039
Maxime Ripard12e14802013-10-14 21:07:47 +020040#define TIMER_SYNC_TICKS 3
41
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010042static void __iomem *timer_base;
Maxime Ripard7e141832013-07-16 16:45:38 +020043static u32 ticks_per_jiffy;
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010044
Maxime Ripard63d88f12013-07-16 16:45:38 +020045/*
46 * When we disable a timer, we need to wait at least for 2 cycles of
47 * the timer source clock. We will use for that the clocksource timer
48 * that is already setup and runs at the same frequency than the other
49 * timers, and we never will be disabled.
50 */
51static void sun4i_clkevt_sync(void)
52{
53 u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
54
Maxime Ripard12e14802013-10-14 21:07:47 +020055 while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
Maxime Ripard63d88f12013-07-16 16:45:38 +020056 cpu_relax();
57}
58
Maxime Ripard96651a02013-07-16 16:45:38 +020059static void sun4i_clkevt_time_stop(u8 timer)
60{
61 u32 val = readl(timer_base + TIMER_CTL_REG(timer));
62 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
63 sun4i_clkevt_sync();
64}
65
66static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
67{
68 writel(delay, timer_base + TIMER_INTVAL_REG(timer));
69}
70
71static void sun4i_clkevt_time_start(u8 timer, bool periodic)
72{
73 u32 val = readl(timer_base + TIMER_CTL_REG(timer));
74
75 if (periodic)
76 val &= ~TIMER_CTL_ONESHOT;
77 else
78 val |= TIMER_CTL_ONESHOT;
79
Maxime Ripard7e141832013-07-16 16:45:38 +020080 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
81 timer_base + TIMER_CTL_REG(timer));
Maxime Ripard96651a02013-07-16 16:45:38 +020082}
83
Maxime Ripard119fd632013-03-24 11:49:25 +010084static void sun4i_clkevt_mode(enum clock_event_mode mode,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010085 struct clock_event_device *clk)
86{
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010087 switch (mode) {
88 case CLOCK_EVT_MODE_PERIODIC:
Maxime Ripard96651a02013-07-16 16:45:38 +020089 sun4i_clkevt_time_stop(0);
Maxime Ripard7e141832013-07-16 16:45:38 +020090 sun4i_clkevt_time_setup(0, ticks_per_jiffy);
Maxime Ripard96651a02013-07-16 16:45:38 +020091 sun4i_clkevt_time_start(0, true);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010092 break;
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010093 case CLOCK_EVT_MODE_ONESHOT:
Maxime Ripard96651a02013-07-16 16:45:38 +020094 sun4i_clkevt_time_stop(0);
95 sun4i_clkevt_time_start(0, false);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010096 break;
97 case CLOCK_EVT_MODE_UNUSED:
98 case CLOCK_EVT_MODE_SHUTDOWN:
99 default:
Maxime Ripard96651a02013-07-16 16:45:38 +0200100 sun4i_clkevt_time_stop(0);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100101 break;
102 }
103}
104
Maxime Ripard119fd632013-03-24 11:49:25 +0100105static int sun4i_clkevt_next_event(unsigned long evt,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100106 struct clock_event_device *unused)
107{
Maxime Ripard96651a02013-07-16 16:45:38 +0200108 sun4i_clkevt_time_stop(0);
Maxime Ripard12e14802013-10-14 21:07:47 +0200109 sun4i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
Maxime Ripard96651a02013-07-16 16:45:38 +0200110 sun4i_clkevt_time_start(0, false);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100111
112 return 0;
113}
114
Maxime Ripard119fd632013-03-24 11:49:25 +0100115static struct clock_event_device sun4i_clockevent = {
116 .name = "sun4i_tick",
Maxime Ripard5df9aff2013-11-07 12:01:48 +0100117 .rating = 350,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100118 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
Maxime Ripard119fd632013-03-24 11:49:25 +0100119 .set_mode = sun4i_clkevt_mode,
120 .set_next_event = sun4i_clkevt_next_event,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100121};
122
123
Maxime Ripard119fd632013-03-24 11:49:25 +0100124static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100125{
126 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
127
128 writel(0x1, timer_base + TIMER_IRQ_ST_REG);
129 evt->event_handler(evt);
130
131 return IRQ_HANDLED;
132}
133
Maxime Ripard119fd632013-03-24 11:49:25 +0100134static struct irqaction sun4i_timer_irq = {
135 .name = "sun4i_timer0",
Maxime Ripard33536522013-10-14 21:07:48 +0200136 .flags = IRQF_TIMER | IRQF_IRQPOLL,
Maxime Ripard119fd632013-03-24 11:49:25 +0100137 .handler = sun4i_timer_interrupt,
138 .dev_id = &sun4i_clockevent,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100139};
140
Stephen Boyd662e7232013-11-20 00:47:32 +0100141static u64 notrace sun4i_timer_sched_read(void)
Maxime Ripard137c6b32013-07-16 16:45:37 +0200142{
143 return ~readl(timer_base + TIMER_CNTVAL_REG(1));
144}
145
Maxime Ripard119fd632013-03-24 11:49:25 +0100146static void __init sun4i_timer_init(struct device_node *node)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100147{
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100148 unsigned long rate = 0;
149 struct clk *clk;
150 int ret, irq;
151 u32 val;
152
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100153 timer_base = of_iomap(node, 0);
154 if (!timer_base)
155 panic("Can't map registers");
156
157 irq = irq_of_parse_and_map(node, 0);
158 if (irq <= 0)
159 panic("Can't parse IRQ");
160
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100161 clk = of_clk_get(node, 0);
162 if (IS_ERR(clk))
163 panic("Can't get timer clock");
Maxime Ripard8c31bec2013-07-16 16:45:38 +0200164 clk_prepare_enable(clk);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100165
166 rate = clk_get_rate(clk);
167
Maxime Ripard137c6b32013-07-16 16:45:37 +0200168 writel(~0, timer_base + TIMER_INTVAL_REG(1));
169 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
170 TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
171 timer_base + TIMER_CTL_REG(1));
172
Hans de Goede37b8b002015-03-30 22:17:10 +0200173 /*
174 * sched_clock_register does not have priorities, and on sun6i and
175 * later there is a better sched_clock registered by arm_arch_timer.c
176 */
177 if (of_machine_is_compatible("allwinner,sun4i-a10") ||
178 of_machine_is_compatible("allwinner,sun5i-a13") ||
179 of_machine_is_compatible("allwinner,sun5i-a10s"))
180 sched_clock_register(sun4i_timer_sched_read, 32, rate);
181
Maxime Ripard137c6b32013-07-16 16:45:37 +0200182 clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
Maxime Ripard5df9aff2013-11-07 12:01:48 +0100183 rate, 350, 32, clocksource_mmio_readl_down);
Maxime Ripard137c6b32013-07-16 16:45:37 +0200184
Maxime Ripard7e141832013-07-16 16:45:38 +0200185 ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100186
Maxime Ripard7e141832013-07-16 16:45:38 +0200187 writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
Maxime Riparda2c49e72013-07-16 16:45:38 +0200188 timer_base + TIMER_CTL_REG(0));
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100189
Marc Zyngier6db50bb2013-12-02 09:29:35 +0000190 /* Make sure timer is stopped before playing with interrupts */
191 sun4i_clkevt_time_stop(0);
192
Maxime Ripard6bab4a82014-11-18 23:59:33 +0100193 sun4i_clockevent.cpumask = cpu_possible_mask;
194 sun4i_clockevent.irq = irq;
195
196 clockevents_config_and_register(&sun4i_clockevent, rate,
197 TIMER_SYNC_TICKS, 0xffffffff);
198
Maxime Ripard119fd632013-03-24 11:49:25 +0100199 ret = setup_irq(irq, &sun4i_timer_irq);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100200 if (ret)
201 pr_warn("failed to setup irq %d\n", irq);
202
203 /* Enable timer0 interrupt */
Maxime Ripard04981732013-03-10 17:03:46 +0100204 val = readl(timer_base + TIMER_IRQ_EN_REG);
205 writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100206}
Maxime Ripardec6c0852014-02-06 10:40:31 +0100207CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
Maxime Ripard119fd632013-03-24 11:49:25 +0100208 sun4i_timer_init);