blob: c0304ff608b064b3785af81532fc2b8c7f7f2b30 [file] [log] [blame]
Andrew Victor1a0ed732006-12-01 09:04:47 +01001/*
Andrew Victorad48ce72008-04-16 20:43:49 +01002 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
Andrew Victor1a0ed732006-12-01 09:04:47 +01003 *
4 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5 * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
Andrew Victorad48ce72008-04-16 20:43:49 +01006 * Converted to ClockSource/ClockEvents by David Brownell.
Andrew Victor1a0ed732006-12-01 09:04:47 +01007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
Maxime Ripard52c3ffb2014-07-01 11:33:14 +020012
Maxime Ripardcffbfe62014-07-01 11:33:21 +020013#define pr_fmt(fmt) "AT91: PIT: " fmt
14
Maxime Ripard52c3ffb2014-07-01 11:33:14 +020015#include <linux/clk.h>
16#include <linux/clockchips.h>
Andrew Victor1a0ed732006-12-01 09:04:47 +010017#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/kernel.h>
Jean-Christophe PLAGNIOL-VILLARD23fa6482012-02-27 11:19:34 +010020#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
Maxime Ripard64568d12014-07-01 11:33:23 +020023#include <linux/slab.h>
Andrew Victor1a0ed732006-12-01 09:04:47 +010024
Jean-Christophe PLAGNIOL-VILLARDffe5cd82012-10-30 08:09:09 +080025#define AT91_PIT_MR 0x00 /* Mode Register */
Maxime Ripard52c3ffb2014-07-01 11:33:14 +020026#define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */
27#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
28#define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */
Andrew Victor1a0ed732006-12-01 09:04:47 +010029
Jean-Christophe PLAGNIOL-VILLARDffe5cd82012-10-30 08:09:09 +080030#define AT91_PIT_SR 0x04 /* Status Register */
Maxime Ripard52c3ffb2014-07-01 11:33:14 +020031#define AT91_PIT_PITS BIT(0) /* Timer Status */
Jean-Christophe PLAGNIOL-VILLARDffe5cd82012-10-30 08:09:09 +080032
33#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
34#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
Maxime Ripard52c3ffb2014-07-01 11:33:14 +020035#define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */
36#define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */
Andrew Victor1a0ed732006-12-01 09:04:47 +010037
38#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
39#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
40
Maxime Ripard64568d12014-07-01 11:33:23 +020041struct pit_data {
42 struct clock_event_device clkevt;
43 struct clocksource clksrc;
Andrew Victorad48ce72008-04-16 20:43:49 +010044
Maxime Ripard64568d12014-07-01 11:33:23 +020045 void __iomem *base;
46 u32 cycle;
47 u32 cnt;
48 unsigned int irq;
49 struct clk *mck;
50};
51
52static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc)
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +080053{
Maxime Ripard64568d12014-07-01 11:33:23 +020054 return container_of(clksrc, struct pit_data, clksrc);
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +080055}
56
Maxime Ripard64568d12014-07-01 11:33:23 +020057static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clkevt)
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +080058{
Maxime Ripard64568d12014-07-01 11:33:23 +020059 return container_of(clkevt, struct pit_data, clkevt);
60}
61
62static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
63{
Ben Dooks4806c872015-03-30 22:17:09 +020064 return readl_relaxed(base + reg_offset);
Maxime Ripard64568d12014-07-01 11:33:23 +020065}
66
67static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
68{
Ben Dooks4806c872015-03-30 22:17:09 +020069 writel_relaxed(value, base + reg_offset);
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +080070}
Andrew Victorad48ce72008-04-16 20:43:49 +010071
Andrew Victor1a0ed732006-12-01 09:04:47 +010072/*
Andrew Victorad48ce72008-04-16 20:43:49 +010073 * Clocksource: just a monotonic counter of MCK/16 cycles.
74 * We don't care whether or not PIT irqs are enabled.
Andrew Victor1a0ed732006-12-01 09:04:47 +010075 */
Magnus Damm8e196082009-04-21 12:24:00 -070076static cycle_t read_pit_clk(struct clocksource *cs)
Andrew Victor1a0ed732006-12-01 09:04:47 +010077{
Maxime Ripard64568d12014-07-01 11:33:23 +020078 struct pit_data *data = clksrc_to_pit_data(cs);
Andrew Victorad48ce72008-04-16 20:43:49 +010079 unsigned long flags;
80 u32 elapsed;
81 u32 t;
Andrew Victor1a0ed732006-12-01 09:04:47 +010082
Andrew Victorad48ce72008-04-16 20:43:49 +010083 raw_local_irq_save(flags);
Maxime Ripard64568d12014-07-01 11:33:23 +020084 elapsed = data->cnt;
85 t = pit_read(data->base, AT91_PIT_PIIR);
Andrew Victorad48ce72008-04-16 20:43:49 +010086 raw_local_irq_restore(flags);
Andrew Victor1a0ed732006-12-01 09:04:47 +010087
Maxime Ripard64568d12014-07-01 11:33:23 +020088 elapsed += PIT_PICNT(t) * data->cycle;
Andrew Victorad48ce72008-04-16 20:43:49 +010089 elapsed += PIT_CPIV(t);
90 return elapsed;
Andrew Victor1a0ed732006-12-01 09:04:47 +010091}
92
Andrew Victorad48ce72008-04-16 20:43:49 +010093/*
94 * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
95 */
96static void
97pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
98{
Maxime Ripard64568d12014-07-01 11:33:23 +020099 struct pit_data *data = clkevt_to_pit_data(dev);
100
Andrew Victorad48ce72008-04-16 20:43:49 +0100101 switch (mode) {
102 case CLOCK_EVT_MODE_PERIODIC:
Uwe Kleine-König501d7032009-09-21 09:30:09 +0200103 /* update clocksource counter */
Maxime Ripard64568d12014-07-01 11:33:23 +0200104 data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));
105 pit_write(data->base, AT91_PIT_MR,
106 (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN);
Andrew Victorad48ce72008-04-16 20:43:49 +0100107 break;
108 case CLOCK_EVT_MODE_ONESHOT:
109 BUG();
110 /* FALLTHROUGH */
111 case CLOCK_EVT_MODE_SHUTDOWN:
112 case CLOCK_EVT_MODE_UNUSED:
113 /* disable irq, leaving the clocksource active */
Maxime Ripard64568d12014-07-01 11:33:23 +0200114 pit_write(data->base, AT91_PIT_MR,
115 (data->cycle - 1) | AT91_PIT_PITEN);
Andrew Victorad48ce72008-04-16 20:43:49 +0100116 break;
117 case CLOCK_EVT_MODE_RESUME:
118 break;
119 }
120}
121
Stephen Warren49356ae2012-11-07 16:32:41 -0700122static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
123{
Maxime Ripard64568d12014-07-01 11:33:23 +0200124 struct pit_data *data = clkevt_to_pit_data(cedev);
125
Stephen Warren49356ae2012-11-07 16:32:41 -0700126 /* Disable timer */
Maxime Ripard64568d12014-07-01 11:33:23 +0200127 pit_write(data->base, AT91_PIT_MR, 0);
Stephen Warren49356ae2012-11-07 16:32:41 -0700128}
129
Maxime Ripard64568d12014-07-01 11:33:23 +0200130static void at91sam926x_pit_reset(struct pit_data *data)
Stephen Warren49356ae2012-11-07 16:32:41 -0700131{
132 /* Disable timer and irqs */
Maxime Ripard64568d12014-07-01 11:33:23 +0200133 pit_write(data->base, AT91_PIT_MR, 0);
Stephen Warren49356ae2012-11-07 16:32:41 -0700134
135 /* Clear any pending interrupts, wait for PIT to stop counting */
Maxime Ripard64568d12014-07-01 11:33:23 +0200136 while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0)
Stephen Warren49356ae2012-11-07 16:32:41 -0700137 cpu_relax();
138
139 /* Start PIT but don't enable IRQ */
Maxime Ripard64568d12014-07-01 11:33:23 +0200140 pit_write(data->base, AT91_PIT_MR,
141 (data->cycle - 1) | AT91_PIT_PITEN);
Stephen Warren49356ae2012-11-07 16:32:41 -0700142}
143
144static void at91sam926x_pit_resume(struct clock_event_device *cedev)
145{
Maxime Ripard64568d12014-07-01 11:33:23 +0200146 struct pit_data *data = clkevt_to_pit_data(cedev);
147
148 at91sam926x_pit_reset(data);
Stephen Warren49356ae2012-11-07 16:32:41 -0700149}
150
Andrew Victor1a0ed732006-12-01 09:04:47 +0100151/*
152 * IRQ handler for the timer.
153 */
Andrew Victorad48ce72008-04-16 20:43:49 +0100154static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
Andrew Victor1a0ed732006-12-01 09:04:47 +0100155{
Maxime Ripard64568d12014-07-01 11:33:23 +0200156 struct pit_data *data = dev_id;
157
Uwe Kleine-König501d7032009-09-21 09:30:09 +0200158 /*
159 * irqs should be disabled here, but as the irq is shared they are only
160 * guaranteed to be off if the timer irq is registered first.
161 */
162 WARN_ON_ONCE(!irqs_disabled());
Andrew Victor1a0ed732006-12-01 09:04:47 +0100163
Andrew Victorad48ce72008-04-16 20:43:49 +0100164 /* The PIT interrupt may be disabled, and is shared */
Maxime Ripard64568d12014-07-01 11:33:23 +0200165 if ((data->clkevt.mode == CLOCK_EVT_MODE_PERIODIC) &&
166 (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) {
Andrew Victorad48ce72008-04-16 20:43:49 +0100167 unsigned nr_ticks;
168
169 /* Get number of ticks performed before irq, and ack it */
Maxime Ripard64568d12014-07-01 11:33:23 +0200170 nr_ticks = PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));
Andrew Victor1a0ed732006-12-01 09:04:47 +0100171 do {
Maxime Ripard64568d12014-07-01 11:33:23 +0200172 data->cnt += data->cycle;
173 data->clkevt.event_handler(&data->clkevt);
Andrew Victor1a0ed732006-12-01 09:04:47 +0100174 nr_ticks--;
175 } while (nr_ticks);
176
Andrew Victor1a0ed732006-12-01 09:04:47 +0100177 return IRQ_HANDLED;
Andrew Victorad48ce72008-04-16 20:43:49 +0100178 }
179
180 return IRQ_NONE;
Andrew Victor1a0ed732006-12-01 09:04:47 +0100181}
182
Andrew Victor1a0ed732006-12-01 09:04:47 +0100183/*
Andrew Victorad48ce72008-04-16 20:43:49 +0100184 * Set up both clocksource and clockevent support.
Andrew Victor1a0ed732006-12-01 09:04:47 +0100185 */
Maxime Ripard64568d12014-07-01 11:33:23 +0200186static void __init at91sam926x_pit_common_init(struct pit_data *data)
Andrew Victor1a0ed732006-12-01 09:04:47 +0100187{
Andrew Victorad48ce72008-04-16 20:43:49 +0100188 unsigned long pit_rate;
189 unsigned bits;
Nicolas Ferre986c2652012-02-17 11:54:29 +0100190 int ret;
Andrew Victor1a0ed732006-12-01 09:04:47 +0100191
Andrew Victorad48ce72008-04-16 20:43:49 +0100192 /*
193 * Use our actual MCK to figure out how many MCK/16 ticks per
194 * 1/HZ period (instead of a compile-time constant LATCH).
195 */
Maxime Ripard64568d12014-07-01 11:33:23 +0200196 pit_rate = clk_get_rate(data->mck) / 16;
197 data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ);
198 WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0);
Andrew Victorad48ce72008-04-16 20:43:49 +0100199
200 /* Initialize and enable the timer */
Maxime Ripard64568d12014-07-01 11:33:23 +0200201 at91sam926x_pit_reset(data);
Andrew Victorad48ce72008-04-16 20:43:49 +0100202
203 /*
204 * Register clocksource. The high order bits of PIV are unused,
205 * so this isn't a 32-bit counter unless we get clockevent irqs.
206 */
Maxime Ripard64568d12014-07-01 11:33:23 +0200207 bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */;
208 data->clksrc.mask = CLOCKSOURCE_MASK(bits);
209 data->clksrc.name = "pit";
210 data->clksrc.rating = 175;
211 data->clksrc.read = read_pit_clk,
212 data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS,
213 clocksource_register_hz(&data->clksrc, pit_rate);
Andrew Victorad48ce72008-04-16 20:43:49 +0100214
215 /* Set up irq handler */
Maxime Ripard64568d12014-07-01 11:33:23 +0200216 ret = request_irq(data->irq, at91sam926x_pit_interrupt,
Maxime Ripard7f282e02014-07-01 11:33:22 +0200217 IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
Maxime Ripard64568d12014-07-01 11:33:23 +0200218 "at91_tick", data);
Nicolas Ferre986c2652012-02-17 11:54:29 +0100219 if (ret)
Maxime Ripardcffbfe62014-07-01 11:33:21 +0200220 panic(pr_fmt("Unable to setup IRQ\n"));
Andrew Victorad48ce72008-04-16 20:43:49 +0100221
222 /* Set up and register clockevents */
Maxime Ripard64568d12014-07-01 11:33:23 +0200223 data->clkevt.name = "pit";
224 data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;
225 data->clkevt.shift = 32;
226 data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift);
227 data->clkevt.rating = 100;
228 data->clkevt.cpumask = cpumask_of(0);
229
230 data->clkevt.set_mode = pit_clkevt_mode;
231 data->clkevt.resume = at91sam926x_pit_resume;
232 data->clkevt.suspend = at91sam926x_pit_suspend;
233 clockevents_register_device(&data->clkevt);
Andrew Victor1a0ed732006-12-01 09:04:47 +0100234}
235
Maxime Ripardf807a892014-07-01 11:33:18 +0200236static void __init at91sam926x_pit_dt_init(struct device_node *node)
237{
Maxime Ripard64568d12014-07-01 11:33:23 +0200238 struct pit_data *data;
Maxime Ripardf807a892014-07-01 11:33:18 +0200239
Maxime Ripard64568d12014-07-01 11:33:23 +0200240 data = kzalloc(sizeof(*data), GFP_KERNEL);
241 if (!data)
242 panic(pr_fmt("Unable to allocate memory\n"));
243
244 data->base = of_iomap(node, 0);
245 if (!data->base)
Maxime Ripardcffbfe62014-07-01 11:33:21 +0200246 panic(pr_fmt("Could not map PIT address\n"));
Maxime Ripardf807a892014-07-01 11:33:18 +0200247
Maxime Ripard64568d12014-07-01 11:33:23 +0200248 data->mck = of_clk_get(node, 0);
249 if (IS_ERR(data->mck))
Maxime Ripardf807a892014-07-01 11:33:18 +0200250 /* Fallback on clkdev for !CCF-based boards */
Maxime Ripard64568d12014-07-01 11:33:23 +0200251 data->mck = clk_get(NULL, "mck");
Maxime Ripardf807a892014-07-01 11:33:18 +0200252
Maxime Ripard64568d12014-07-01 11:33:23 +0200253 if (IS_ERR(data->mck))
Maxime Ripardcffbfe62014-07-01 11:33:21 +0200254 panic(pr_fmt("Unable to get mck clk\n"));
Maxime Ripardf807a892014-07-01 11:33:18 +0200255
256 /* Get the interrupts property */
Maxime Ripard64568d12014-07-01 11:33:23 +0200257 data->irq = irq_of_parse_and_map(node, 0);
258 if (!data->irq)
Maxime Ripardcffbfe62014-07-01 11:33:21 +0200259 panic(pr_fmt("Unable to get IRQ from DT\n"));
Maxime Ripardf807a892014-07-01 11:33:18 +0200260
Maxime Ripard64568d12014-07-01 11:33:23 +0200261 at91sam926x_pit_common_init(data);
Maxime Ripardf807a892014-07-01 11:33:18 +0200262}
263CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
264 at91sam926x_pit_dt_init);