blob: 2d59038dec43512e40ca46f4a0989c3b1253e0af [file] [log] [blame]
Juergen Beisertd0f349f2008-07-05 10:02:50 +02001/*
2 * linux/arch/arm/plat-mxc/time.c
3 *
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/clockchips.h>
27#include <linux/clk.h>
Sebastian Andrzej Siewior1119c842014-01-22 12:35:44 +010028#include <linux/delay.h>
Sascha Hauer821dc4d2012-03-09 09:29:27 +010029#include <linux/err.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070030#include <linux/sched_clock.h>
Shawn Guo6dd74782015-05-22 13:53:45 +080031#include <linux/slab.h>
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +020032#include <linux/of.h>
33#include <linux/of_address.h>
34#include <linux/of_irq.h>
Shawn Guo0931aff2015-05-15 11:41:39 +080035#include <soc/imx/timer.h>
Juergen Beisertd0f349f2008-07-05 10:02:50 +020036
Sascha Hauer0f3332c2009-12-04 09:34:51 +010037/*
Shenwei Wang65d0a162015-04-29 16:40:27 -050038 * There are 4 versions of the timer hardware on Freescale MXC hardware.
39 * - MX1/MXL
40 * - MX21, MX27.
41 * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
42 * - MX6DL, MX6SX, MX6Q(rev1.1+)
Sascha Hauer0f3332c2009-12-04 09:34:51 +010043 */
44
Sascha Hauerec996ba2009-02-18 20:58:40 +010045/* defines common for all i.MX */
46#define MXC_TCTL 0x00
Sascha Hauer0f3332c2009-12-04 09:34:51 +010047#define MXC_TCTL_TEN (1 << 0) /* Enable module */
Sascha Hauerec996ba2009-02-18 20:58:40 +010048#define MXC_TPRER 0x04
49
50/* MX1, MX21, MX27 */
51#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
52#define MX1_2_TCTL_IRQEN (1 << 4)
53#define MX1_2_TCTL_FRR (1 << 8)
54#define MX1_2_TCMP 0x08
55#define MX1_2_TCN 0x10
56#define MX1_2_TSTAT 0x14
57
58/* MX21, MX27 */
59#define MX2_TSTAT_CAPT (1 << 1)
60#define MX2_TSTAT_COMP (1 << 0)
61
Anson Huangbad3db12014-09-11 11:29:42 +080062/* MX31, MX35, MX25, MX5, MX6 */
Amit Kucheria38a66f52010-04-21 21:34:36 +030063#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
64#define V2_TCTL_CLK_IPG (1 << 6)
Richard Zhao1f152b42012-05-15 15:34:40 +080065#define V2_TCTL_CLK_PER (2 << 6)
Anson Huangbad3db12014-09-11 11:29:42 +080066#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
Amit Kucheria38a66f52010-04-21 21:34:36 +030067#define V2_TCTL_FRR (1 << 9)
Anson Huangbad3db12014-09-11 11:29:42 +080068#define V2_TCTL_24MEN (1 << 10)
69#define V2_TPRER_PRE24M 12
Amit Kucheria38a66f52010-04-21 21:34:36 +030070#define V2_IR 0x0c
71#define V2_TSTAT 0x08
72#define V2_TSTAT_OF1 (1 << 0)
73#define V2_TCN 0x24
74#define V2_TCMP 0x10
Juergen Beisertd0f349f2008-07-05 10:02:50 +020075
Anson Huangbad3db12014-09-11 11:29:42 +080076#define V2_TIMER_RATE_OSC_DIV8 3000000
77
Shawn Guo6dd74782015-05-22 13:53:45 +080078struct imx_timer {
Shawn Guo0931aff2015-05-15 11:41:39 +080079 enum imx_gpt_type type;
Shawn Guo6dd74782015-05-22 13:53:45 +080080 void __iomem *base;
81 int irq;
82 struct clk *clk_per;
83 struct clk *clk_ipg;
Shawn Guo9c8694b2015-05-15 14:24:41 +080084 const struct imx_gpt_data *gpt;
Shawn Guoe510d202015-05-22 16:38:49 +080085 struct clock_event_device ced;
86 enum clock_event_mode cem;
87 struct irqaction act;
Shawn Guo9c8694b2015-05-15 14:24:41 +080088};
89
90struct imx_gpt_data {
Shawn Guo24f74ad2015-05-22 21:39:55 +080091 int reg_tstat;
92 int reg_tcn;
93 int reg_tcmp;
Shawn Guo9c8694b2015-05-15 14:24:41 +080094 void (*gpt_setup_tctl)(struct imx_timer *imxtm);
Shawn Guodb2ae4b2015-05-22 22:42:55 +080095 void (*gpt_irq_enable)(struct imx_timer *imxtm);
96 void (*gpt_irq_disable)(struct imx_timer *imxtm);
97 void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);
Shawn Guo5ab04752015-05-22 15:51:41 +080098 int (*set_next_event)(unsigned long evt,
99 struct clock_event_device *ced);
Shawn Guo6dd74782015-05-22 13:53:45 +0800100};
101
Shawn Guoe510d202015-05-22 16:38:49 +0800102static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)
103{
104 return container_of(ced, struct imx_timer, ced);
105}
106
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800107static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200108{
Sascha Hauerec996ba2009-02-18 20:58:40 +0100109 unsigned int tmp;
110
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800111 tmp = readl_relaxed(imxtm->base + MXC_TCTL);
112 writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
113}
114#define imx21_gpt_irq_disable imx1_gpt_irq_disable
115
116static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
117{
118 writel_relaxed(0, imxtm->base + V2_IR);
119}
120#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable
121
122static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
123{
124 unsigned int tmp;
125
126 tmp = readl_relaxed(imxtm->base + MXC_TCTL);
127 writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
128}
129#define imx21_gpt_irq_enable imx1_gpt_irq_enable
130
131static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
132{
133 writel_relaxed(1<<0, imxtm->base + V2_IR);
134}
135#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable
136
137static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
138{
139 writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100140}
141
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800142static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
Sascha Hauerec996ba2009-02-18 20:58:40 +0100143{
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800144 writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
Shawn Guo89955522015-05-22 22:23:28 +0800145 imxtm->base + MX1_2_TSTAT);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100146}
147
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800148static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
149{
150 writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
151}
152#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge
153
Russell King234b6ced2011-05-08 14:09:47 +0100154static void __iomem *sched_clock_reg;
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200155
Stephen Boydb93767e2013-11-15 15:26:12 -0800156static u64 notrace mxc_read_sched_clock(void)
Jan Weitzelc124bef2011-03-17 13:44:30 +0100157{
Shawn Guoc7770bb2015-05-19 18:47:47 +0800158 return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
Jan Weitzelc124bef2011-03-17 13:44:30 +0100159}
160
Sebastian Andrzej Siewior1119c842014-01-22 12:35:44 +0100161static struct delay_timer imx_delay_timer;
162
163static unsigned long imx_read_current_timer(void)
164{
Shawn Guoc7770bb2015-05-19 18:47:47 +0800165 return readl_relaxed(sched_clock_reg);
Sebastian Andrzej Siewior1119c842014-01-22 12:35:44 +0100166}
167
Shawn Guo6dd74782015-05-22 13:53:45 +0800168static int __init mxc_clocksource_init(struct imx_timer *imxtm)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200169{
Shawn Guo6dd74782015-05-22 13:53:45 +0800170 unsigned int c = clk_get_rate(imxtm->clk_per);
Shawn Guo24f74ad2015-05-22 21:39:55 +0800171 void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200172
Sebastian Andrzej Siewior1119c842014-01-22 12:35:44 +0100173 imx_delay_timer.read_current_timer = &imx_read_current_timer;
174 imx_delay_timer.freq = c;
175 register_current_timer_delay(&imx_delay_timer);
176
Russell King234b6ced2011-05-08 14:09:47 +0100177 sched_clock_reg = reg;
Sascha Hauerec996ba2009-02-18 20:58:40 +0100178
Stephen Boydb93767e2013-11-15 15:26:12 -0800179 sched_clock_register(mxc_read_sched_clock, 32, c);
Russell King234b6ced2011-05-08 14:09:47 +0100180 return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
181 clocksource_mmio_readl_up);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200182}
183
184/* clock event */
185
Sascha Hauerec996ba2009-02-18 20:58:40 +0100186static int mx1_2_set_next_event(unsigned long evt,
Shawn Guo89955522015-05-22 22:23:28 +0800187 struct clock_event_device *ced)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200188{
Shawn Guo89955522015-05-22 22:23:28 +0800189 struct imx_timer *imxtm = to_imx_timer(ced);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200190 unsigned long tcmp;
191
Shawn Guo89955522015-05-22 22:23:28 +0800192 tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200193
Shawn Guo89955522015-05-22 22:23:28 +0800194 writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100195
Shawn Guo89955522015-05-22 22:23:28 +0800196 return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
Sascha Hauerec996ba2009-02-18 20:58:40 +0100197 -ETIME : 0;
198}
199
Amit Kucheria38a66f52010-04-21 21:34:36 +0300200static int v2_set_next_event(unsigned long evt,
Shawn Guo89955522015-05-22 22:23:28 +0800201 struct clock_event_device *ced)
Sascha Hauerec996ba2009-02-18 20:58:40 +0100202{
Shawn Guo89955522015-05-22 22:23:28 +0800203 struct imx_timer *imxtm = to_imx_timer(ced);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100204 unsigned long tcmp;
205
Shawn Guo89955522015-05-22 22:23:28 +0800206 tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;
Sascha Hauerec996ba2009-02-18 20:58:40 +0100207
Shawn Guo89955522015-05-22 22:23:28 +0800208 writel_relaxed(tcmp, imxtm->base + V2_TCMP);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100209
Shawn Guoeea8e322012-12-06 22:54:41 +0800210 return evt < 0x7fffffff &&
Shawn Guo89955522015-05-22 22:23:28 +0800211 (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200212 -ETIME : 0;
213}
214
215#ifdef DEBUG
216static const char *clock_event_mode_label[] = {
217 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
218 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
219 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
Uwe Kleine-Königde9c5152012-07-16 22:07:06 +0200220 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
221 [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200222};
223#endif /* DEBUG */
224
225static void mxc_set_mode(enum clock_event_mode mode,
Shawn Guoe510d202015-05-22 16:38:49 +0800226 struct clock_event_device *ced)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200227{
Shawn Guoe510d202015-05-22 16:38:49 +0800228 struct imx_timer *imxtm = to_imx_timer(ced);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200229 unsigned long flags;
230
231 /*
232 * The timer interrupt generation is disabled at least
233 * for enough time to call mxc_set_next_event()
234 */
235 local_irq_save(flags);
236
237 /* Disable interrupt in GPT module */
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800238 imxtm->gpt->gpt_irq_disable(imxtm);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200239
Shawn Guoe510d202015-05-22 16:38:49 +0800240 if (mode != imxtm->cem) {
Shawn Guo24f74ad2015-05-22 21:39:55 +0800241 u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200242 /* Set event time into far-far future */
Shawn Guo24f74ad2015-05-22 21:39:55 +0800243 writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
Sascha Hauerec996ba2009-02-18 20:58:40 +0100244
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200245 /* Clear pending interrupt */
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800246 imxtm->gpt->gpt_irq_acknowledge(imxtm);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200247 }
248
249#ifdef DEBUG
250 printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
Shawn Guoe510d202015-05-22 16:38:49 +0800251 clock_event_mode_label[imxtm->cem],
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200252 clock_event_mode_label[mode]);
253#endif /* DEBUG */
254
255 /* Remember timer mode */
Shawn Guoe510d202015-05-22 16:38:49 +0800256 imxtm->cem = mode;
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200257 local_irq_restore(flags);
258
259 switch (mode) {
260 case CLOCK_EVT_MODE_PERIODIC:
261 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
262 "supported for i.MX\n");
263 break;
264 case CLOCK_EVT_MODE_ONESHOT:
265 /*
266 * Do not put overhead of interrupt enable/disable into
267 * mxc_set_next_event(), the core has about 4 minutes
268 * to call mxc_set_next_event() or shutdown clock after
269 * mode switching
270 */
271 local_irq_save(flags);
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800272 imxtm->gpt->gpt_irq_enable(imxtm);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200273 local_irq_restore(flags);
274 break;
275 case CLOCK_EVT_MODE_SHUTDOWN:
276 case CLOCK_EVT_MODE_UNUSED:
277 case CLOCK_EVT_MODE_RESUME:
278 /* Left event sources disabled, no more interrupts appear */
279 break;
280 }
281}
282
283/*
284 * IRQ handler for the timer
285 */
286static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
287{
Shawn Guoe510d202015-05-22 16:38:49 +0800288 struct clock_event_device *ced = dev_id;
Shawn Guo24f74ad2015-05-22 21:39:55 +0800289 struct imx_timer *imxtm = to_imx_timer(ced);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200290 uint32_t tstat;
291
Shawn Guo24f74ad2015-05-22 21:39:55 +0800292 tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200293
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800294 imxtm->gpt->gpt_irq_acknowledge(imxtm);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200295
Shawn Guoe510d202015-05-22 16:38:49 +0800296 ced->event_handler(ced);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200297
298 return IRQ_HANDLED;
299}
300
Shawn Guo6dd74782015-05-22 13:53:45 +0800301static int __init mxc_clockevent_init(struct imx_timer *imxtm)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200302{
Shawn Guoe510d202015-05-22 16:38:49 +0800303 struct clock_event_device *ced = &imxtm->ced;
304 struct irqaction *act = &imxtm->act;
305
306 imxtm->cem = CLOCK_EVT_MODE_UNUSED;
307
308 ced->name = "mxc_timer1";
309 ced->features = CLOCK_EVT_FEAT_ONESHOT;
310 ced->set_mode = mxc_set_mode;
311 ced->set_next_event = imxtm->gpt->set_next_event;
312 ced->rating = 200;
313 ced->cpumask = cpumask_of(0);
314 clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
Shawn Guo838a2ae2013-01-12 11:50:05 +0000315 0xff, 0xfffffffe);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200316
Shawn Guoe510d202015-05-22 16:38:49 +0800317 act->name = "i.MX Timer Tick";
318 act->flags = IRQF_TIMER | IRQF_IRQPOLL;
319 act->handler = mxc_timer_interrupt;
320 act->dev_id = ced;
321
322 return setup_irq(imxtm->irq, act);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200323}
324
Shawn Guo9c8694b2015-05-15 14:24:41 +0800325static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
326{
327 u32 tctl_val;
328
329 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
330 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
331}
332#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl
333
334static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
335{
336 u32 tctl_val;
337
338 tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
339 if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
340 tctl_val |= V2_TCTL_CLK_OSC_DIV8;
341 else
342 tctl_val |= V2_TCTL_CLK_PER;
343
344 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
345}
346
347static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
348{
349 u32 tctl_val;
350
351 tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
352 if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
353 tctl_val |= V2_TCTL_CLK_OSC_DIV8;
354 /* 24 / 8 = 3 MHz */
355 writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
356 tctl_val |= V2_TCTL_24MEN;
357 } else {
358 tctl_val |= V2_TCTL_CLK_PER;
359 }
360
361 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
362}
363
364static const struct imx_gpt_data imx1_gpt_data = {
Shawn Guo24f74ad2015-05-22 21:39:55 +0800365 .reg_tstat = MX1_2_TSTAT,
366 .reg_tcn = MX1_2_TCN,
367 .reg_tcmp = MX1_2_TCMP,
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800368 .gpt_irq_enable = imx1_gpt_irq_enable,
369 .gpt_irq_disable = imx1_gpt_irq_disable,
370 .gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800371 .gpt_setup_tctl = imx1_gpt_setup_tctl,
Shawn Guo5ab04752015-05-22 15:51:41 +0800372 .set_next_event = mx1_2_set_next_event,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800373};
374
375static const struct imx_gpt_data imx21_gpt_data = {
Shawn Guo24f74ad2015-05-22 21:39:55 +0800376 .reg_tstat = MX1_2_TSTAT,
377 .reg_tcn = MX1_2_TCN,
378 .reg_tcmp = MX1_2_TCMP,
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800379 .gpt_irq_enable = imx21_gpt_irq_enable,
380 .gpt_irq_disable = imx21_gpt_irq_disable,
381 .gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800382 .gpt_setup_tctl = imx21_gpt_setup_tctl,
Shawn Guo5ab04752015-05-22 15:51:41 +0800383 .set_next_event = mx1_2_set_next_event,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800384};
385
386static const struct imx_gpt_data imx31_gpt_data = {
Shawn Guo24f74ad2015-05-22 21:39:55 +0800387 .reg_tstat = V2_TSTAT,
388 .reg_tcn = V2_TCN,
389 .reg_tcmp = V2_TCMP,
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800390 .gpt_irq_enable = imx31_gpt_irq_enable,
391 .gpt_irq_disable = imx31_gpt_irq_disable,
392 .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800393 .gpt_setup_tctl = imx31_gpt_setup_tctl,
Shawn Guo5ab04752015-05-22 15:51:41 +0800394 .set_next_event = v2_set_next_event,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800395};
396
397static const struct imx_gpt_data imx6dl_gpt_data = {
Shawn Guo24f74ad2015-05-22 21:39:55 +0800398 .reg_tstat = V2_TSTAT,
399 .reg_tcn = V2_TCN,
400 .reg_tcmp = V2_TCMP,
Shawn Guodb2ae4b2015-05-22 22:42:55 +0800401 .gpt_irq_enable = imx6dl_gpt_irq_enable,
402 .gpt_irq_disable = imx6dl_gpt_irq_disable,
403 .gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800404 .gpt_setup_tctl = imx6dl_gpt_setup_tctl,
Shawn Guo5ab04752015-05-22 15:51:41 +0800405 .set_next_event = v2_set_next_event,
Shawn Guo9c8694b2015-05-15 14:24:41 +0800406};
407
Shawn Guo6dd74782015-05-22 13:53:45 +0800408static void __init _mxc_timer_init(struct imx_timer *imxtm)
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200409{
Shawn Guo9c8694b2015-05-15 14:24:41 +0800410 switch (imxtm->type) {
411 case GPT_TYPE_IMX1:
412 imxtm->gpt = &imx1_gpt_data;
413 break;
414 case GPT_TYPE_IMX21:
415 imxtm->gpt = &imx21_gpt_data;
416 break;
417 case GPT_TYPE_IMX31:
418 imxtm->gpt = &imx31_gpt_data;
419 break;
420 case GPT_TYPE_IMX6DL:
421 imxtm->gpt = &imx6dl_gpt_data;
422 break;
423 default:
424 BUG();
425 }
426
Shawn Guo6dd74782015-05-22 13:53:45 +0800427 if (IS_ERR(imxtm->clk_per)) {
Sascha Hauer2cfb4512012-05-16 12:29:53 +0200428 pr_err("i.MX timer: unable to get clk\n");
429 return;
Sascha Hauer821dc4d2012-03-09 09:29:27 +0100430 }
Sascha Hauerec996ba2009-02-18 20:58:40 +0100431
Shawn Guo6dd74782015-05-22 13:53:45 +0800432 if (!IS_ERR(imxtm->clk_ipg))
433 clk_prepare_enable(imxtm->clk_ipg);
Sascha Hauer2cfb4512012-05-16 12:29:53 +0200434
Shawn Guo6dd74782015-05-22 13:53:45 +0800435 clk_prepare_enable(imxtm->clk_per);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200436
437 /*
438 * Initialise to a known state (all timers off, and timing reset)
439 */
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200440
Shawn Guo6dd74782015-05-22 13:53:45 +0800441 writel_relaxed(0, imxtm->base + MXC_TCTL);
442 writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
Sascha Hauerec996ba2009-02-18 20:58:40 +0100443
Shawn Guo9c8694b2015-05-15 14:24:41 +0800444 imxtm->gpt->gpt_setup_tctl(imxtm);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200445
446 /* init and register the timer to the framework */
Shawn Guo6dd74782015-05-22 13:53:45 +0800447 mxc_clocksource_init(imxtm);
448 mxc_clockevent_init(imxtm);
Juergen Beisertd0f349f2008-07-05 10:02:50 +0200449}
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +0200450
Shawn Guo0931aff2015-05-15 11:41:39 +0800451void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
Alexander Shiyanf4696752014-05-27 13:04:46 +0400452{
Shawn Guo6dd74782015-05-22 13:53:45 +0800453 struct imx_timer *imxtm;
Alexander Shiyanf4696752014-05-27 13:04:46 +0400454
Shawn Guo6dd74782015-05-22 13:53:45 +0800455 imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
456 BUG_ON(!imxtm);
Alexander Shiyand7f98912014-05-27 13:04:47 +0400457
Shawn Guo6dd74782015-05-22 13:53:45 +0800458 imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
459 imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
460
461 imxtm->base = ioremap(pbase, SZ_4K);
462 BUG_ON(!imxtm->base);
463
Shawn Guo0931aff2015-05-15 11:41:39 +0800464 imxtm->type = type;
465
Shawn Guo6dd74782015-05-22 13:53:45 +0800466 _mxc_timer_init(imxtm);
Alexander Shiyanf4696752014-05-27 13:04:46 +0400467}
468
Shawn Guobef11c82015-05-15 13:38:20 +0800469static void __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +0200470{
Shawn Guo6dd74782015-05-22 13:53:45 +0800471 struct imx_timer *imxtm;
472 static int initialized;
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +0200473
Shawn Guo6dd74782015-05-22 13:53:45 +0800474 /* Support one instance only */
475 if (initialized)
Alexander Shiyanfd4959d2014-07-13 09:34:00 +0400476 return;
477
Shawn Guo6dd74782015-05-22 13:53:45 +0800478 imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
479 BUG_ON(!imxtm);
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +0200480
Shawn Guo6dd74782015-05-22 13:53:45 +0800481 imxtm->base = of_iomap(np, 0);
482 WARN_ON(!imxtm->base);
483 imxtm->irq = irq_of_parse_and_map(np, 0);
484
485 imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
Alexander Shiyanf4696752014-05-27 13:04:46 +0400486
Anson Huangbad3db12014-09-11 11:29:42 +0800487 /* Try osc_per first, and fall back to per otherwise */
Shawn Guo6dd74782015-05-22 13:53:45 +0800488 imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
489 if (IS_ERR(imxtm->clk_per))
490 imxtm->clk_per = of_clk_get_by_name(np, "per");
Anson Huangbad3db12014-09-11 11:29:42 +0800491
Shawn Guobef11c82015-05-15 13:38:20 +0800492 imxtm->type = type;
493
Shawn Guo6dd74782015-05-22 13:53:45 +0800494 _mxc_timer_init(imxtm);
495
496 initialized = 1;
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +0200497}
Shawn Guobef11c82015-05-15 13:38:20 +0800498
499static void __init imx1_timer_init_dt(struct device_node *np)
500{
501 mxc_timer_init_dt(np, GPT_TYPE_IMX1);
502}
503
504static void __init imx21_timer_init_dt(struct device_node *np)
505{
506 mxc_timer_init_dt(np, GPT_TYPE_IMX21);
507}
508
509static void __init imx31_timer_init_dt(struct device_node *np)
510{
511 enum imx_gpt_type type = GPT_TYPE_IMX31;
512
513 /*
514 * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
515 * GPT device, while they actually have different programming model.
516 * This is a workaround to keep the existing i.MX6DL/S DTBs continue
517 * working with the new kernel.
518 */
519 if (of_machine_is_compatible("fsl,imx6dl"))
520 type = GPT_TYPE_IMX6DL;
521
522 mxc_timer_init_dt(np, type);
523}
524
525static void __init imx6dl_timer_init_dt(struct device_node *np)
526{
527 mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
528}
529
530CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
531CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
Philippe Reynes747d34e2015-06-27 23:11:44 +0200532CLOCKSOURCE_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
Shawn Guobef11c82015-05-15 13:38:20 +0800533CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
534CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
535CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
536CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
537CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
538CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
539CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
540CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
541CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);