Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-versatile/pci.c |
| 3 | * |
| 4 | * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved. |
| 5 | * You can redistribute and/or modify this software under the terms of version 2 |
| 6 | * of the GNU General Public License as published by the Free Software Foundation. |
| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED |
| 8 | * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 9 | * General Public License for more details. |
| 10 | * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software. |
| 11 | * |
| 12 | * ARM Versatile PCI driver. |
| 13 | * |
| 14 | * 14/04/2005 Initial version, colin.king@philips.com |
| 15 | * |
| 16 | */ |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/pci.h> |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 19 | #include <linux/ioport.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/spinlock.h> |
| 22 | #include <linux/init.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 23 | #include <linux/io.h> |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 24 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 25 | #include <mach/hardware.h> |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 26 | #include <asm/irq.h> |
| 27 | #include <asm/system.h> |
| 28 | #include <asm/mach/pci.h> |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 29 | |
| 30 | /* |
| 31 | * these spaces are mapped using the following base registers: |
| 32 | * |
| 33 | * Usage Local Bus Memory Base/Map registers used |
| 34 | * |
| 35 | * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch |
| 36 | * Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch |
| 37 | * IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO |
| 38 | * Cfg 42000000 - 42FFFFFF PCI config |
| 39 | * |
| 40 | */ |
Al Viro | 399ad77 | 2006-10-11 17:22:34 +0100 | [diff] [blame] | 41 | #define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n)) |
| 42 | #define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL) |
| 43 | #define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0) |
| 44 | #define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4) |
| 45 | #define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8) |
| 46 | #define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10) |
| 47 | #define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14) |
| 48 | #define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18) |
| 49 | #define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc) |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 50 | |
| 51 | #define DEVICE_ID_OFFSET 0x00 |
| 52 | #define CSR_OFFSET 0x04 |
| 53 | #define CLASS_ID_OFFSET 0x08 |
| 54 | |
| 55 | #define VP_PCI_DEVICE_ID 0x030010ee |
| 56 | #define VP_PCI_CLASS_ID 0x0b400000 |
| 57 | |
| 58 | static unsigned long pci_slot_ignore = 0; |
| 59 | |
| 60 | static int __init versatile_pci_slot_ignore(char *str) |
| 61 | { |
| 62 | int retval; |
| 63 | int slot; |
| 64 | |
| 65 | while ((retval = get_option(&str,&slot))) { |
| 66 | if ((slot < 0) || (slot > 31)) { |
| 67 | printk("Illegal slot value: %d\n",slot); |
| 68 | } else { |
| 69 | pci_slot_ignore |= (1 << slot); |
| 70 | } |
| 71 | } |
| 72 | return 1; |
| 73 | } |
| 74 | |
| 75 | __setup("pci_slot_ignore=", versatile_pci_slot_ignore); |
| 76 | |
| 77 | |
Al Viro | 399ad77 | 2006-10-11 17:22:34 +0100 | [diff] [blame] | 78 | static void __iomem *__pci_addr(struct pci_bus *bus, |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 79 | unsigned int devfn, int offset) |
| 80 | { |
| 81 | unsigned int busnr = bus->number; |
| 82 | |
| 83 | /* |
| 84 | * Trap out illegal values |
| 85 | */ |
| 86 | if (offset > 255) |
| 87 | BUG(); |
| 88 | if (busnr > 255) |
| 89 | BUG(); |
| 90 | if (devfn > 255) |
| 91 | BUG(); |
| 92 | |
Al Viro | 399ad77 | 2006-10-11 17:22:34 +0100 | [diff] [blame] | 93 | return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) | |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 94 | (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset); |
| 95 | } |
| 96 | |
| 97 | static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where, |
| 98 | int size, u32 *val) |
| 99 | { |
Al Viro | 399ad77 | 2006-10-11 17:22:34 +0100 | [diff] [blame] | 100 | void __iomem *addr = __pci_addr(bus, devfn, where & ~3); |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 101 | u32 v; |
| 102 | int slot = PCI_SLOT(devfn); |
| 103 | |
| 104 | if (pci_slot_ignore & (1 << slot)) { |
| 105 | /* Ignore this slot */ |
| 106 | switch (size) { |
| 107 | case 1: |
| 108 | v = 0xff; |
| 109 | break; |
| 110 | case 2: |
| 111 | v = 0xffff; |
| 112 | break; |
| 113 | default: |
| 114 | v = 0xffffffff; |
| 115 | } |
| 116 | } else { |
| 117 | switch (size) { |
| 118 | case 1: |
Andrzej Zaborowski | 756813c | 2007-06-26 14:31:23 +0100 | [diff] [blame] | 119 | v = __raw_readl(addr); |
| 120 | if (where & 2) v >>= 16; |
| 121 | if (where & 1) v >>= 8; |
| 122 | v &= 0xff; |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 123 | break; |
| 124 | |
| 125 | case 2: |
Al Viro | 399ad77 | 2006-10-11 17:22:34 +0100 | [diff] [blame] | 126 | v = __raw_readl(addr); |
| 127 | if (where & 2) v >>= 16; |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 128 | v &= 0xffff; |
| 129 | break; |
| 130 | |
| 131 | default: |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 132 | v = __raw_readl(addr); |
| 133 | break; |
| 134 | } |
| 135 | } |
| 136 | |
| 137 | *val = v; |
| 138 | return PCIBIOS_SUCCESSFUL; |
| 139 | } |
| 140 | |
| 141 | static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where, |
| 142 | int size, u32 val) |
| 143 | { |
Al Viro | 399ad77 | 2006-10-11 17:22:34 +0100 | [diff] [blame] | 144 | void __iomem *addr = __pci_addr(bus, devfn, where); |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 145 | int slot = PCI_SLOT(devfn); |
| 146 | |
| 147 | if (pci_slot_ignore & (1 << slot)) { |
| 148 | return PCIBIOS_SUCCESSFUL; |
| 149 | } |
| 150 | |
| 151 | switch (size) { |
| 152 | case 1: |
| 153 | __raw_writeb((u8)val, addr); |
| 154 | break; |
| 155 | |
| 156 | case 2: |
| 157 | __raw_writew((u16)val, addr); |
| 158 | break; |
| 159 | |
| 160 | case 4: |
| 161 | __raw_writel(val, addr); |
| 162 | break; |
| 163 | } |
| 164 | |
| 165 | return PCIBIOS_SUCCESSFUL; |
| 166 | } |
| 167 | |
| 168 | static struct pci_ops pci_versatile_ops = { |
| 169 | .read = versatile_read_config, |
| 170 | .write = versatile_write_config, |
| 171 | }; |
| 172 | |
| 173 | static struct resource io_mem = { |
| 174 | .name = "PCI I/O space", |
| 175 | .start = VERSATILE_PCI_MEM_BASE0, |
| 176 | .end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1, |
| 177 | .flags = IORESOURCE_IO, |
| 178 | }; |
| 179 | |
| 180 | static struct resource non_mem = { |
| 181 | .name = "PCI non-prefetchable", |
| 182 | .start = VERSATILE_PCI_MEM_BASE1, |
| 183 | .end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1, |
| 184 | .flags = IORESOURCE_MEM, |
| 185 | }; |
| 186 | |
| 187 | static struct resource pre_mem = { |
| 188 | .name = "PCI prefetchable", |
| 189 | .start = VERSATILE_PCI_MEM_BASE2, |
| 190 | .end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1, |
| 191 | .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, |
| 192 | }; |
| 193 | |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 194 | static int __init pci_versatile_setup_resources(struct list_head *resources) |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 195 | { |
| 196 | int ret = 0; |
| 197 | |
| 198 | ret = request_resource(&iomem_resource, &io_mem); |
| 199 | if (ret) { |
| 200 | printk(KERN_ERR "PCI: unable to allocate I/O " |
| 201 | "memory region (%d)\n", ret); |
| 202 | goto out; |
| 203 | } |
| 204 | ret = request_resource(&iomem_resource, &non_mem); |
| 205 | if (ret) { |
| 206 | printk(KERN_ERR "PCI: unable to allocate non-prefetchable " |
| 207 | "memory region (%d)\n", ret); |
| 208 | goto release_io_mem; |
| 209 | } |
| 210 | ret = request_resource(&iomem_resource, &pre_mem); |
| 211 | if (ret) { |
| 212 | printk(KERN_ERR "PCI: unable to allocate prefetchable " |
| 213 | "memory region (%d)\n", ret); |
| 214 | goto release_non_mem; |
| 215 | } |
| 216 | |
| 217 | /* |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 218 | * the IO resource for this bus |
| 219 | * the mem resource for this bus |
| 220 | * the prefetch mem resource for this bus |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 221 | */ |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 222 | pci_add_resource(resources, &io_mem); |
| 223 | pci_add_resource(resources, &non_mem); |
| 224 | pci_add_resource(resources, &pre_mem); |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 225 | |
| 226 | goto out; |
| 227 | |
| 228 | release_non_mem: |
| 229 | release_resource(&non_mem); |
| 230 | release_io_mem: |
| 231 | release_resource(&io_mem); |
| 232 | out: |
| 233 | return ret; |
| 234 | } |
| 235 | |
| 236 | int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) |
| 237 | { |
| 238 | int ret = 0; |
| 239 | int i; |
| 240 | int myslot = -1; |
| 241 | unsigned long val; |
Catalin Marinas | c27a216 | 2006-02-22 19:51:38 +0000 | [diff] [blame] | 242 | void __iomem *local_pci_cfg_base; |
| 243 | |
| 244 | val = __raw_readl(SYS_PCICTL); |
| 245 | if (!(val & 1)) { |
| 246 | printk("Not plugged into PCI backplane!\n"); |
| 247 | ret = -EIO; |
| 248 | goto out; |
| 249 | } |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 250 | |
| 251 | if (nr == 0) { |
| 252 | sys->mem_offset = 0; |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 253 | ret = pci_versatile_setup_resources(&sys->resources); |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 254 | if (ret < 0) { |
| 255 | printk("pci_versatile_setup: resources... oops?\n"); |
| 256 | goto out; |
| 257 | } |
| 258 | } else { |
| 259 | printk("pci_versatile_setup: resources... nr == 0??\n"); |
| 260 | goto out; |
| 261 | } |
| 262 | |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 263 | /* |
| 264 | * We need to discover the PCI core first to configure itself |
| 265 | * before the main PCI probing is performed |
| 266 | */ |
Catalin Marinas | c27a216 | 2006-02-22 19:51:38 +0000 | [diff] [blame] | 267 | for (i=0; i<32; i++) |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 268 | if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) && |
| 269 | (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) { |
| 270 | myslot = i; |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 271 | break; |
| 272 | } |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 273 | |
| 274 | if (myslot == -1) { |
| 275 | printk("Cannot find PCI core!\n"); |
| 276 | ret = -EIO; |
Catalin Marinas | c27a216 | 2006-02-22 19:51:38 +0000 | [diff] [blame] | 277 | goto out; |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 278 | } |
| 279 | |
Catalin Marinas | c27a216 | 2006-02-22 19:51:38 +0000 | [diff] [blame] | 280 | printk("PCI core found (slot %d)\n",myslot); |
| 281 | |
| 282 | __raw_writel(myslot, PCI_SELFID); |
Al Viro | 399ad77 | 2006-10-11 17:22:34 +0100 | [diff] [blame] | 283 | local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11); |
Catalin Marinas | c27a216 | 2006-02-22 19:51:38 +0000 | [diff] [blame] | 284 | |
| 285 | val = __raw_readl(local_pci_cfg_base + CSR_OFFSET); |
| 286 | val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; |
| 287 | __raw_writel(val, local_pci_cfg_base + CSR_OFFSET); |
| 288 | |
| 289 | /* |
| 290 | * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM |
| 291 | */ |
| 292 | __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0); |
| 293 | __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1); |
| 294 | __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2); |
| 295 | |
| 296 | /* |
| 297 | * Do not to map Versatile FPGA PCI device into memory space |
| 298 | */ |
| 299 | pci_slot_ignore |= (1 << myslot); |
| 300 | ret = 1; |
| 301 | |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 302 | out: |
| 303 | return ret; |
| 304 | } |
| 305 | |
| 306 | |
Russell King | a3e5bb4 | 2010-07-27 08:59:55 +0100 | [diff] [blame] | 307 | struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys) |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 308 | { |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 309 | return pci_scan_root_bus(NULL, sys->busnr, &pci_versatile_ops, sys, |
| 310 | &sys->resources); |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 311 | } |
| 312 | |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 313 | void __init pci_versatile_preinit(void) |
| 314 | { |
Rob Herring | c9d95fb | 2011-06-28 21:16:13 -0500 | [diff] [blame] | 315 | pcibios_min_io = 0x44000000; |
| 316 | pcibios_min_mem = 0x50000000; |
| 317 | |
Catalin Marinas | c27a216 | 2006-02-22 19:51:38 +0000 | [diff] [blame] | 318 | __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0); |
| 319 | __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1); |
| 320 | __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2); |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 321 | |
Catalin Marinas | c27a216 | 2006-02-22 19:51:38 +0000 | [diff] [blame] | 322 | __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0); |
| 323 | __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1); |
| 324 | __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2); |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 325 | |
Catalin Marinas | c27a216 | 2006-02-22 19:51:38 +0000 | [diff] [blame] | 326 | __raw_writel(1, SYS_PCICTL); |
| 327 | } |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 328 | |
| 329 | /* |
| 330 | * map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this. |
| 331 | */ |
Ralf Baechle | d534194 | 2011-06-10 15:30:21 +0100 | [diff] [blame] | 332 | static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 333 | { |
| 334 | int irq; |
| 335 | int devslot = PCI_SLOT(dev->devfn); |
| 336 | |
Catalin Marinas | c27a216 | 2006-02-22 19:51:38 +0000 | [diff] [blame] | 337 | /* slot, pin, irq |
| 338 | * 24 1 27 |
| 339 | * 25 1 28 |
| 340 | * 26 1 29 |
| 341 | * 27 1 30 |
| 342 | */ |
| 343 | irq = 27 + ((slot + pin - 1) & 3); |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 344 | |
Catalin Marinas | c27a216 | 2006-02-22 19:51:38 +0000 | [diff] [blame] | 345 | printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq); |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 346 | |
| 347 | return irq; |
| 348 | } |
| 349 | |
| 350 | static struct hw_pci versatile_pci __initdata = { |
| 351 | .swizzle = NULL, |
| 352 | .map_irq = versatile_map_irq, |
| 353 | .nr_controllers = 1, |
| 354 | .setup = pci_versatile_setup, |
| 355 | .scan = pci_versatile_scan_bus, |
| 356 | .preinit = pci_versatile_preinit, |
Catalin Marinas | c0da085 | 2005-06-20 18:51:06 +0100 | [diff] [blame] | 357 | }; |
| 358 | |
| 359 | static int __init versatile_pci_init(void) |
| 360 | { |
| 361 | pci_common_init(&versatile_pci); |
| 362 | return 0; |
| 363 | } |
| 364 | |
| 365 | subsys_initcall(versatile_pci_init); |