Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 1 | /* |
| 2 | * General Purpose functions for the global management of the |
| 3 | * Communication Processor Module. |
| 4 | * Copyright (c) 1997 Dan error_act (dmalek@jlc.net) |
| 5 | * |
| 6 | * In addition to the individual control of the communication |
| 7 | * channels, there are a few functions that globally affect the |
| 8 | * communication processor. |
| 9 | * |
| 10 | * Buffer descriptors must be allocated from the dual ported memory |
| 11 | * space. The allocator for that is here. When the communication |
| 12 | * process is reset, we reclaim the memory available. There is |
| 13 | * currently no deallocator for this memory. |
| 14 | * The amount of space available is platform dependent. On the |
| 15 | * MBX, the EPPC software loads additional microcode into the |
| 16 | * communication processor, and uses some of the DP ram for this |
| 17 | * purpose. Current, the first 512 bytes and the last 256 bytes of |
| 18 | * memory are used. Right now I am conservative and only use the |
| 19 | * memory that can never be used for microcode. If there are |
| 20 | * applications that require more DP ram, we can expand the boundaries |
| 21 | * but then we have to be careful of any downloaded microcode. |
| 22 | */ |
| 23 | #include <linux/errno.h> |
| 24 | #include <linux/sched.h> |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/dma-mapping.h> |
| 27 | #include <linux/param.h> |
| 28 | #include <linux/string.h> |
| 29 | #include <linux/mm.h> |
| 30 | #include <linux/interrupt.h> |
| 31 | #include <linux/irq.h> |
| 32 | #include <linux/module.h> |
| 33 | #include <asm/mpc8xx.h> |
| 34 | #include <asm/page.h> |
| 35 | #include <asm/pgtable.h> |
| 36 | #include <asm/8xx_immap.h> |
| 37 | #include <asm/commproc.h> |
| 38 | #include <asm/io.h> |
| 39 | #include <asm/tlbflush.h> |
| 40 | #include <asm/rheap.h> |
| 41 | #include <asm/prom.h> |
| 42 | |
| 43 | #include <asm/fs_pd.h> |
| 44 | |
| 45 | #define CPM_MAP_SIZE (0x4000) |
| 46 | |
| 47 | static void m8xx_cpm_dpinit(void); |
Scott Wood | 4b218e9 | 2007-08-21 02:36:19 +1000 | [diff] [blame] | 48 | static uint host_buffer; /* One page of host buffer */ |
| 49 | static uint host_end; /* end + 1 */ |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 50 | cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */ |
| 51 | immap_t __iomem *mpc8xx_immr; |
| 52 | static cpic8xx_t __iomem *cpic_reg; |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 53 | |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 54 | static struct irq_host *cpm_pic_host; |
| 55 | |
| 56 | static void cpm_mask_irq(unsigned int irq) |
| 57 | { |
| 58 | unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq; |
| 59 | |
| 60 | clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); |
| 61 | } |
| 62 | |
| 63 | static void cpm_unmask_irq(unsigned int irq) |
| 64 | { |
| 65 | unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq; |
| 66 | |
| 67 | setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); |
| 68 | } |
| 69 | |
| 70 | static void cpm_end_irq(unsigned int irq) |
| 71 | { |
| 72 | unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq; |
| 73 | |
| 74 | out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec)); |
| 75 | } |
| 76 | |
| 77 | static struct irq_chip cpm_pic = { |
| 78 | .typename = " CPM PIC ", |
| 79 | .mask = cpm_mask_irq, |
| 80 | .unmask = cpm_unmask_irq, |
| 81 | .eoi = cpm_end_irq, |
| 82 | }; |
| 83 | |
| 84 | int cpm_get_irq(void) |
| 85 | { |
| 86 | int cpm_vec; |
| 87 | |
| 88 | /* Get the vector by setting the ACK bit and then reading |
| 89 | * the register. |
| 90 | */ |
| 91 | out_be16(&cpic_reg->cpic_civr, 1); |
| 92 | cpm_vec = in_be16(&cpic_reg->cpic_civr); |
| 93 | cpm_vec >>= 11; |
| 94 | |
| 95 | return irq_linear_revmap(cpm_pic_host, cpm_vec); |
| 96 | } |
| 97 | |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 98 | static int cpm_pic_host_map(struct irq_host *h, unsigned int virq, |
| 99 | irq_hw_number_t hw) |
| 100 | { |
| 101 | pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); |
| 102 | |
| 103 | get_irq_desc(virq)->status |= IRQ_LEVEL; |
| 104 | set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | /* The CPM can generate the error interrupt when there is a race condition |
| 109 | * between generating and masking interrupts. All we have to do is ACK it |
| 110 | * and return. This is a no-op function so we don't need any special |
| 111 | * tests in the interrupt handler. |
| 112 | */ |
Scott Wood | 4b218e9 | 2007-08-21 02:36:19 +1000 | [diff] [blame] | 113 | static irqreturn_t cpm_error_interrupt(int irq, void *dev) |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 114 | { |
| 115 | return IRQ_HANDLED; |
| 116 | } |
| 117 | |
| 118 | static struct irqaction cpm_error_irqaction = { |
| 119 | .handler = cpm_error_interrupt, |
| 120 | .mask = CPU_MASK_NONE, |
| 121 | .name = "error", |
| 122 | }; |
| 123 | |
| 124 | static struct irq_host_ops cpm_pic_host_ops = { |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 125 | .map = cpm_pic_host_map, |
| 126 | }; |
| 127 | |
| 128 | unsigned int cpm_pic_init(void) |
| 129 | { |
| 130 | struct device_node *np = NULL; |
| 131 | struct resource res; |
| 132 | unsigned int sirq = NO_IRQ, hwirq, eirq; |
| 133 | int ret; |
| 134 | |
| 135 | pr_debug("cpm_pic_init\n"); |
| 136 | |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 137 | np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic"); |
| 138 | if (np == NULL) |
| 139 | np = of_find_compatible_node(NULL, "cpm-pic", "CPM"); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 140 | if (np == NULL) { |
| 141 | printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n"); |
| 142 | return sirq; |
| 143 | } |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 144 | |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 145 | ret = of_address_to_resource(np, 0, &res); |
| 146 | if (ret) |
| 147 | goto end; |
| 148 | |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 149 | cpic_reg = ioremap(res.start, res.end - res.start + 1); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 150 | if (cpic_reg == NULL) |
| 151 | goto end; |
| 152 | |
| 153 | sirq = irq_of_parse_and_map(np, 0); |
| 154 | if (sirq == NO_IRQ) |
| 155 | goto end; |
| 156 | |
| 157 | /* Initialize the CPM interrupt controller. */ |
| 158 | hwirq = (unsigned int)irq_map[sirq].hwirq; |
| 159 | out_be32(&cpic_reg->cpic_cicr, |
| 160 | (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | |
| 161 | ((hwirq/2) << 13) | CICR_HP_MASK); |
| 162 | |
| 163 | out_be32(&cpic_reg->cpic_cimr, 0); |
| 164 | |
Michael Ellerman | 52964f8 | 2007-08-28 18:47:54 +1000 | [diff] [blame] | 165 | cpm_pic_host = irq_alloc_host(of_node_get(np), IRQ_HOST_MAP_LINEAR, |
| 166 | 64, &cpm_pic_host_ops, 64); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 167 | if (cpm_pic_host == NULL) { |
| 168 | printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n"); |
| 169 | sirq = NO_IRQ; |
| 170 | goto end; |
| 171 | } |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 172 | |
| 173 | /* Install our own error handler. */ |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 174 | np = of_find_compatible_node(NULL, NULL, "fsl,cpm1"); |
| 175 | if (np == NULL) |
| 176 | np = of_find_node_by_type(NULL, "cpm"); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 177 | if (np == NULL) { |
| 178 | printk(KERN_ERR "CPM PIC init: can not find cpm node\n"); |
| 179 | goto end; |
| 180 | } |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 181 | |
Scott Wood | 4b218e9 | 2007-08-21 02:36:19 +1000 | [diff] [blame] | 182 | eirq = irq_of_parse_and_map(np, 0); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 183 | if (eirq == NO_IRQ) |
| 184 | goto end; |
| 185 | |
| 186 | if (setup_irq(eirq, &cpm_error_irqaction)) |
| 187 | printk(KERN_ERR "Could not allocate CPM error IRQ!"); |
| 188 | |
| 189 | setbits32(&cpic_reg->cpic_cicr, CICR_IEN); |
| 190 | |
| 191 | end: |
| 192 | of_node_put(np); |
| 193 | return sirq; |
| 194 | } |
| 195 | |
| 196 | void cpm_reset(void) |
| 197 | { |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 198 | sysconf8xx_t __iomem *siu_conf; |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 199 | |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 200 | mpc8xx_immr = ioremap(get_immrbase(), 0x4000); |
| 201 | if (!mpc8xx_immr) { |
| 202 | printk(KERN_CRIT "Could not map IMMR\n"); |
| 203 | return; |
| 204 | } |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 205 | |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 206 | cpmp = &mpc8xx_immr->im_cpm; |
| 207 | |
| 208 | #ifndef CONFIG_PPC_EARLY_DEBUG_CPM |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 209 | /* Perform a reset. |
| 210 | */ |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 211 | out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 212 | |
| 213 | /* Wait for it. |
| 214 | */ |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 215 | while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG); |
| 216 | #endif |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 217 | |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 218 | #ifdef CONFIG_UCODE_PATCH |
| 219 | cpm_load_patch(cpmp); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 220 | #endif |
| 221 | |
| 222 | /* Set SDMA Bus Request priority 5. |
| 223 | * On 860T, this also enables FEC priority 6. I am not sure |
| 224 | * this is what we realy want for some applications, but the |
| 225 | * manual recommends it. |
| 226 | * Bit 25, FAM can also be set to use FEC aggressive mode (860T). |
| 227 | */ |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 228 | siu_conf = immr_map(im_siu_conf); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 229 | out_be32(&siu_conf->sc_sdcr, 1); |
| 230 | immr_unmap(siu_conf); |
| 231 | |
| 232 | /* Reclaim the DP memory for our use. */ |
| 233 | m8xx_cpm_dpinit(); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 234 | } |
| 235 | |
| 236 | /* We used to do this earlier, but have to postpone as long as possible |
| 237 | * to ensure the kernel VM is now running. |
| 238 | */ |
| 239 | static void |
| 240 | alloc_host_memory(void) |
| 241 | { |
| 242 | dma_addr_t physaddr; |
| 243 | |
| 244 | /* Set the host page for allocation. |
| 245 | */ |
| 246 | host_buffer = (uint)dma_alloc_coherent(NULL, PAGE_SIZE, &physaddr, |
| 247 | GFP_KERNEL); |
| 248 | host_end = host_buffer + PAGE_SIZE; |
| 249 | } |
| 250 | |
| 251 | /* We also own one page of host buffer space for the allocation of |
| 252 | * UART "fifos" and the like. |
| 253 | */ |
| 254 | uint |
| 255 | m8xx_cpm_hostalloc(uint size) |
| 256 | { |
| 257 | uint retloc; |
| 258 | |
| 259 | if (host_buffer == 0) |
| 260 | alloc_host_memory(); |
| 261 | |
| 262 | if ((host_buffer + size) >= host_end) |
| 263 | return(0); |
| 264 | |
| 265 | retloc = host_buffer; |
| 266 | host_buffer += size; |
| 267 | |
| 268 | return(retloc); |
| 269 | } |
| 270 | |
| 271 | /* Set a baud rate generator. This needs lots of work. There are |
| 272 | * four BRGs, any of which can be wired to any channel. |
| 273 | * The internal baud rate clock is the system clock divided by 16. |
| 274 | * This assumes the baudrate is 16x oversampled by the uart. |
| 275 | */ |
| 276 | #define BRG_INT_CLK (get_brgfreq()) |
| 277 | #define BRG_UART_CLK (BRG_INT_CLK/16) |
| 278 | #define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16) |
| 279 | |
| 280 | void |
| 281 | cpm_setbrg(uint brg, uint rate) |
| 282 | { |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 283 | u32 __iomem *bp; |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 284 | |
| 285 | /* This is good enough to get SMCs running..... |
| 286 | */ |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 287 | bp = &cpmp->cp_brgc1; |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 288 | bp += brg; |
| 289 | /* The BRG has a 12-bit counter. For really slow baud rates (or |
| 290 | * really fast processors), we may have to further divide by 16. |
| 291 | */ |
| 292 | if (((BRG_UART_CLK / rate) - 1) < 4096) |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 293 | out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 294 | else |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 295 | out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) | |
| 296 | CPM_BRG_EN | CPM_BRG_DIV16); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | /* |
| 300 | * dpalloc / dpfree bits. |
| 301 | */ |
| 302 | static spinlock_t cpm_dpmem_lock; |
| 303 | /* |
| 304 | * 16 blocks should be enough to satisfy all requests |
| 305 | * until the memory subsystem goes up... |
| 306 | */ |
| 307 | static rh_block_t cpm_boot_dpmem_rh_block[16]; |
| 308 | static rh_info_t cpm_dpmem_info; |
| 309 | |
| 310 | #define CPM_DPMEM_ALIGNMENT 8 |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 311 | static u8 __iomem *dpram_vbase; |
| 312 | static phys_addr_t dpram_pbase; |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 313 | |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 314 | static void m8xx_cpm_dpinit(void) |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 315 | { |
| 316 | spin_lock_init(&cpm_dpmem_lock); |
| 317 | |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 318 | dpram_vbase = cpmp->cp_dpmem; |
| 319 | dpram_pbase = get_immrbase() + offsetof(immap_t, im_cpm.cp_dpmem); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 320 | |
| 321 | /* Initialize the info header */ |
| 322 | rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT, |
| 323 | sizeof(cpm_boot_dpmem_rh_block) / |
| 324 | sizeof(cpm_boot_dpmem_rh_block[0]), |
| 325 | cpm_boot_dpmem_rh_block); |
| 326 | |
| 327 | /* |
| 328 | * Attach the usable dpmem area. |
| 329 | * XXX: This is actually crap. CPM_DATAONLY_BASE and |
| 330 | * CPM_DATAONLY_SIZE are a subset of the available dparm. It varies |
| 331 | * with the processor and the microcode patches applied / activated. |
| 332 | * But the following should be at least safe. |
| 333 | */ |
Timur Tabi | 4c35630 | 2007-05-08 14:46:36 -0500 | [diff] [blame] | 334 | rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | /* |
| 338 | * Allocate the requested size worth of DP memory. |
| 339 | * This function returns an offset into the DPRAM area. |
| 340 | * Use cpm_dpram_addr() to get the virtual address of the area. |
| 341 | */ |
Timur Tabi | 4c35630 | 2007-05-08 14:46:36 -0500 | [diff] [blame] | 342 | unsigned long cpm_dpalloc(uint size, uint align) |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 343 | { |
Timur Tabi | 4c35630 | 2007-05-08 14:46:36 -0500 | [diff] [blame] | 344 | unsigned long start; |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 345 | unsigned long flags; |
| 346 | |
| 347 | spin_lock_irqsave(&cpm_dpmem_lock, flags); |
| 348 | cpm_dpmem_info.alignment = align; |
| 349 | start = rh_alloc(&cpm_dpmem_info, size, "commproc"); |
| 350 | spin_unlock_irqrestore(&cpm_dpmem_lock, flags); |
| 351 | |
| 352 | return (uint)start; |
| 353 | } |
| 354 | EXPORT_SYMBOL(cpm_dpalloc); |
| 355 | |
Timur Tabi | 4c35630 | 2007-05-08 14:46:36 -0500 | [diff] [blame] | 356 | int cpm_dpfree(unsigned long offset) |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 357 | { |
| 358 | int ret; |
| 359 | unsigned long flags; |
| 360 | |
| 361 | spin_lock_irqsave(&cpm_dpmem_lock, flags); |
Timur Tabi | 4c35630 | 2007-05-08 14:46:36 -0500 | [diff] [blame] | 362 | ret = rh_free(&cpm_dpmem_info, offset); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 363 | spin_unlock_irqrestore(&cpm_dpmem_lock, flags); |
| 364 | |
| 365 | return ret; |
| 366 | } |
| 367 | EXPORT_SYMBOL(cpm_dpfree); |
| 368 | |
Timur Tabi | 4c35630 | 2007-05-08 14:46:36 -0500 | [diff] [blame] | 369 | unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align) |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 370 | { |
Timur Tabi | 4c35630 | 2007-05-08 14:46:36 -0500 | [diff] [blame] | 371 | unsigned long start; |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 372 | unsigned long flags; |
| 373 | |
| 374 | spin_lock_irqsave(&cpm_dpmem_lock, flags); |
| 375 | cpm_dpmem_info.alignment = align; |
Timur Tabi | 4c35630 | 2007-05-08 14:46:36 -0500 | [diff] [blame] | 376 | start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc"); |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 377 | spin_unlock_irqrestore(&cpm_dpmem_lock, flags); |
| 378 | |
Timur Tabi | 4c35630 | 2007-05-08 14:46:36 -0500 | [diff] [blame] | 379 | return start; |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 380 | } |
| 381 | EXPORT_SYMBOL(cpm_dpalloc_fixed); |
| 382 | |
| 383 | void cpm_dpdump(void) |
| 384 | { |
| 385 | rh_dump(&cpm_dpmem_info); |
| 386 | } |
| 387 | EXPORT_SYMBOL(cpm_dpdump); |
| 388 | |
Timur Tabi | 4c35630 | 2007-05-08 14:46:36 -0500 | [diff] [blame] | 389 | void *cpm_dpram_addr(unsigned long offset) |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 390 | { |
| 391 | return (void *)(dpram_vbase + offset); |
| 392 | } |
| 393 | EXPORT_SYMBOL(cpm_dpram_addr); |
| 394 | |
Scott Wood | fb533d0 | 2007-09-14 14:22:36 -0500 | [diff] [blame] | 395 | uint cpm_dpram_phys(u8 *addr) |
Vitaly Bordug | f2a0bd3 | 2007-01-24 22:41:24 +0300 | [diff] [blame] | 396 | { |
| 397 | return (dpram_pbase + (uint)(addr - dpram_vbase)); |
| 398 | } |
Jochen Friedrich | 83af919 | 2007-09-24 19:13:46 +0200 | [diff] [blame] | 399 | EXPORT_SYMBOL(cpm_dpram_phys); |
Scott Wood | 663edbd | 2007-07-16 17:22:01 -0500 | [diff] [blame] | 400 | |
| 401 | struct cpm_ioport16 { |
| 402 | __be16 dir, par, sor, dat, intr; |
| 403 | __be16 res[3]; |
| 404 | }; |
| 405 | |
| 406 | struct cpm_ioport32 { |
| 407 | __be32 dir, par, sor; |
| 408 | }; |
| 409 | |
| 410 | static void cpm1_set_pin32(int port, int pin, int flags) |
| 411 | { |
| 412 | struct cpm_ioport32 __iomem *iop; |
| 413 | pin = 1 << (31 - pin); |
| 414 | |
| 415 | if (port == CPM_PORTB) |
| 416 | iop = (struct cpm_ioport32 __iomem *) |
| 417 | &mpc8xx_immr->im_cpm.cp_pbdir; |
| 418 | else |
| 419 | iop = (struct cpm_ioport32 __iomem *) |
| 420 | &mpc8xx_immr->im_cpm.cp_pedir; |
| 421 | |
| 422 | if (flags & CPM_PIN_OUTPUT) |
| 423 | setbits32(&iop->dir, pin); |
| 424 | else |
| 425 | clrbits32(&iop->dir, pin); |
| 426 | |
| 427 | if (!(flags & CPM_PIN_GPIO)) |
| 428 | setbits32(&iop->par, pin); |
| 429 | else |
| 430 | clrbits32(&iop->par, pin); |
| 431 | |
| 432 | if (port == CPM_PORTE) { |
| 433 | if (flags & CPM_PIN_SECONDARY) |
| 434 | setbits32(&iop->sor, pin); |
| 435 | else |
| 436 | clrbits32(&iop->sor, pin); |
| 437 | |
| 438 | if (flags & CPM_PIN_OPENDRAIN) |
| 439 | setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); |
| 440 | else |
| 441 | clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); |
| 442 | } |
| 443 | } |
| 444 | |
| 445 | static void cpm1_set_pin16(int port, int pin, int flags) |
| 446 | { |
| 447 | struct cpm_ioport16 __iomem *iop = |
| 448 | (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport; |
| 449 | |
| 450 | pin = 1 << (15 - pin); |
| 451 | |
| 452 | if (port != 0) |
| 453 | iop += port - 1; |
| 454 | |
| 455 | if (flags & CPM_PIN_OUTPUT) |
| 456 | setbits16(&iop->dir, pin); |
| 457 | else |
| 458 | clrbits16(&iop->dir, pin); |
| 459 | |
| 460 | if (!(flags & CPM_PIN_GPIO)) |
| 461 | setbits16(&iop->par, pin); |
| 462 | else |
| 463 | clrbits16(&iop->par, pin); |
| 464 | |
| 465 | if (port == CPM_PORTC) { |
| 466 | if (flags & CPM_PIN_SECONDARY) |
| 467 | setbits16(&iop->sor, pin); |
| 468 | else |
| 469 | clrbits16(&iop->sor, pin); |
| 470 | } |
| 471 | } |
| 472 | |
| 473 | void cpm1_set_pin(enum cpm_port port, int pin, int flags) |
| 474 | { |
| 475 | if (port == CPM_PORTB || port == CPM_PORTE) |
| 476 | cpm1_set_pin32(port, pin, flags); |
| 477 | else |
| 478 | cpm1_set_pin16(port, pin, flags); |
| 479 | } |
| 480 | |
| 481 | int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode) |
| 482 | { |
| 483 | int shift; |
| 484 | int i, bits = 0; |
| 485 | u32 __iomem *reg; |
| 486 | u32 mask = 7; |
| 487 | |
| 488 | u8 clk_map[][3] = { |
| 489 | {CPM_CLK_SCC1, CPM_BRG1, 0}, |
| 490 | {CPM_CLK_SCC1, CPM_BRG2, 1}, |
| 491 | {CPM_CLK_SCC1, CPM_BRG3, 2}, |
| 492 | {CPM_CLK_SCC1, CPM_BRG4, 3}, |
| 493 | {CPM_CLK_SCC1, CPM_CLK1, 4}, |
| 494 | {CPM_CLK_SCC1, CPM_CLK2, 5}, |
| 495 | {CPM_CLK_SCC1, CPM_CLK3, 6}, |
| 496 | {CPM_CLK_SCC1, CPM_CLK4, 7}, |
| 497 | |
| 498 | {CPM_CLK_SCC2, CPM_BRG1, 0}, |
| 499 | {CPM_CLK_SCC2, CPM_BRG2, 1}, |
| 500 | {CPM_CLK_SCC2, CPM_BRG3, 2}, |
| 501 | {CPM_CLK_SCC2, CPM_BRG4, 3}, |
| 502 | {CPM_CLK_SCC2, CPM_CLK1, 4}, |
| 503 | {CPM_CLK_SCC2, CPM_CLK2, 5}, |
| 504 | {CPM_CLK_SCC2, CPM_CLK3, 6}, |
| 505 | {CPM_CLK_SCC2, CPM_CLK4, 7}, |
| 506 | |
| 507 | {CPM_CLK_SCC3, CPM_BRG1, 0}, |
| 508 | {CPM_CLK_SCC3, CPM_BRG2, 1}, |
| 509 | {CPM_CLK_SCC3, CPM_BRG3, 2}, |
| 510 | {CPM_CLK_SCC3, CPM_BRG4, 3}, |
| 511 | {CPM_CLK_SCC3, CPM_CLK5, 4}, |
| 512 | {CPM_CLK_SCC3, CPM_CLK6, 5}, |
| 513 | {CPM_CLK_SCC3, CPM_CLK7, 6}, |
| 514 | {CPM_CLK_SCC3, CPM_CLK8, 7}, |
| 515 | |
| 516 | {CPM_CLK_SCC4, CPM_BRG1, 0}, |
| 517 | {CPM_CLK_SCC4, CPM_BRG2, 1}, |
| 518 | {CPM_CLK_SCC4, CPM_BRG3, 2}, |
| 519 | {CPM_CLK_SCC4, CPM_BRG4, 3}, |
| 520 | {CPM_CLK_SCC4, CPM_CLK5, 4}, |
| 521 | {CPM_CLK_SCC4, CPM_CLK6, 5}, |
| 522 | {CPM_CLK_SCC4, CPM_CLK7, 6}, |
| 523 | {CPM_CLK_SCC4, CPM_CLK8, 7}, |
| 524 | |
| 525 | {CPM_CLK_SMC1, CPM_BRG1, 0}, |
| 526 | {CPM_CLK_SMC1, CPM_BRG2, 1}, |
| 527 | {CPM_CLK_SMC1, CPM_BRG3, 2}, |
| 528 | {CPM_CLK_SMC1, CPM_BRG4, 3}, |
| 529 | {CPM_CLK_SMC1, CPM_CLK1, 4}, |
| 530 | {CPM_CLK_SMC1, CPM_CLK2, 5}, |
| 531 | {CPM_CLK_SMC1, CPM_CLK3, 6}, |
| 532 | {CPM_CLK_SMC1, CPM_CLK4, 7}, |
| 533 | |
| 534 | {CPM_CLK_SMC2, CPM_BRG1, 0}, |
| 535 | {CPM_CLK_SMC2, CPM_BRG2, 1}, |
| 536 | {CPM_CLK_SMC2, CPM_BRG3, 2}, |
| 537 | {CPM_CLK_SMC2, CPM_BRG4, 3}, |
| 538 | {CPM_CLK_SMC2, CPM_CLK5, 4}, |
| 539 | {CPM_CLK_SMC2, CPM_CLK6, 5}, |
| 540 | {CPM_CLK_SMC2, CPM_CLK7, 6}, |
| 541 | {CPM_CLK_SMC2, CPM_CLK8, 7}, |
| 542 | }; |
| 543 | |
| 544 | switch (target) { |
| 545 | case CPM_CLK_SCC1: |
| 546 | reg = &mpc8xx_immr->im_cpm.cp_sicr; |
| 547 | shift = 0; |
| 548 | break; |
| 549 | |
| 550 | case CPM_CLK_SCC2: |
| 551 | reg = &mpc8xx_immr->im_cpm.cp_sicr; |
| 552 | shift = 8; |
| 553 | break; |
| 554 | |
| 555 | case CPM_CLK_SCC3: |
| 556 | reg = &mpc8xx_immr->im_cpm.cp_sicr; |
| 557 | shift = 16; |
| 558 | break; |
| 559 | |
| 560 | case CPM_CLK_SCC4: |
| 561 | reg = &mpc8xx_immr->im_cpm.cp_sicr; |
| 562 | shift = 24; |
| 563 | break; |
| 564 | |
| 565 | case CPM_CLK_SMC1: |
| 566 | reg = &mpc8xx_immr->im_cpm.cp_simode; |
| 567 | shift = 12; |
| 568 | break; |
| 569 | |
| 570 | case CPM_CLK_SMC2: |
| 571 | reg = &mpc8xx_immr->im_cpm.cp_simode; |
| 572 | shift = 28; |
| 573 | break; |
| 574 | |
| 575 | default: |
| 576 | printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n"); |
| 577 | return -EINVAL; |
| 578 | } |
| 579 | |
| 580 | if (reg == &mpc8xx_immr->im_cpm.cp_sicr && mode == CPM_CLK_RX) |
| 581 | shift += 3; |
| 582 | |
| 583 | for (i = 0; i < ARRAY_SIZE(clk_map); i++) { |
| 584 | if (clk_map[i][0] == target && clk_map[i][1] == clock) { |
| 585 | bits = clk_map[i][2]; |
| 586 | break; |
| 587 | } |
| 588 | } |
| 589 | |
| 590 | if (i == ARRAY_SIZE(clk_map)) { |
| 591 | printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n"); |
| 592 | return -EINVAL; |
| 593 | } |
| 594 | |
| 595 | bits <<= shift; |
| 596 | mask <<= shift; |
| 597 | out_be32(reg, (in_be32(reg) & ~mask) | bits); |
| 598 | |
| 599 | return 0; |
| 600 | } |