Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2012, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _LINUX_CORESIGHT_H |
| 14 | #define _LINUX_CORESIGHT_H |
| 15 | |
| 16 | #include <linux/device.h> |
| 17 | |
| 18 | /* Peripheral id registers (0xFD0-0xFEC) */ |
| 19 | #define CORESIGHT_PERIPHIDR4 0xfd0 |
| 20 | #define CORESIGHT_PERIPHIDR5 0xfd4 |
| 21 | #define CORESIGHT_PERIPHIDR6 0xfd8 |
| 22 | #define CORESIGHT_PERIPHIDR7 0xfdC |
| 23 | #define CORESIGHT_PERIPHIDR0 0xfe0 |
| 24 | #define CORESIGHT_PERIPHIDR1 0xfe4 |
| 25 | #define CORESIGHT_PERIPHIDR2 0xfe8 |
| 26 | #define CORESIGHT_PERIPHIDR3 0xfeC |
| 27 | /* Component id registers (0xFF0-0xFFC) */ |
| 28 | #define CORESIGHT_COMPIDR0 0xff0 |
| 29 | #define CORESIGHT_COMPIDR1 0xff4 |
| 30 | #define CORESIGHT_COMPIDR2 0xff8 |
| 31 | #define CORESIGHT_COMPIDR3 0xffC |
| 32 | |
| 33 | #define ETM_ARCH_V3_3 0x23 |
| 34 | #define ETM_ARCH_V3_5 0x25 |
| 35 | #define PFT_ARCH_V1_0 0x30 |
| 36 | #define PFT_ARCH_V1_1 0x31 |
| 37 | |
| 38 | #define CORESIGHT_UNLOCK 0xc5acce55 |
| 39 | |
| 40 | extern struct bus_type coresight_bustype; |
| 41 | |
| 42 | enum coresight_dev_type { |
| 43 | CORESIGHT_DEV_TYPE_NONE, |
| 44 | CORESIGHT_DEV_TYPE_SINK, |
| 45 | CORESIGHT_DEV_TYPE_LINK, |
| 46 | CORESIGHT_DEV_TYPE_LINKSINK, |
| 47 | CORESIGHT_DEV_TYPE_SOURCE, |
| 48 | }; |
| 49 | |
| 50 | enum coresight_dev_subtype_sink { |
| 51 | CORESIGHT_DEV_SUBTYPE_SINK_NONE, |
| 52 | CORESIGHT_DEV_SUBTYPE_SINK_PORT, |
| 53 | CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, |
| 54 | }; |
| 55 | |
| 56 | enum coresight_dev_subtype_link { |
| 57 | CORESIGHT_DEV_SUBTYPE_LINK_NONE, |
| 58 | CORESIGHT_DEV_SUBTYPE_LINK_MERG, |
| 59 | CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, |
| 60 | CORESIGHT_DEV_SUBTYPE_LINK_FIFO, |
| 61 | }; |
| 62 | |
| 63 | enum coresight_dev_subtype_source { |
| 64 | CORESIGHT_DEV_SUBTYPE_SOURCE_NONE, |
| 65 | CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, |
| 66 | CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, |
| 67 | CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, |
| 68 | }; |
| 69 | |
| 70 | /** |
| 71 | * struct coresight_dev_subtype - further characterisation of a type |
| 72 | * @sink_subtype: type of sink this component is, as defined |
| 73 | by @coresight_dev_subtype_sink. |
| 74 | * @link_subtype: type of link this component is, as defined |
| 75 | by @coresight_dev_subtype_link. |
| 76 | * @source_subtype: type of source this component is, as defined |
| 77 | by @coresight_dev_subtype_source. |
| 78 | */ |
| 79 | struct coresight_dev_subtype { |
| 80 | enum coresight_dev_subtype_sink sink_subtype; |
| 81 | enum coresight_dev_subtype_link link_subtype; |
| 82 | enum coresight_dev_subtype_source source_subtype; |
| 83 | }; |
| 84 | |
| 85 | /** |
| 86 | * struct coresight_platform_data - data harvested from the DT specification |
| 87 | * @cpu: the CPU a source belongs to. Only applicable for ETM/PTMs. |
| 88 | * @name: name of the component as shown under sysfs. |
| 89 | * @nr_inport: number of input ports for this component. |
Pankaj Dubey | 8ee885a | 2014-11-13 14:12:48 +0530 | [diff] [blame] | 90 | * @outports: list of remote endpoint port number. |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 91 | * @child_names:name of all child components connected to this device. |
| 92 | * @child_ports:child component port number the current component is |
| 93 | connected to. |
| 94 | * @nr_outport: number of output ports for this component. |
| 95 | * @clk: The clock this component is associated to. |
| 96 | */ |
| 97 | struct coresight_platform_data { |
| 98 | int cpu; |
| 99 | const char *name; |
| 100 | int nr_inport; |
| 101 | int *outports; |
| 102 | const char **child_names; |
| 103 | int *child_ports; |
| 104 | int nr_outport; |
| 105 | struct clk *clk; |
| 106 | }; |
| 107 | |
| 108 | /** |
| 109 | * struct coresight_desc - description of a component required from drivers |
| 110 | * @type: as defined by @coresight_dev_type. |
| 111 | * @subtype: as defined by @coresight_dev_subtype. |
| 112 | * @ops: generic operations for this component, as defined |
| 113 | by @coresight_ops. |
| 114 | * @pdata: platform data collected from DT. |
| 115 | * @dev: The device entity associated to this component. |
Pankaj Dubey | 8ee885a | 2014-11-13 14:12:48 +0530 | [diff] [blame] | 116 | * @groups: operations specific to this component. These will end up |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 117 | in the component's sysfs sub-directory. |
| 118 | */ |
| 119 | struct coresight_desc { |
| 120 | enum coresight_dev_type type; |
| 121 | struct coresight_dev_subtype subtype; |
| 122 | const struct coresight_ops *ops; |
| 123 | struct coresight_platform_data *pdata; |
| 124 | struct device *dev; |
| 125 | const struct attribute_group **groups; |
| 126 | }; |
| 127 | |
| 128 | /** |
| 129 | * struct coresight_connection - representation of a single connection |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 130 | * @outport: a connection's output port number. |
| 131 | * @chid_name: remote component's name. |
| 132 | * @child_port: remote component's port number @output is connected to. |
| 133 | * @child_dev: a @coresight_device representation of the component |
| 134 | connected to @outport. |
| 135 | */ |
| 136 | struct coresight_connection { |
| 137 | int outport; |
| 138 | const char *child_name; |
| 139 | int child_port; |
| 140 | struct coresight_device *child_dev; |
| 141 | }; |
| 142 | |
| 143 | /** |
| 144 | * struct coresight_device - representation of a device as used by the framework |
Pankaj Dubey | 8ee885a | 2014-11-13 14:12:48 +0530 | [diff] [blame] | 145 | * @conns: array of coresight_connections associated to this component. |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 146 | * @nr_inport: number of input port associated to this component. |
| 147 | * @nr_outport: number of output port associated to this component. |
| 148 | * @type: as defined by @coresight_dev_type. |
| 149 | * @subtype: as defined by @coresight_dev_subtype. |
| 150 | * @ops: generic operations for this component, as defined |
| 151 | by @coresight_ops. |
| 152 | * @dev: The device entity associated to this component. |
| 153 | * @refcnt: keep track of what is in use. |
| 154 | * @path_link: link of current component into the path being enabled. |
| 155 | * @orphan: true if the component has connections that haven't been linked. |
| 156 | * @enable: 'true' if component is currently part of an active path. |
| 157 | * @activated: 'true' only if a _sink_ has been activated. A sink can be |
| 158 | activated but not yet enabled. Enabling for a _sink_ |
| 159 | happens when a source has been selected for that it. |
| 160 | */ |
| 161 | struct coresight_device { |
| 162 | struct coresight_connection *conns; |
| 163 | int nr_inport; |
| 164 | int nr_outport; |
| 165 | enum coresight_dev_type type; |
| 166 | struct coresight_dev_subtype subtype; |
| 167 | const struct coresight_ops *ops; |
| 168 | struct device dev; |
| 169 | atomic_t *refcnt; |
| 170 | struct list_head path_link; |
| 171 | bool orphan; |
| 172 | bool enable; /* true only if configured as part of a path */ |
| 173 | bool activated; /* true only if a sink is part of a path */ |
| 174 | }; |
| 175 | |
| 176 | #define to_coresight_device(d) container_of(d, struct coresight_device, dev) |
| 177 | |
| 178 | #define source_ops(csdev) csdev->ops->source_ops |
| 179 | #define sink_ops(csdev) csdev->ops->sink_ops |
| 180 | #define link_ops(csdev) csdev->ops->link_ops |
| 181 | |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 182 | /** |
| 183 | * struct coresight_ops_sink - basic operations for a sink |
| 184 | * Operations available for sinks |
| 185 | * @enable: enables the sink. |
| 186 | * @disable: disables the sink. |
| 187 | */ |
| 188 | struct coresight_ops_sink { |
| 189 | int (*enable)(struct coresight_device *csdev); |
| 190 | void (*disable)(struct coresight_device *csdev); |
| 191 | }; |
| 192 | |
| 193 | /** |
| 194 | * struct coresight_ops_link - basic operations for a link |
| 195 | * Operations available for links. |
| 196 | * @enable: enables flow between iport and oport. |
| 197 | * @disable: disables flow between iport and oport. |
| 198 | */ |
| 199 | struct coresight_ops_link { |
| 200 | int (*enable)(struct coresight_device *csdev, int iport, int oport); |
| 201 | void (*disable)(struct coresight_device *csdev, int iport, int oport); |
| 202 | }; |
| 203 | |
| 204 | /** |
| 205 | * struct coresight_ops_source - basic operations for a source |
| 206 | * Operations available for sources. |
| 207 | * @trace_id: returns the value of the component's trace ID as known |
| 208 | to the HW. |
| 209 | * @enable: enables tracing from a source. |
| 210 | * @disable: disables tracing for a source. |
| 211 | */ |
| 212 | struct coresight_ops_source { |
| 213 | int (*trace_id)(struct coresight_device *csdev); |
| 214 | int (*enable)(struct coresight_device *csdev); |
| 215 | void (*disable)(struct coresight_device *csdev); |
| 216 | }; |
| 217 | |
| 218 | struct coresight_ops { |
| 219 | const struct coresight_ops_sink *sink_ops; |
| 220 | const struct coresight_ops_link *link_ops; |
| 221 | const struct coresight_ops_source *source_ops; |
| 222 | }; |
| 223 | |
| 224 | #ifdef CONFIG_CORESIGHT |
| 225 | extern struct coresight_device * |
| 226 | coresight_register(struct coresight_desc *desc); |
| 227 | extern void coresight_unregister(struct coresight_device *csdev); |
| 228 | extern int coresight_enable(struct coresight_device *csdev); |
| 229 | extern void coresight_disable(struct coresight_device *csdev); |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 230 | extern int coresight_timeout(void __iomem *addr, u32 offset, |
| 231 | int position, int value); |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 232 | #else |
| 233 | static inline struct coresight_device * |
| 234 | coresight_register(struct coresight_desc *desc) { return NULL; } |
| 235 | static inline void coresight_unregister(struct coresight_device *csdev) {} |
| 236 | static inline int |
| 237 | coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } |
| 238 | static inline void coresight_disable(struct coresight_device *csdev) {} |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 239 | static inline int coresight_timeout(void __iomem *addr, u32 offset, |
| 240 | int position, int value) { return 1; } |
Mathieu Poirier | c61c4b5 | 2015-01-09 16:57:20 -0700 | [diff] [blame] | 241 | #endif |
| 242 | |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 243 | #ifdef CONFIG_OF |
Mathieu Poirier | c61c4b5 | 2015-01-09 16:57:20 -0700 | [diff] [blame] | 244 | extern struct coresight_platform_data *of_get_coresight_platform_data( |
| 245 | struct device *dev, struct device_node *node); |
| 246 | #else |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 247 | static inline struct coresight_platform_data *of_get_coresight_platform_data( |
| 248 | struct device *dev, struct device_node *node) { return NULL; } |
| 249 | #endif |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 250 | |
| 251 | #endif |