Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1 | /* |
| 2 | * MUSB OTG driver host support |
| 3 | * |
| 4 | * Copyright 2005 Mentor Graphics Corporation |
| 5 | * Copyright (C) 2005-2006 by Texas Instruments |
| 6 | * Copyright (C) 2006-2007 Nokia Corporation |
Sergei Shtylyov | c7bbc05 | 2009-03-26 18:26:40 -0700 | [diff] [blame] | 7 | * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * version 2 as published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 21 | * 02110-1301 USA |
| 22 | * |
| 23 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 26 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 33 | * |
| 34 | */ |
| 35 | |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/kernel.h> |
| 38 | #include <linux/delay.h> |
| 39 | #include <linux/sched.h> |
| 40 | #include <linux/slab.h> |
| 41 | #include <linux/errno.h> |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 42 | #include <linux/list.h> |
Maulik Mankad | 496dda7 | 2010-09-24 13:44:06 +0300 | [diff] [blame] | 43 | #include <linux/dma-mapping.h> |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 44 | |
| 45 | #include "musb_core.h" |
| 46 | #include "musb_host.h" |
| 47 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 48 | /* MUSB HOST status 22-mar-2006 |
| 49 | * |
| 50 | * - There's still lots of partial code duplication for fault paths, so |
| 51 | * they aren't handled as consistently as they need to be. |
| 52 | * |
| 53 | * - PIO mostly behaved when last tested. |
| 54 | * + including ep0, with all usbtest cases 9, 10 |
| 55 | * + usbtest 14 (ep0out) doesn't seem to run at all |
| 56 | * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest |
| 57 | * configurations, but otherwise double buffering passes basic tests. |
| 58 | * + for 2.6.N, for N > ~10, needs API changes for hcd framework. |
| 59 | * |
| 60 | * - DMA (CPPI) ... partially behaves, not currently recommended |
| 61 | * + about 1/15 the speed of typical EHCI implementations (PCI) |
| 62 | * + RX, all too often reqpkt seems to misbehave after tx |
| 63 | * + TX, no known issues (other than evident silicon issue) |
| 64 | * |
| 65 | * - DMA (Mentor/OMAP) ...has at least toggle update problems |
| 66 | * |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 67 | * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet |
| 68 | * starvation ... nothing yet for TX, interrupt, or bulk. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 69 | * |
| 70 | * - Not tested with HNP, but some SRP paths seem to behave. |
| 71 | * |
| 72 | * NOTE 24-August-2006: |
| 73 | * |
| 74 | * - Bulk traffic finally uses both sides of hardware ep1, freeing up an |
| 75 | * extra endpoint for periodic use enabling hub + keybd + mouse. That |
| 76 | * mostly works, except that with "usbnet" it's easy to trigger cases |
| 77 | * with "ping" where RX loses. (a) ping to davinci, even "ping -f", |
| 78 | * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses |
| 79 | * although ARP RX wins. (That test was done with a full speed link.) |
| 80 | */ |
| 81 | |
| 82 | |
| 83 | /* |
| 84 | * NOTE on endpoint usage: |
| 85 | * |
| 86 | * CONTROL transfers all go through ep0. BULK ones go through dedicated IN |
| 87 | * and OUT endpoints ... hardware is dedicated for those "async" queue(s). |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 88 | * (Yes, bulk _could_ use more of the endpoints than that, and would even |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 89 | * benefit from it.) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 90 | * |
| 91 | * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. |
| 92 | * So far that scheduling is both dumb and optimistic: the endpoint will be |
| 93 | * "claimed" until its software queue is no longer refilled. No multiplexing |
| 94 | * of transfers between endpoints, or anything clever. |
| 95 | */ |
| 96 | |
Daniel Mack | 74c2e93 | 2013-04-10 21:55:45 +0200 | [diff] [blame] | 97 | struct musb *hcd_to_musb(struct usb_hcd *hcd) |
| 98 | { |
| 99 | return *(struct musb **) hcd->hcd_priv; |
| 100 | } |
| 101 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 102 | |
| 103 | static void musb_ep_program(struct musb *musb, u8 epnum, |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 104 | struct urb *urb, int is_out, |
| 105 | u8 *buf, u32 offset, u32 len); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 106 | |
| 107 | /* |
| 108 | * Clear TX fifo. Needed to avoid BABBLE errors. |
| 109 | */ |
David Brownell | c767c1c | 2008-09-11 11:53:23 +0300 | [diff] [blame] | 110 | static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 111 | { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 112 | struct musb *musb = ep->musb; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 113 | void __iomem *epio = ep->regs; |
| 114 | u16 csr; |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 115 | u16 lastcsr = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 116 | int retries = 1000; |
| 117 | |
| 118 | csr = musb_readw(epio, MUSB_TXCSR); |
| 119 | while (csr & MUSB_TXCSR_FIFONOTEMPTY) { |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 120 | if (csr != lastcsr) |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 121 | dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 122 | lastcsr = csr; |
Daniel Mack | 2ccc6d3 | 2014-05-26 14:52:37 +0200 | [diff] [blame] | 123 | csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 124 | musb_writew(epio, MUSB_TXCSR, csr); |
| 125 | csr = musb_readw(epio, MUSB_TXCSR); |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 126 | if (WARN(retries-- < 1, |
| 127 | "Could not flush host TX%d fifo: csr: %04x\n", |
| 128 | ep->epnum, csr)) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 129 | return; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 130 | mdelay(1); |
| 131 | } |
| 132 | } |
| 133 | |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 134 | static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) |
| 135 | { |
| 136 | void __iomem *epio = ep->regs; |
| 137 | u16 csr; |
| 138 | int retries = 5; |
| 139 | |
| 140 | /* scrub any data left in the fifo */ |
| 141 | do { |
| 142 | csr = musb_readw(epio, MUSB_TXCSR); |
| 143 | if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) |
| 144 | break; |
| 145 | musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); |
| 146 | csr = musb_readw(epio, MUSB_TXCSR); |
| 147 | udelay(10); |
| 148 | } while (--retries); |
| 149 | |
| 150 | WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", |
| 151 | ep->epnum, csr); |
| 152 | |
| 153 | /* and reset for the next transfer */ |
| 154 | musb_writew(epio, MUSB_TXCSR, 0); |
| 155 | } |
| 156 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 157 | /* |
| 158 | * Start transmit. Caller is responsible for locking shared resources. |
| 159 | * musb must be locked. |
| 160 | */ |
| 161 | static inline void musb_h_tx_start(struct musb_hw_ep *ep) |
| 162 | { |
| 163 | u16 txcsr; |
| 164 | |
| 165 | /* NOTE: no locks here; caller should lock and select EP */ |
| 166 | if (ep->epnum) { |
| 167 | txcsr = musb_readw(ep->regs, MUSB_TXCSR); |
| 168 | txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; |
| 169 | musb_writew(ep->regs, MUSB_TXCSR, txcsr); |
| 170 | } else { |
| 171 | txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; |
| 172 | musb_writew(ep->regs, MUSB_CSR0, txcsr); |
| 173 | } |
| 174 | |
| 175 | } |
| 176 | |
Sergei Shtylyov | c7bbc05 | 2009-03-26 18:26:40 -0700 | [diff] [blame] | 177 | static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 178 | { |
| 179 | u16 txcsr; |
| 180 | |
| 181 | /* NOTE: no locks here; caller should lock and select EP */ |
| 182 | txcsr = musb_readw(ep->regs, MUSB_TXCSR); |
| 183 | txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; |
Sergei Shtylyov | c7bbc05 | 2009-03-26 18:26:40 -0700 | [diff] [blame] | 184 | if (is_cppi_enabled()) |
| 185 | txcsr |= MUSB_TXCSR_DMAMODE; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 186 | musb_writew(ep->regs, MUSB_TXCSR, txcsr); |
| 187 | } |
| 188 | |
Sergei Shtylyov | 3e5c6dc | 2009-03-27 12:55:16 -0700 | [diff] [blame] | 189 | static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh) |
| 190 | { |
| 191 | if (is_in != 0 || ep->is_shared_fifo) |
| 192 | ep->in_qh = qh; |
| 193 | if (is_in == 0 || ep->is_shared_fifo) |
| 194 | ep->out_qh = qh; |
| 195 | } |
| 196 | |
| 197 | static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in) |
| 198 | { |
| 199 | return is_in ? ep->in_qh : ep->out_qh; |
| 200 | } |
| 201 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 202 | /* |
| 203 | * Start the URB at the front of an endpoint's queue |
| 204 | * end must be claimed from the caller. |
| 205 | * |
| 206 | * Context: controller locked, irqs blocked |
| 207 | */ |
| 208 | static void |
| 209 | musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) |
| 210 | { |
| 211 | u16 frame; |
| 212 | u32 len; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 213 | void __iomem *mbase = musb->mregs; |
| 214 | struct urb *urb = next_urb(qh); |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 215 | void *buf = urb->transfer_buffer; |
| 216 | u32 offset = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 217 | struct musb_hw_ep *hw_ep = qh->hw_ep; |
| 218 | unsigned pipe = urb->pipe; |
| 219 | u8 address = usb_pipedevice(pipe); |
| 220 | int epnum = hw_ep->epnum; |
| 221 | |
| 222 | /* initialize software qh state */ |
| 223 | qh->offset = 0; |
| 224 | qh->segsize = 0; |
| 225 | |
| 226 | /* gather right source of data */ |
| 227 | switch (qh->type) { |
| 228 | case USB_ENDPOINT_XFER_CONTROL: |
| 229 | /* control transfers always start with SETUP */ |
| 230 | is_in = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 231 | musb->ep0_stage = MUSB_EP0_START; |
| 232 | buf = urb->setup_packet; |
| 233 | len = 8; |
| 234 | break; |
| 235 | case USB_ENDPOINT_XFER_ISOC: |
| 236 | qh->iso_idx = 0; |
| 237 | qh->frame = 0; |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 238 | offset = urb->iso_frame_desc[0].offset; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 239 | len = urb->iso_frame_desc[0].length; |
| 240 | break; |
| 241 | default: /* bulk, interrupt */ |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 242 | /* actual_length may be nonzero on retry paths */ |
| 243 | buf = urb->transfer_buffer + urb->actual_length; |
| 244 | len = urb->transfer_buffer_length - urb->actual_length; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 245 | } |
| 246 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 247 | dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 248 | qh, urb, address, qh->epnum, |
| 249 | is_in ? "in" : "out", |
| 250 | ({char *s; switch (qh->type) { |
| 251 | case USB_ENDPOINT_XFER_CONTROL: s = ""; break; |
| 252 | case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; |
| 253 | case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; |
| 254 | default: s = "-intr"; break; |
Joe Perches | 2b84f92 | 2013-10-08 16:01:37 -0700 | [diff] [blame] | 255 | } s; }), |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 256 | epnum, buf + offset, len); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 257 | |
| 258 | /* Configure endpoint */ |
Sergei Shtylyov | 3e5c6dc | 2009-03-27 12:55:16 -0700 | [diff] [blame] | 259 | musb_ep_set_qh(hw_ep, is_in, qh); |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 260 | musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 261 | |
| 262 | /* transmit may have more work: start it when it is time */ |
| 263 | if (is_in) |
| 264 | return; |
| 265 | |
| 266 | /* determine if the time is right for a periodic transfer */ |
| 267 | switch (qh->type) { |
| 268 | case USB_ENDPOINT_XFER_ISOC: |
| 269 | case USB_ENDPOINT_XFER_INT: |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 270 | dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n"); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 271 | frame = musb_readw(mbase, MUSB_FRAME); |
| 272 | /* FIXME this doesn't implement that scheduling policy ... |
| 273 | * or handle framecounter wrapping |
| 274 | */ |
Alan Stern | 8a1ea51 | 2013-05-29 13:21:01 -0400 | [diff] [blame] | 275 | if (1) { /* Always assume URB_ISO_ASAP */ |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 276 | /* REVISIT the SOF irq handler shouldn't duplicate |
| 277 | * this code; and we don't init urb->start_frame... |
| 278 | */ |
| 279 | qh->frame = 0; |
| 280 | goto start; |
| 281 | } else { |
| 282 | qh->frame = urb->start_frame; |
| 283 | /* enable SOF interrupt so we can count down */ |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 284 | dev_dbg(musb->controller, "SOF for %d\n", epnum); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 285 | #if 1 /* ifndef CONFIG_ARCH_DAVINCI */ |
| 286 | musb_writeb(mbase, MUSB_INTRUSBE, 0xff); |
| 287 | #endif |
| 288 | } |
| 289 | break; |
| 290 | default: |
| 291 | start: |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 292 | dev_dbg(musb->controller, "Start TX%d %s\n", epnum, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 293 | hw_ep->tx_channel ? "dma" : "pio"); |
| 294 | |
| 295 | if (!hw_ep->tx_channel) |
| 296 | musb_h_tx_start(hw_ep); |
| 297 | else if (is_cppi_enabled() || tusb_dma_omap()) |
Sergei Shtylyov | c7bbc05 | 2009-03-26 18:26:40 -0700 | [diff] [blame] | 298 | musb_h_tx_dma_start(hw_ep); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 299 | } |
| 300 | } |
| 301 | |
Sergei Shtylyov | c9cd06b | 2009-03-27 12:58:31 -0700 | [diff] [blame] | 302 | /* Context: caller owns controller lock, IRQs are blocked */ |
| 303 | static void musb_giveback(struct musb *musb, struct urb *urb, int status) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 304 | __releases(musb->lock) |
| 305 | __acquires(musb->lock) |
| 306 | { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 307 | dev_dbg(musb->controller, |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 308 | "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", |
| 309 | urb, urb->complete, status, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 310 | usb_pipedevice(urb->pipe), |
| 311 | usb_pipeendpoint(urb->pipe), |
| 312 | usb_pipein(urb->pipe) ? "in" : "out", |
| 313 | urb->actual_length, urb->transfer_buffer_length |
| 314 | ); |
| 315 | |
Daniel Mack | 8b125df | 2013-04-10 21:55:50 +0200 | [diff] [blame] | 316 | usb_hcd_unlink_urb_from_ep(musb->hcd, urb); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 317 | spin_unlock(&musb->lock); |
Daniel Mack | 8b125df | 2013-04-10 21:55:50 +0200 | [diff] [blame] | 318 | usb_hcd_giveback_urb(musb->hcd, urb, status); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 319 | spin_lock(&musb->lock); |
| 320 | } |
| 321 | |
Sergei Shtylyov | 846099a | 2009-03-27 12:54:21 -0700 | [diff] [blame] | 322 | /* For bulk/interrupt endpoints only */ |
| 323 | static inline void musb_save_toggle(struct musb_qh *qh, int is_in, |
| 324 | struct urb *urb) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 325 | { |
Sergei Shtylyov | 846099a | 2009-03-27 12:54:21 -0700 | [diff] [blame] | 326 | void __iomem *epio = qh->hw_ep->regs; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 327 | u16 csr; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 328 | |
Sergei Shtylyov | 846099a | 2009-03-27 12:54:21 -0700 | [diff] [blame] | 329 | /* |
| 330 | * FIXME: the current Mentor DMA code seems to have |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 331 | * problems getting toggle correct. |
| 332 | */ |
| 333 | |
Sergei Shtylyov | 846099a | 2009-03-27 12:54:21 -0700 | [diff] [blame] | 334 | if (is_in) |
| 335 | csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 336 | else |
Sergei Shtylyov | 846099a | 2009-03-27 12:54:21 -0700 | [diff] [blame] | 337 | csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 338 | |
Sergei Shtylyov | 846099a | 2009-03-27 12:54:21 -0700 | [diff] [blame] | 339 | usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 340 | } |
| 341 | |
Sergei Shtylyov | c9cd06b | 2009-03-27 12:58:31 -0700 | [diff] [blame] | 342 | /* |
| 343 | * Advance this hardware endpoint's queue, completing the specified URB and |
| 344 | * advancing to either the next URB queued to that qh, or else invalidating |
| 345 | * that qh and advancing to the next qh scheduled after the current one. |
| 346 | * |
| 347 | * Context: caller owns controller lock, IRQs are blocked |
| 348 | */ |
| 349 | static void musb_advance_schedule(struct musb *musb, struct urb *urb, |
| 350 | struct musb_hw_ep *hw_ep, int is_in) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 351 | { |
Sergei Shtylyov | c9cd06b | 2009-03-27 12:58:31 -0700 | [diff] [blame] | 352 | struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 353 | struct musb_hw_ep *ep = qh->hw_ep; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 354 | int ready = qh->is_ready; |
Sergei Shtylyov | c9cd06b | 2009-03-27 12:58:31 -0700 | [diff] [blame] | 355 | int status; |
| 356 | |
| 357 | status = (urb->status == -EINPROGRESS) ? 0 : urb->status; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 358 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 359 | /* save toggle eagerly, for paranoia */ |
| 360 | switch (qh->type) { |
| 361 | case USB_ENDPOINT_XFER_BULK: |
| 362 | case USB_ENDPOINT_XFER_INT: |
Sergei Shtylyov | 846099a | 2009-03-27 12:54:21 -0700 | [diff] [blame] | 363 | musb_save_toggle(qh, is_in, urb); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 364 | break; |
| 365 | case USB_ENDPOINT_XFER_ISOC: |
Sergei Shtylyov | 1fe975f | 2009-07-10 20:02:44 +0300 | [diff] [blame] | 366 | if (status == 0 && urb->error_count) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 367 | status = -EXDEV; |
| 368 | break; |
| 369 | } |
| 370 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 371 | qh->is_ready = 0; |
Sergei Shtylyov | c9cd06b | 2009-03-27 12:58:31 -0700 | [diff] [blame] | 372 | musb_giveback(musb, urb, status); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 373 | qh->is_ready = ready; |
| 374 | |
| 375 | /* reclaim resources (and bandwidth) ASAP; deschedule it, and |
| 376 | * invalidate qh as soon as list_empty(&hep->urb_list) |
| 377 | */ |
| 378 | if (list_empty(&qh->hep->urb_list)) { |
| 379 | struct list_head *head; |
Ajay Kumar Gupta | 8c778db | 2012-06-21 17:18:12 +0530 | [diff] [blame] | 380 | struct dma_controller *dma = musb->dma_controller; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 381 | |
Ajay Kumar Gupta | 8c778db | 2012-06-21 17:18:12 +0530 | [diff] [blame] | 382 | if (is_in) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 383 | ep->rx_reinit = 1; |
Ajay Kumar Gupta | 8c778db | 2012-06-21 17:18:12 +0530 | [diff] [blame] | 384 | if (ep->rx_channel) { |
| 385 | dma->channel_release(ep->rx_channel); |
| 386 | ep->rx_channel = NULL; |
| 387 | } |
| 388 | } else { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 389 | ep->tx_reinit = 1; |
Ajay Kumar Gupta | 8c778db | 2012-06-21 17:18:12 +0530 | [diff] [blame] | 390 | if (ep->tx_channel) { |
| 391 | dma->channel_release(ep->tx_channel); |
| 392 | ep->tx_channel = NULL; |
| 393 | } |
| 394 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 395 | |
Sergei Shtylyov | 3e5c6dc | 2009-03-27 12:55:16 -0700 | [diff] [blame] | 396 | /* Clobber old pointers to this qh */ |
| 397 | musb_ep_set_qh(ep, is_in, NULL); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 398 | qh->hep->hcpriv = NULL; |
| 399 | |
| 400 | switch (qh->type) { |
| 401 | |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 402 | case USB_ENDPOINT_XFER_CONTROL: |
| 403 | case USB_ENDPOINT_XFER_BULK: |
| 404 | /* fifo policy for these lists, except that NAKing |
| 405 | * should rotate a qh to the end (for fairness). |
| 406 | */ |
| 407 | if (qh->mux == 1) { |
| 408 | head = qh->ring.prev; |
| 409 | list_del(&qh->ring); |
| 410 | kfree(qh); |
| 411 | qh = first_qh(head); |
| 412 | break; |
| 413 | } |
| 414 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 415 | case USB_ENDPOINT_XFER_ISOC: |
| 416 | case USB_ENDPOINT_XFER_INT: |
| 417 | /* this is where periodic bandwidth should be |
| 418 | * de-allocated if it's tracked and allocated; |
| 419 | * and where we'd update the schedule tree... |
| 420 | */ |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 421 | kfree(qh); |
| 422 | qh = NULL; |
| 423 | break; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 424 | } |
| 425 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 426 | |
Sergei Shtylyov | a2fd814 | 2009-02-21 15:30:45 -0800 | [diff] [blame] | 427 | if (qh != NULL && qh->is_ready) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 428 | dev_dbg(musb->controller, "... next ep%d %cX urb %p\n", |
Sergei Shtylyov | c9cd06b | 2009-03-27 12:58:31 -0700 | [diff] [blame] | 429 | hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 430 | musb_start_urb(musb, is_in, qh); |
| 431 | } |
| 432 | } |
| 433 | |
David Brownell | c767c1c | 2008-09-11 11:53:23 +0300 | [diff] [blame] | 434 | static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 435 | { |
| 436 | /* we don't want fifo to fill itself again; |
| 437 | * ignore dma (various models), |
| 438 | * leave toggle alone (may not have been saved yet) |
| 439 | */ |
| 440 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; |
| 441 | csr &= ~(MUSB_RXCSR_H_REQPKT |
| 442 | | MUSB_RXCSR_H_AUTOREQ |
| 443 | | MUSB_RXCSR_AUTOCLEAR); |
| 444 | |
| 445 | /* write 2x to allow double buffering */ |
| 446 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 447 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 448 | |
| 449 | /* flush writebuffer */ |
| 450 | return musb_readw(hw_ep->regs, MUSB_RXCSR); |
| 451 | } |
| 452 | |
| 453 | /* |
| 454 | * PIO RX for a packet (or part of it). |
| 455 | */ |
| 456 | static bool |
| 457 | musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) |
| 458 | { |
| 459 | u16 rx_count; |
| 460 | u8 *buf; |
| 461 | u16 csr; |
| 462 | bool done = false; |
| 463 | u32 length; |
| 464 | int do_flush = 0; |
| 465 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 466 | void __iomem *epio = hw_ep->regs; |
| 467 | struct musb_qh *qh = hw_ep->in_qh; |
| 468 | int pipe = urb->pipe; |
| 469 | void *buffer = urb->transfer_buffer; |
| 470 | |
| 471 | /* musb_ep_select(mbase, epnum); */ |
| 472 | rx_count = musb_readw(epio, MUSB_RXCOUNT); |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 473 | dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 474 | urb->transfer_buffer, qh->offset, |
| 475 | urb->transfer_buffer_length); |
| 476 | |
| 477 | /* unload FIFO */ |
| 478 | if (usb_pipeisoc(pipe)) { |
| 479 | int status = 0; |
| 480 | struct usb_iso_packet_descriptor *d; |
| 481 | |
| 482 | if (iso_err) { |
| 483 | status = -EILSEQ; |
| 484 | urb->error_count++; |
| 485 | } |
| 486 | |
| 487 | d = urb->iso_frame_desc + qh->iso_idx; |
| 488 | buf = buffer + d->offset; |
| 489 | length = d->length; |
| 490 | if (rx_count > length) { |
| 491 | if (status == 0) { |
| 492 | status = -EOVERFLOW; |
| 493 | urb->error_count++; |
| 494 | } |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 495 | dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 496 | do_flush = 1; |
| 497 | } else |
| 498 | length = rx_count; |
| 499 | urb->actual_length += length; |
| 500 | d->actual_length = length; |
| 501 | |
| 502 | d->status = status; |
| 503 | |
| 504 | /* see if we are done */ |
| 505 | done = (++qh->iso_idx >= urb->number_of_packets); |
| 506 | } else { |
| 507 | /* non-isoch */ |
| 508 | buf = buffer + qh->offset; |
| 509 | length = urb->transfer_buffer_length - qh->offset; |
| 510 | if (rx_count > length) { |
| 511 | if (urb->status == -EINPROGRESS) |
| 512 | urb->status = -EOVERFLOW; |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 513 | dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 514 | do_flush = 1; |
| 515 | } else |
| 516 | length = rx_count; |
| 517 | urb->actual_length += length; |
| 518 | qh->offset += length; |
| 519 | |
| 520 | /* see if we are done */ |
| 521 | done = (urb->actual_length == urb->transfer_buffer_length) |
| 522 | || (rx_count < qh->maxpacket) |
| 523 | || (urb->status != -EINPROGRESS); |
| 524 | if (done |
| 525 | && (urb->status == -EINPROGRESS) |
| 526 | && (urb->transfer_flags & URB_SHORT_NOT_OK) |
| 527 | && (urb->actual_length |
| 528 | < urb->transfer_buffer_length)) |
| 529 | urb->status = -EREMOTEIO; |
| 530 | } |
| 531 | |
| 532 | musb_read_fifo(hw_ep, length, buf); |
| 533 | |
| 534 | csr = musb_readw(epio, MUSB_RXCSR); |
| 535 | csr |= MUSB_RXCSR_H_WZC_BITS; |
| 536 | if (unlikely(do_flush)) |
| 537 | musb_h_flush_rxfifo(hw_ep, csr); |
| 538 | else { |
| 539 | /* REVISIT this assumes AUTOCLEAR is never set */ |
| 540 | csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); |
| 541 | if (!done) |
| 542 | csr |= MUSB_RXCSR_H_REQPKT; |
| 543 | musb_writew(epio, MUSB_RXCSR, csr); |
| 544 | } |
| 545 | |
| 546 | return done; |
| 547 | } |
| 548 | |
| 549 | /* we don't always need to reinit a given side of an endpoint... |
| 550 | * when we do, use tx/rx reinit routine and then construct a new CSR |
| 551 | * to address data toggle, NYET, and DMA or PIO. |
| 552 | * |
| 553 | * it's possible that driver bugs (especially for DMA) or aborting a |
| 554 | * transfer might have left the endpoint busier than it should be. |
| 555 | * the busy/not-empty tests are basically paranoia. |
| 556 | */ |
| 557 | static void |
| 558 | musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) |
| 559 | { |
| 560 | u16 csr; |
| 561 | |
| 562 | /* NOTE: we know the "rx" fifo reinit never triggers for ep0. |
| 563 | * That always uses tx_reinit since ep0 repurposes TX register |
| 564 | * offsets; the initial SETUP packet is also a kind of OUT. |
| 565 | */ |
| 566 | |
| 567 | /* if programmed for Tx, put it in RX mode */ |
| 568 | if (ep->is_shared_fifo) { |
| 569 | csr = musb_readw(ep->regs, MUSB_TXCSR); |
| 570 | if (csr & MUSB_TXCSR_MODE) { |
| 571 | musb_h_tx_flush_fifo(ep); |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 572 | csr = musb_readw(ep->regs, MUSB_TXCSR); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 573 | musb_writew(ep->regs, MUSB_TXCSR, |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 574 | csr | MUSB_TXCSR_FRCDATATOG); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 575 | } |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 576 | |
| 577 | /* |
| 578 | * Clear the MODE bit (and everything else) to enable Rx. |
| 579 | * NOTE: we mustn't clear the DMAMODE bit before DMAENAB. |
| 580 | */ |
| 581 | if (csr & MUSB_TXCSR_DMAMODE) |
| 582 | musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 583 | musb_writew(ep->regs, MUSB_TXCSR, 0); |
| 584 | |
| 585 | /* scrub all previous state, clearing toggle */ |
| 586 | } else { |
| 587 | csr = musb_readw(ep->regs, MUSB_RXCSR); |
| 588 | if (csr & MUSB_RXCSR_RXPKTRDY) |
| 589 | WARNING("rx%d, packet/%d ready?\n", ep->epnum, |
| 590 | musb_readw(ep->regs, MUSB_RXCOUNT)); |
| 591 | |
| 592 | musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); |
| 593 | } |
| 594 | |
| 595 | /* target addr and (for multipoint) hub addr/port */ |
| 596 | if (musb->is_multipoint) { |
Bryan Wu | c6cf8b0 | 2008-12-02 21:33:48 +0200 | [diff] [blame] | 597 | musb_write_rxfunaddr(ep->target_regs, qh->addr_reg); |
| 598 | musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg); |
| 599 | musb_write_rxhubport(ep->target_regs, qh->h_port_reg); |
| 600 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 601 | } else |
| 602 | musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); |
| 603 | |
| 604 | /* protocol/endpoint, interval/NAKlimit, i/o size */ |
| 605 | musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); |
| 606 | musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); |
| 607 | /* NOTE: bulk combining rewrites high bits of maxpacket */ |
Cliff Cai | 9f445cb | 2010-01-28 20:44:18 -0500 | [diff] [blame] | 608 | /* Set RXMAXP with the FIFO size of the endpoint |
| 609 | * to disable double buffer mode. |
| 610 | */ |
Felipe Balbi | 0662481 | 2011-01-21 13:39:20 +0800 | [diff] [blame] | 611 | if (musb->double_buffer_not_ok) |
Cliff Cai | 9f445cb | 2010-01-28 20:44:18 -0500 | [diff] [blame] | 612 | musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); |
| 613 | else |
| 614 | musb_writew(ep->regs, MUSB_RXMAXP, |
| 615 | qh->maxpacket | ((qh->hb_mult - 1) << 11)); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 616 | |
| 617 | ep->rx_reinit = 0; |
| 618 | } |
| 619 | |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 620 | static bool musb_tx_dma_program(struct dma_controller *dma, |
| 621 | struct musb_hw_ep *hw_ep, struct musb_qh *qh, |
| 622 | struct urb *urb, u32 offset, u32 length) |
| 623 | { |
| 624 | struct dma_channel *channel = hw_ep->tx_channel; |
| 625 | void __iomem *epio = hw_ep->regs; |
| 626 | u16 pkt_size = qh->maxpacket; |
| 627 | u16 csr; |
| 628 | u8 mode; |
| 629 | |
Mian Yousaf Kaukab | aee5500 | 2013-05-15 14:03:24 +0200 | [diff] [blame] | 630 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 631 | if (length > channel->max_len) |
| 632 | length = channel->max_len; |
| 633 | |
| 634 | csr = musb_readw(epio, MUSB_TXCSR); |
| 635 | if (length > pkt_size) { |
| 636 | mode = 1; |
Ajay Kumar Gupta | a483d70 | 2009-04-03 16:16:17 -0700 | [diff] [blame] | 637 | csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; |
| 638 | /* autoset shouldn't be set in high bandwidth */ |
supriya karanth | f278628 | 2012-12-06 11:16:23 +0530 | [diff] [blame] | 639 | /* |
| 640 | * Enable Autoset according to table |
| 641 | * below |
| 642 | * bulk_split hb_mult Autoset_Enable |
| 643 | * 0 1 Yes(Normal) |
| 644 | * 0 >1 No(High BW ISO) |
| 645 | * 1 1 Yes(HS bulk) |
| 646 | * 1 >1 Yes(FS bulk) |
| 647 | */ |
| 648 | if (qh->hb_mult == 1 || (qh->hb_mult > 1 && |
| 649 | can_bulk_split(hw_ep->musb, qh->type))) |
Ajay Kumar Gupta | a483d70 | 2009-04-03 16:16:17 -0700 | [diff] [blame] | 650 | csr |= MUSB_TXCSR_AUTOSET; |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 651 | } else { |
| 652 | mode = 0; |
| 653 | csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); |
| 654 | csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ |
| 655 | } |
| 656 | channel->desired_mode = mode; |
| 657 | musb_writew(epio, MUSB_TXCSR, csr); |
| 658 | #else |
| 659 | if (!is_cppi_enabled() && !tusb_dma_omap()) |
| 660 | return false; |
| 661 | |
| 662 | channel->actual_len = 0; |
| 663 | |
| 664 | /* |
| 665 | * TX uses "RNDIS" mode automatically but needs help |
| 666 | * to identify the zero-length-final-packet case. |
| 667 | */ |
| 668 | mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; |
| 669 | #endif |
| 670 | |
| 671 | qh->segsize = length; |
| 672 | |
Santosh Shilimkar | 4c64733 | 2010-09-20 10:32:07 +0300 | [diff] [blame] | 673 | /* |
| 674 | * Ensure the data reaches to main memory before starting |
| 675 | * DMA transfer |
| 676 | */ |
| 677 | wmb(); |
| 678 | |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 679 | if (!dma->channel_program(channel, pkt_size, mode, |
| 680 | urb->transfer_dma + offset, length)) { |
| 681 | dma->channel_release(channel); |
| 682 | hw_ep->tx_channel = NULL; |
| 683 | |
| 684 | csr = musb_readw(epio, MUSB_TXCSR); |
| 685 | csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); |
| 686 | musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); |
| 687 | return false; |
| 688 | } |
| 689 | return true; |
| 690 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 691 | |
| 692 | /* |
| 693 | * Program an HDRC endpoint as per the given URB |
| 694 | * Context: irqs blocked, controller lock held |
| 695 | */ |
| 696 | static void musb_ep_program(struct musb *musb, u8 epnum, |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 697 | struct urb *urb, int is_out, |
| 698 | u8 *buf, u32 offset, u32 len) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 699 | { |
| 700 | struct dma_controller *dma_controller; |
| 701 | struct dma_channel *dma_channel; |
| 702 | u8 dma_ok; |
| 703 | void __iomem *mbase = musb->mregs; |
| 704 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 705 | void __iomem *epio = hw_ep->regs; |
Sergei Shtylyov | 3e5c6dc | 2009-03-27 12:55:16 -0700 | [diff] [blame] | 706 | struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); |
| 707 | u16 packet_sz = qh->maxpacket; |
Ajay Kumar Gupta | 3132122 | 2012-07-20 11:07:22 +0530 | [diff] [blame] | 708 | u8 use_dma = 1; |
| 709 | u16 csr; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 710 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 711 | dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s " |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 712 | "h_addr%02x h_port%02x bytes %d\n", |
| 713 | is_out ? "-->" : "<--", |
| 714 | epnum, urb, urb->dev->speed, |
| 715 | qh->addr_reg, qh->epnum, is_out ? "out" : "in", |
| 716 | qh->h_addr_reg, qh->h_port_reg, |
| 717 | len); |
| 718 | |
| 719 | musb_ep_select(mbase, epnum); |
| 720 | |
Ajay Kumar Gupta | 3132122 | 2012-07-20 11:07:22 +0530 | [diff] [blame] | 721 | if (is_out && !len) { |
| 722 | use_dma = 0; |
| 723 | csr = musb_readw(epio, MUSB_TXCSR); |
| 724 | csr &= ~MUSB_TXCSR_DMAENAB; |
| 725 | musb_writew(epio, MUSB_TXCSR, csr); |
| 726 | hw_ep->tx_channel = NULL; |
| 727 | } |
| 728 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 729 | /* candidate for DMA? */ |
| 730 | dma_controller = musb->dma_controller; |
Ajay Kumar Gupta | 3132122 | 2012-07-20 11:07:22 +0530 | [diff] [blame] | 731 | if (use_dma && is_dma_capable() && epnum && dma_controller) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 732 | dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; |
| 733 | if (!dma_channel) { |
| 734 | dma_channel = dma_controller->channel_alloc( |
| 735 | dma_controller, hw_ep, is_out); |
| 736 | if (is_out) |
| 737 | hw_ep->tx_channel = dma_channel; |
| 738 | else |
| 739 | hw_ep->rx_channel = dma_channel; |
| 740 | } |
| 741 | } else |
| 742 | dma_channel = NULL; |
| 743 | |
| 744 | /* make sure we clear DMAEnab, autoSet bits from previous run */ |
| 745 | |
| 746 | /* OUT/transmit/EP0 or IN/receive? */ |
| 747 | if (is_out) { |
| 748 | u16 csr; |
| 749 | u16 int_txe; |
| 750 | u16 load_count; |
| 751 | |
| 752 | csr = musb_readw(epio, MUSB_TXCSR); |
| 753 | |
| 754 | /* disable interrupt in case we flush */ |
Sebastian Andrzej Siewior | b18d26f | 2012-10-30 19:52:26 +0100 | [diff] [blame] | 755 | int_txe = musb->intrtxe; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 756 | musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); |
| 757 | |
| 758 | /* general endpoint setup */ |
| 759 | if (epnum) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 760 | /* flush all old state, set default */ |
supriya karanth | a70b844 | 2013-01-04 17:10:33 +0530 | [diff] [blame] | 761 | /* |
| 762 | * We could be flushing valid |
| 763 | * packets in double buffering |
| 764 | * case |
| 765 | */ |
| 766 | if (!hw_ep->tx_double_buffered) |
| 767 | musb_h_tx_flush_fifo(hw_ep); |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 768 | |
| 769 | /* |
| 770 | * We must not clear the DMAMODE bit before or in |
| 771 | * the same cycle with the DMAENAB bit, so we clear |
| 772 | * the latter first... |
| 773 | */ |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 774 | csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 775 | | MUSB_TXCSR_AUTOSET |
| 776 | | MUSB_TXCSR_DMAENAB |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 777 | | MUSB_TXCSR_FRCDATATOG |
| 778 | | MUSB_TXCSR_H_RXSTALL |
| 779 | | MUSB_TXCSR_H_ERROR |
| 780 | | MUSB_TXCSR_TXPKTRDY |
| 781 | ); |
| 782 | csr |= MUSB_TXCSR_MODE; |
| 783 | |
supriya karanth | a70b844 | 2013-01-04 17:10:33 +0530 | [diff] [blame] | 784 | if (!hw_ep->tx_double_buffered) { |
| 785 | if (usb_gettoggle(urb->dev, qh->epnum, 1)) |
| 786 | csr |= MUSB_TXCSR_H_WR_DATATOGGLE |
| 787 | | MUSB_TXCSR_H_DATATOGGLE; |
| 788 | else |
| 789 | csr |= MUSB_TXCSR_CLRDATATOG; |
| 790 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 791 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 792 | musb_writew(epio, MUSB_TXCSR, csr); |
| 793 | /* REVISIT may need to clear FLUSHFIFO ... */ |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 794 | csr &= ~MUSB_TXCSR_DMAMODE; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 795 | musb_writew(epio, MUSB_TXCSR, csr); |
| 796 | csr = musb_readw(epio, MUSB_TXCSR); |
| 797 | } else { |
| 798 | /* endpoint 0: just flush */ |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 799 | musb_h_ep0_flush_fifo(hw_ep); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 800 | } |
| 801 | |
| 802 | /* target addr and (for multipoint) hub addr/port */ |
| 803 | if (musb->is_multipoint) { |
Bryan Wu | c6cf8b0 | 2008-12-02 21:33:48 +0200 | [diff] [blame] | 804 | musb_write_txfunaddr(mbase, epnum, qh->addr_reg); |
| 805 | musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); |
| 806 | musb_write_txhubport(mbase, epnum, qh->h_port_reg); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 807 | /* FIXME if !epnum, do the same for RX ... */ |
| 808 | } else |
| 809 | musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); |
| 810 | |
| 811 | /* protocol/endpoint/interval/NAKlimit */ |
| 812 | if (epnum) { |
| 813 | musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); |
supriya karanth | f278628 | 2012-12-06 11:16:23 +0530 | [diff] [blame] | 814 | if (musb->double_buffer_not_ok) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 815 | musb_writew(epio, MUSB_TXMAXP, |
Felipe Balbi | 0662481 | 2011-01-21 13:39:20 +0800 | [diff] [blame] | 816 | hw_ep->max_packet_sz_tx); |
supriya karanth | f278628 | 2012-12-06 11:16:23 +0530 | [diff] [blame] | 817 | } else if (can_bulk_split(musb, qh->type)) { |
| 818 | qh->hb_mult = hw_ep->max_packet_sz_tx |
| 819 | / packet_sz; |
Ajay Kumar Gupta | ccc080c | 2011-12-13 10:32:42 +0530 | [diff] [blame] | 820 | musb_writew(epio, MUSB_TXMAXP, packet_sz |
supriya karanth | f278628 | 2012-12-06 11:16:23 +0530 | [diff] [blame] | 821 | | ((qh->hb_mult) - 1) << 11); |
| 822 | } else { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 823 | musb_writew(epio, MUSB_TXMAXP, |
Felipe Balbi | 0662481 | 2011-01-21 13:39:20 +0800 | [diff] [blame] | 824 | qh->maxpacket | |
| 825 | ((qh->hb_mult - 1) << 11)); |
supriya karanth | f278628 | 2012-12-06 11:16:23 +0530 | [diff] [blame] | 826 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 827 | musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); |
| 828 | } else { |
| 829 | musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); |
| 830 | if (musb->is_multipoint) |
| 831 | musb_writeb(epio, MUSB_TYPE0, |
| 832 | qh->type_reg); |
| 833 | } |
| 834 | |
| 835 | if (can_bulk_split(musb, qh->type)) |
| 836 | load_count = min((u32) hw_ep->max_packet_sz_tx, |
| 837 | len); |
| 838 | else |
| 839 | load_count = min((u32) packet_sz, len); |
| 840 | |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 841 | if (dma_channel && musb_tx_dma_program(dma_controller, |
| 842 | hw_ep, qh, urb, offset, len)) |
| 843 | load_count = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 844 | |
| 845 | if (load_count) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 846 | /* PIO to load FIFO */ |
| 847 | qh->segsize = load_count; |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 848 | if (!buf) { |
| 849 | sg_miter_start(&qh->sg_miter, urb->sg, 1, |
| 850 | SG_MITER_ATOMIC |
| 851 | | SG_MITER_FROM_SG); |
| 852 | if (!sg_miter_next(&qh->sg_miter)) { |
| 853 | dev_err(musb->controller, |
| 854 | "error: sg" |
| 855 | "list empty\n"); |
| 856 | sg_miter_stop(&qh->sg_miter); |
| 857 | goto finish; |
| 858 | } |
| 859 | buf = qh->sg_miter.addr + urb->sg->offset + |
| 860 | urb->actual_length; |
| 861 | load_count = min_t(u32, load_count, |
| 862 | qh->sg_miter.length); |
| 863 | musb_write_fifo(hw_ep, load_count, buf); |
| 864 | qh->sg_miter.consumed = load_count; |
| 865 | sg_miter_stop(&qh->sg_miter); |
| 866 | } else |
| 867 | musb_write_fifo(hw_ep, load_count, buf); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 868 | } |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 869 | finish: |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 870 | /* re-enable interrupt */ |
| 871 | musb_writew(mbase, MUSB_INTRTXE, int_txe); |
| 872 | |
| 873 | /* IN/receive */ |
| 874 | } else { |
| 875 | u16 csr; |
| 876 | |
| 877 | if (hw_ep->rx_reinit) { |
| 878 | musb_rx_reinit(musb, qh, hw_ep); |
| 879 | |
| 880 | /* init new state: toggle and NYET, maybe DMA later */ |
| 881 | if (usb_gettoggle(urb->dev, qh->epnum, 0)) |
| 882 | csr = MUSB_RXCSR_H_WR_DATATOGGLE |
| 883 | | MUSB_RXCSR_H_DATATOGGLE; |
| 884 | else |
| 885 | csr = 0; |
| 886 | if (qh->type == USB_ENDPOINT_XFER_INT) |
| 887 | csr |= MUSB_RXCSR_DISNYET; |
| 888 | |
| 889 | } else { |
| 890 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); |
| 891 | |
| 892 | if (csr & (MUSB_RXCSR_RXPKTRDY |
| 893 | | MUSB_RXCSR_DMAENAB |
| 894 | | MUSB_RXCSR_H_REQPKT)) |
| 895 | ERR("broken !rx_reinit, ep%d csr %04x\n", |
| 896 | hw_ep->epnum, csr); |
| 897 | |
| 898 | /* scrub any stale state, leaving toggle alone */ |
| 899 | csr &= MUSB_RXCSR_DISNYET; |
| 900 | } |
| 901 | |
| 902 | /* kick things off */ |
| 903 | |
| 904 | if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { |
Sergei Shtylyov | c51e36d | 2011-05-07 19:44:13 +0400 | [diff] [blame] | 905 | /* Candidate for DMA */ |
| 906 | dma_channel->actual_len = 0L; |
| 907 | qh->segsize = len; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 908 | |
Sergei Shtylyov | c51e36d | 2011-05-07 19:44:13 +0400 | [diff] [blame] | 909 | /* AUTOREQ is in a DMA register */ |
| 910 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 911 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 912 | |
Sergei Shtylyov | c51e36d | 2011-05-07 19:44:13 +0400 | [diff] [blame] | 913 | /* |
| 914 | * Unless caller treats short RX transfers as |
| 915 | * errors, we dare not queue multiple transfers. |
| 916 | */ |
| 917 | dma_ok = dma_controller->channel_program(dma_channel, |
| 918 | packet_sz, !(urb->transfer_flags & |
| 919 | URB_SHORT_NOT_OK), |
| 920 | urb->transfer_dma + offset, |
| 921 | qh->segsize); |
| 922 | if (!dma_ok) { |
| 923 | dma_controller->channel_release(dma_channel); |
| 924 | hw_ep->rx_channel = dma_channel = NULL; |
| 925 | } else |
| 926 | csr |= MUSB_RXCSR_DMAENAB; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 927 | } |
| 928 | |
| 929 | csr |= MUSB_RXCSR_H_REQPKT; |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 930 | dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 931 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 932 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); |
| 933 | } |
| 934 | } |
| 935 | |
Ajay Kumar Gupta | f283862 | 2012-07-19 13:41:59 +0530 | [diff] [blame] | 936 | /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to |
| 937 | * the end; avoids starvation for other endpoints. |
| 938 | */ |
| 939 | static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep, |
| 940 | int is_in) |
| 941 | { |
| 942 | struct dma_channel *dma; |
| 943 | struct urb *urb; |
| 944 | void __iomem *mbase = musb->mregs; |
| 945 | void __iomem *epio = ep->regs; |
| 946 | struct musb_qh *cur_qh, *next_qh; |
| 947 | u16 rx_csr, tx_csr; |
| 948 | |
| 949 | musb_ep_select(mbase, ep->epnum); |
| 950 | if (is_in) { |
| 951 | dma = is_dma_capable() ? ep->rx_channel : NULL; |
| 952 | |
| 953 | /* clear nak timeout bit */ |
| 954 | rx_csr = musb_readw(epio, MUSB_RXCSR); |
| 955 | rx_csr |= MUSB_RXCSR_H_WZC_BITS; |
| 956 | rx_csr &= ~MUSB_RXCSR_DATAERROR; |
| 957 | musb_writew(epio, MUSB_RXCSR, rx_csr); |
| 958 | |
| 959 | cur_qh = first_qh(&musb->in_bulk); |
| 960 | } else { |
| 961 | dma = is_dma_capable() ? ep->tx_channel : NULL; |
| 962 | |
| 963 | /* clear nak timeout bit */ |
| 964 | tx_csr = musb_readw(epio, MUSB_TXCSR); |
| 965 | tx_csr |= MUSB_TXCSR_H_WZC_BITS; |
| 966 | tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT; |
| 967 | musb_writew(epio, MUSB_TXCSR, tx_csr); |
| 968 | |
| 969 | cur_qh = first_qh(&musb->out_bulk); |
| 970 | } |
| 971 | if (cur_qh) { |
| 972 | urb = next_urb(cur_qh); |
| 973 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 974 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
| 975 | musb->dma_controller->channel_abort(dma); |
| 976 | urb->actual_length += dma->actual_len; |
| 977 | dma->actual_len = 0L; |
| 978 | } |
| 979 | musb_save_toggle(cur_qh, is_in, urb); |
| 980 | |
| 981 | if (is_in) { |
| 982 | /* move cur_qh to end of queue */ |
| 983 | list_move_tail(&cur_qh->ring, &musb->in_bulk); |
| 984 | |
| 985 | /* get the next qh from musb->in_bulk */ |
| 986 | next_qh = first_qh(&musb->in_bulk); |
| 987 | |
| 988 | /* set rx_reinit and schedule the next qh */ |
| 989 | ep->rx_reinit = 1; |
| 990 | } else { |
| 991 | /* move cur_qh to end of queue */ |
| 992 | list_move_tail(&cur_qh->ring, &musb->out_bulk); |
| 993 | |
| 994 | /* get the next qh from musb->out_bulk */ |
| 995 | next_qh = first_qh(&musb->out_bulk); |
| 996 | |
| 997 | /* set tx_reinit and schedule the next qh */ |
| 998 | ep->tx_reinit = 1; |
| 999 | } |
| 1000 | musb_start_urb(musb, is_in, next_qh); |
| 1001 | } |
| 1002 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1003 | |
| 1004 | /* |
| 1005 | * Service the default endpoint (ep0) as host. |
| 1006 | * Return true until it's time to start the status stage. |
| 1007 | */ |
| 1008 | static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) |
| 1009 | { |
| 1010 | bool more = false; |
| 1011 | u8 *fifo_dest = NULL; |
| 1012 | u16 fifo_count = 0; |
| 1013 | struct musb_hw_ep *hw_ep = musb->control_ep; |
| 1014 | struct musb_qh *qh = hw_ep->in_qh; |
| 1015 | struct usb_ctrlrequest *request; |
| 1016 | |
| 1017 | switch (musb->ep0_stage) { |
| 1018 | case MUSB_EP0_IN: |
| 1019 | fifo_dest = urb->transfer_buffer + urb->actual_length; |
Sergei Shtylyov | 3ecdb9a | 2009-02-21 15:31:23 -0800 | [diff] [blame] | 1020 | fifo_count = min_t(size_t, len, urb->transfer_buffer_length - |
| 1021 | urb->actual_length); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1022 | if (fifo_count < len) |
| 1023 | urb->status = -EOVERFLOW; |
| 1024 | |
| 1025 | musb_read_fifo(hw_ep, fifo_count, fifo_dest); |
| 1026 | |
| 1027 | urb->actual_length += fifo_count; |
| 1028 | if (len < qh->maxpacket) { |
| 1029 | /* always terminate on short read; it's |
| 1030 | * rarely reported as an error. |
| 1031 | */ |
| 1032 | } else if (urb->actual_length < |
| 1033 | urb->transfer_buffer_length) |
| 1034 | more = true; |
| 1035 | break; |
| 1036 | case MUSB_EP0_START: |
| 1037 | request = (struct usb_ctrlrequest *) urb->setup_packet; |
| 1038 | |
| 1039 | if (!request->wLength) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1040 | dev_dbg(musb->controller, "start no-DATA\n"); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1041 | break; |
| 1042 | } else if (request->bRequestType & USB_DIR_IN) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1043 | dev_dbg(musb->controller, "start IN-DATA\n"); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1044 | musb->ep0_stage = MUSB_EP0_IN; |
| 1045 | more = true; |
| 1046 | break; |
| 1047 | } else { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1048 | dev_dbg(musb->controller, "start OUT-DATA\n"); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1049 | musb->ep0_stage = MUSB_EP0_OUT; |
| 1050 | more = true; |
| 1051 | } |
| 1052 | /* FALLTHROUGH */ |
| 1053 | case MUSB_EP0_OUT: |
Sergei Shtylyov | 3ecdb9a | 2009-02-21 15:31:23 -0800 | [diff] [blame] | 1054 | fifo_count = min_t(size_t, qh->maxpacket, |
| 1055 | urb->transfer_buffer_length - |
| 1056 | urb->actual_length); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1057 | if (fifo_count) { |
| 1058 | fifo_dest = (u8 *) (urb->transfer_buffer |
| 1059 | + urb->actual_length); |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1060 | dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n", |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 1061 | fifo_count, |
| 1062 | (fifo_count == 1) ? "" : "s", |
| 1063 | fifo_dest); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1064 | musb_write_fifo(hw_ep, fifo_count, fifo_dest); |
| 1065 | |
| 1066 | urb->actual_length += fifo_count; |
| 1067 | more = true; |
| 1068 | } |
| 1069 | break; |
| 1070 | default: |
| 1071 | ERR("bogus ep0 stage %d\n", musb->ep0_stage); |
| 1072 | break; |
| 1073 | } |
| 1074 | |
| 1075 | return more; |
| 1076 | } |
| 1077 | |
| 1078 | /* |
| 1079 | * Handle default endpoint interrupt as host. Only called in IRQ time |
David Brownell | c767c1c | 2008-09-11 11:53:23 +0300 | [diff] [blame] | 1080 | * from musb_interrupt(). |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1081 | * |
| 1082 | * called with controller irqlocked |
| 1083 | */ |
| 1084 | irqreturn_t musb_h_ep0_irq(struct musb *musb) |
| 1085 | { |
| 1086 | struct urb *urb; |
| 1087 | u16 csr, len; |
| 1088 | int status = 0; |
| 1089 | void __iomem *mbase = musb->mregs; |
| 1090 | struct musb_hw_ep *hw_ep = musb->control_ep; |
| 1091 | void __iomem *epio = hw_ep->regs; |
| 1092 | struct musb_qh *qh = hw_ep->in_qh; |
| 1093 | bool complete = false; |
| 1094 | irqreturn_t retval = IRQ_NONE; |
| 1095 | |
| 1096 | /* ep0 only has one queue, "in" */ |
| 1097 | urb = next_urb(qh); |
| 1098 | |
| 1099 | musb_ep_select(mbase, 0); |
| 1100 | csr = musb_readw(epio, MUSB_CSR0); |
| 1101 | len = (csr & MUSB_CSR0_RXPKTRDY) |
| 1102 | ? musb_readb(epio, MUSB_COUNT0) |
| 1103 | : 0; |
| 1104 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1105 | dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1106 | csr, qh, len, urb, musb->ep0_stage); |
| 1107 | |
| 1108 | /* if we just did status stage, we are done */ |
| 1109 | if (MUSB_EP0_STATUS == musb->ep0_stage) { |
| 1110 | retval = IRQ_HANDLED; |
| 1111 | complete = true; |
| 1112 | } |
| 1113 | |
| 1114 | /* prepare status */ |
| 1115 | if (csr & MUSB_CSR0_H_RXSTALL) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1116 | dev_dbg(musb->controller, "STALLING ENDPOINT\n"); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1117 | status = -EPIPE; |
| 1118 | |
| 1119 | } else if (csr & MUSB_CSR0_H_ERROR) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1120 | dev_dbg(musb->controller, "no response, csr0 %04x\n", csr); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1121 | status = -EPROTO; |
| 1122 | |
| 1123 | } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1124 | dev_dbg(musb->controller, "control NAK timeout\n"); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1125 | |
| 1126 | /* NOTE: this code path would be a good place to PAUSE a |
| 1127 | * control transfer, if another one is queued, so that |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 1128 | * ep0 is more likely to stay busy. That's already done |
| 1129 | * for bulk RX transfers. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1130 | * |
| 1131 | * if (qh->ring.next != &musb->control), then |
| 1132 | * we have a candidate... NAKing is *NOT* an error |
| 1133 | */ |
| 1134 | musb_writew(epio, MUSB_CSR0, 0); |
| 1135 | retval = IRQ_HANDLED; |
| 1136 | } |
| 1137 | |
| 1138 | if (status) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1139 | dev_dbg(musb->controller, "aborting\n"); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1140 | retval = IRQ_HANDLED; |
| 1141 | if (urb) |
| 1142 | urb->status = status; |
| 1143 | complete = true; |
| 1144 | |
| 1145 | /* use the proper sequence to abort the transfer */ |
| 1146 | if (csr & MUSB_CSR0_H_REQPKT) { |
| 1147 | csr &= ~MUSB_CSR0_H_REQPKT; |
| 1148 | musb_writew(epio, MUSB_CSR0, csr); |
| 1149 | csr &= ~MUSB_CSR0_H_NAKTIMEOUT; |
| 1150 | musb_writew(epio, MUSB_CSR0, csr); |
| 1151 | } else { |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 1152 | musb_h_ep0_flush_fifo(hw_ep); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1153 | } |
| 1154 | |
| 1155 | musb_writeb(epio, MUSB_NAKLIMIT0, 0); |
| 1156 | |
| 1157 | /* clear it */ |
| 1158 | musb_writew(epio, MUSB_CSR0, 0); |
| 1159 | } |
| 1160 | |
| 1161 | if (unlikely(!urb)) { |
| 1162 | /* stop endpoint since we have no place for its data, this |
| 1163 | * SHOULD NEVER HAPPEN! */ |
| 1164 | ERR("no URB for end 0\n"); |
| 1165 | |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 1166 | musb_h_ep0_flush_fifo(hw_ep); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1167 | goto done; |
| 1168 | } |
| 1169 | |
| 1170 | if (!complete) { |
| 1171 | /* call common logic and prepare response */ |
| 1172 | if (musb_h_ep0_continue(musb, len, urb)) { |
| 1173 | /* more packets required */ |
| 1174 | csr = (MUSB_EP0_IN == musb->ep0_stage) |
| 1175 | ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; |
| 1176 | } else { |
| 1177 | /* data transfer complete; perform status phase */ |
| 1178 | if (usb_pipeout(urb->pipe) |
| 1179 | || !urb->transfer_buffer_length) |
| 1180 | csr = MUSB_CSR0_H_STATUSPKT |
| 1181 | | MUSB_CSR0_H_REQPKT; |
| 1182 | else |
| 1183 | csr = MUSB_CSR0_H_STATUSPKT |
| 1184 | | MUSB_CSR0_TXPKTRDY; |
| 1185 | |
Ajay Kumar Gupta | 3c4653c | 2014-02-04 15:28:06 +0200 | [diff] [blame] | 1186 | /* disable ping token in status phase */ |
| 1187 | csr |= MUSB_CSR0_H_DIS_PING; |
| 1188 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1189 | /* flag status stage */ |
| 1190 | musb->ep0_stage = MUSB_EP0_STATUS; |
| 1191 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1192 | dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1193 | |
| 1194 | } |
| 1195 | musb_writew(epio, MUSB_CSR0, csr); |
| 1196 | retval = IRQ_HANDLED; |
| 1197 | } else |
| 1198 | musb->ep0_stage = MUSB_EP0_IDLE; |
| 1199 | |
| 1200 | /* call completion handler if done */ |
| 1201 | if (complete) |
| 1202 | musb_advance_schedule(musb, urb, hw_ep, 1); |
| 1203 | done: |
| 1204 | return retval; |
| 1205 | } |
| 1206 | |
| 1207 | |
| 1208 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 1209 | |
| 1210 | /* Host side TX (OUT) using Mentor DMA works as follows: |
| 1211 | submit_urb -> |
| 1212 | - if queue was empty, Program Endpoint |
| 1213 | - ... which starts DMA to fifo in mode 1 or 0 |
| 1214 | |
| 1215 | DMA Isr (transfer complete) -> TxAvail() |
| 1216 | - Stop DMA (~DmaEnab) (<--- Alert ... currently happens |
| 1217 | only in musb_cleanup_urb) |
| 1218 | - TxPktRdy has to be set in mode 0 or for |
| 1219 | short packets in mode 1. |
| 1220 | */ |
| 1221 | |
| 1222 | #endif |
| 1223 | |
| 1224 | /* Service a Tx-Available or dma completion irq for the endpoint */ |
| 1225 | void musb_host_tx(struct musb *musb, u8 epnum) |
| 1226 | { |
| 1227 | int pipe; |
| 1228 | bool done = false; |
| 1229 | u16 tx_csr; |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1230 | size_t length = 0; |
| 1231 | size_t offset = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1232 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 1233 | void __iomem *epio = hw_ep->regs; |
Sergei Shtylyov | 3e5c6dc | 2009-03-27 12:55:16 -0700 | [diff] [blame] | 1234 | struct musb_qh *qh = hw_ep->out_qh; |
| 1235 | struct urb *urb = next_urb(qh); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1236 | u32 status = 0; |
| 1237 | void __iomem *mbase = musb->mregs; |
| 1238 | struct dma_channel *dma; |
T. S., Anil Kumar | f8afbf7f | 2010-09-24 13:44:09 +0300 | [diff] [blame] | 1239 | bool transfer_pending = false; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1240 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1241 | musb_ep_select(mbase, epnum); |
| 1242 | tx_csr = musb_readw(epio, MUSB_TXCSR); |
| 1243 | |
| 1244 | /* with CPPI, DMA sometimes triggers "extra" irqs */ |
| 1245 | if (!urb) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1246 | dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1247 | return; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1248 | } |
| 1249 | |
| 1250 | pipe = urb->pipe; |
| 1251 | dma = is_dma_capable() ? hw_ep->tx_channel : NULL; |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1252 | dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1253 | dma ? ", dma" : ""); |
| 1254 | |
| 1255 | /* check for errors */ |
| 1256 | if (tx_csr & MUSB_TXCSR_H_RXSTALL) { |
| 1257 | /* dma was disabled, fifo flushed */ |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1258 | dev_dbg(musb->controller, "TX end %d stall\n", epnum); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1259 | |
| 1260 | /* stall; record URB status */ |
| 1261 | status = -EPIPE; |
| 1262 | |
| 1263 | } else if (tx_csr & MUSB_TXCSR_H_ERROR) { |
| 1264 | /* (NON-ISO) dma was disabled, fifo flushed */ |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1265 | dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1266 | |
| 1267 | status = -ETIMEDOUT; |
| 1268 | |
| 1269 | } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { |
Ajay Kumar Gupta | f283862 | 2012-07-19 13:41:59 +0530 | [diff] [blame] | 1270 | if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1 |
| 1271 | && !list_is_singular(&musb->out_bulk)) { |
| 1272 | dev_dbg(musb->controller, |
| 1273 | "NAK timeout on TX%d ep\n", epnum); |
| 1274 | musb_bulk_nak_timeout(musb, hw_ep, 0); |
| 1275 | } else { |
| 1276 | dev_dbg(musb->controller, |
| 1277 | "TX end=%d device not responding\n", epnum); |
| 1278 | /* NOTE: this code path would be a good place to PAUSE a |
| 1279 | * transfer, if there's some other (nonperiodic) tx urb |
| 1280 | * that could use this fifo. (dma complicates it...) |
| 1281 | * That's already done for bulk RX transfers. |
| 1282 | * |
| 1283 | * if (bulk && qh->ring.next != &musb->out_bulk), then |
| 1284 | * we have a candidate... NAKing is *NOT* an error |
| 1285 | */ |
| 1286 | musb_ep_select(mbase, epnum); |
| 1287 | musb_writew(epio, MUSB_TXCSR, |
| 1288 | MUSB_TXCSR_H_WZC_BITS |
| 1289 | | MUSB_TXCSR_TXPKTRDY); |
| 1290 | } |
| 1291 | return; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1292 | } |
| 1293 | |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1294 | done: |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1295 | if (status) { |
| 1296 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1297 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
Daniel Mack | 9c54769 | 2014-05-26 14:52:35 +0200 | [diff] [blame] | 1298 | musb->dma_controller->channel_abort(dma); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1299 | } |
| 1300 | |
| 1301 | /* do the proper sequence to abort the transfer in the |
| 1302 | * usb core; the dma engine should already be stopped. |
| 1303 | */ |
| 1304 | musb_h_tx_flush_fifo(hw_ep); |
| 1305 | tx_csr &= ~(MUSB_TXCSR_AUTOSET |
| 1306 | | MUSB_TXCSR_DMAENAB |
| 1307 | | MUSB_TXCSR_H_ERROR |
| 1308 | | MUSB_TXCSR_H_RXSTALL |
| 1309 | | MUSB_TXCSR_H_NAKTIMEOUT |
| 1310 | ); |
| 1311 | |
| 1312 | musb_ep_select(mbase, epnum); |
| 1313 | musb_writew(epio, MUSB_TXCSR, tx_csr); |
| 1314 | /* REVISIT may need to clear FLUSHFIFO ... */ |
| 1315 | musb_writew(epio, MUSB_TXCSR, tx_csr); |
| 1316 | musb_writeb(epio, MUSB_TXINTERVAL, 0); |
| 1317 | |
| 1318 | done = true; |
| 1319 | } |
| 1320 | |
| 1321 | /* second cppi case */ |
| 1322 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1323 | dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1324 | return; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1325 | } |
| 1326 | |
Sergei Shtylyov | c7bbc05 | 2009-03-26 18:26:40 -0700 | [diff] [blame] | 1327 | if (is_dma_capable() && dma && !status) { |
| 1328 | /* |
| 1329 | * DMA has completed. But if we're using DMA mode 1 (multi |
| 1330 | * packet DMA), we need a terminal TXPKTRDY interrupt before |
| 1331 | * we can consider this transfer completed, lest we trash |
| 1332 | * its last packet when writing the next URB's data. So we |
| 1333 | * switch back to mode 0 to get that interrupt; we'll come |
| 1334 | * back here once it happens. |
| 1335 | */ |
| 1336 | if (tx_csr & MUSB_TXCSR_DMAMODE) { |
| 1337 | /* |
| 1338 | * We shouldn't clear DMAMODE with DMAENAB set; so |
| 1339 | * clear them in a safe order. That should be OK |
| 1340 | * once TXPKTRDY has been set (and I've never seen |
| 1341 | * it being 0 at this moment -- DMA interrupt latency |
| 1342 | * is significant) but if it hasn't been then we have |
| 1343 | * no choice but to stop being polite and ignore the |
| 1344 | * programmer's guide... :-) |
| 1345 | * |
| 1346 | * Note that we must write TXCSR with TXPKTRDY cleared |
| 1347 | * in order not to re-trigger the packet send (this bit |
| 1348 | * can't be cleared by CPU), and there's another caveat: |
| 1349 | * TXPKTRDY may be set shortly and then cleared in the |
| 1350 | * double-buffered FIFO mode, so we do an extra TXCSR |
| 1351 | * read for debouncing... |
| 1352 | */ |
| 1353 | tx_csr &= musb_readw(epio, MUSB_TXCSR); |
| 1354 | if (tx_csr & MUSB_TXCSR_TXPKTRDY) { |
| 1355 | tx_csr &= ~(MUSB_TXCSR_DMAENAB | |
| 1356 | MUSB_TXCSR_TXPKTRDY); |
| 1357 | musb_writew(epio, MUSB_TXCSR, |
| 1358 | tx_csr | MUSB_TXCSR_H_WZC_BITS); |
| 1359 | } |
| 1360 | tx_csr &= ~(MUSB_TXCSR_DMAMODE | |
| 1361 | MUSB_TXCSR_TXPKTRDY); |
| 1362 | musb_writew(epio, MUSB_TXCSR, |
| 1363 | tx_csr | MUSB_TXCSR_H_WZC_BITS); |
| 1364 | |
| 1365 | /* |
| 1366 | * There is no guarantee that we'll get an interrupt |
| 1367 | * after clearing DMAMODE as we might have done this |
| 1368 | * too late (after TXPKTRDY was cleared by controller). |
| 1369 | * Re-read TXCSR as we have spoiled its previous value. |
| 1370 | */ |
| 1371 | tx_csr = musb_readw(epio, MUSB_TXCSR); |
| 1372 | } |
| 1373 | |
| 1374 | /* |
| 1375 | * We may get here from a DMA completion or TXPKTRDY interrupt. |
| 1376 | * In any case, we must check the FIFO status here and bail out |
| 1377 | * only if the FIFO still has data -- that should prevent the |
| 1378 | * "missed" TXPKTRDY interrupts and deal with double-buffered |
| 1379 | * FIFO mode too... |
| 1380 | */ |
| 1381 | if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1382 | dev_dbg(musb->controller, "DMA complete but packet still in FIFO, " |
Sergei Shtylyov | c7bbc05 | 2009-03-26 18:26:40 -0700 | [diff] [blame] | 1383 | "CSR %04x\n", tx_csr); |
| 1384 | return; |
| 1385 | } |
| 1386 | } |
| 1387 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1388 | if (!status || dma || usb_pipeisoc(pipe)) { |
| 1389 | if (dma) |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1390 | length = dma->actual_len; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1391 | else |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1392 | length = qh->segsize; |
| 1393 | qh->offset += length; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1394 | |
| 1395 | if (usb_pipeisoc(pipe)) { |
| 1396 | struct usb_iso_packet_descriptor *d; |
| 1397 | |
| 1398 | d = urb->iso_frame_desc + qh->iso_idx; |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1399 | d->actual_length = length; |
| 1400 | d->status = status; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1401 | if (++qh->iso_idx >= urb->number_of_packets) { |
| 1402 | done = true; |
| 1403 | } else { |
| 1404 | d++; |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1405 | offset = d->offset; |
| 1406 | length = d->length; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1407 | } |
T. S., Anil Kumar | f8afbf7f | 2010-09-24 13:44:09 +0300 | [diff] [blame] | 1408 | } else if (dma && urb->transfer_buffer_length == qh->offset) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1409 | done = true; |
| 1410 | } else { |
| 1411 | /* see if we need to send more data, or ZLP */ |
| 1412 | if (qh->segsize < qh->maxpacket) |
| 1413 | done = true; |
| 1414 | else if (qh->offset == urb->transfer_buffer_length |
| 1415 | && !(urb->transfer_flags |
| 1416 | & URB_ZERO_PACKET)) |
| 1417 | done = true; |
| 1418 | if (!done) { |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1419 | offset = qh->offset; |
| 1420 | length = urb->transfer_buffer_length - offset; |
T. S., Anil Kumar | f8afbf7f | 2010-09-24 13:44:09 +0300 | [diff] [blame] | 1421 | transfer_pending = true; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1422 | } |
| 1423 | } |
| 1424 | } |
| 1425 | |
| 1426 | /* urb->status != -EINPROGRESS means request has been faulted, |
| 1427 | * so we must abort this transfer after cleanup |
| 1428 | */ |
| 1429 | if (urb->status != -EINPROGRESS) { |
| 1430 | done = true; |
| 1431 | if (status == 0) |
| 1432 | status = urb->status; |
| 1433 | } |
| 1434 | |
| 1435 | if (done) { |
| 1436 | /* set status */ |
| 1437 | urb->status = status; |
| 1438 | urb->actual_length = qh->offset; |
| 1439 | musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1440 | return; |
T. S., Anil Kumar | f8afbf7f | 2010-09-24 13:44:09 +0300 | [diff] [blame] | 1441 | } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) { |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1442 | if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, |
Ajay Kumar Gupta | dfeffa5 | 2009-11-17 15:22:55 +0530 | [diff] [blame] | 1443 | offset, length)) { |
| 1444 | if (is_cppi_enabled() || tusb_dma_omap()) |
| 1445 | musb_h_tx_dma_start(hw_ep); |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1446 | return; |
Ajay Kumar Gupta | dfeffa5 | 2009-11-17 15:22:55 +0530 | [diff] [blame] | 1447 | } |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1448 | } else if (tx_csr & MUSB_TXCSR_DMAENAB) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1449 | dev_dbg(musb->controller, "not complete, but DMA enabled?\n"); |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1450 | return; |
| 1451 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1452 | |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1453 | /* |
| 1454 | * PIO: start next packet in this URB. |
| 1455 | * |
| 1456 | * REVISIT: some docs say that when hw_ep->tx_double_buffered, |
| 1457 | * (and presumably, FIFO is not half-full) we should write *two* |
| 1458 | * packets before updating TXCSR; other docs disagree... |
| 1459 | */ |
| 1460 | if (length > qh->maxpacket) |
| 1461 | length = qh->maxpacket; |
Maulik Mankad | 496dda7 | 2010-09-24 13:44:06 +0300 | [diff] [blame] | 1462 | /* Unmap the buffer so that CPU can use it */ |
Daniel Mack | 8b125df | 2013-04-10 21:55:50 +0200 | [diff] [blame] | 1463 | usb_hcd_unmap_urb_for_dma(musb->hcd, urb); |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1464 | |
| 1465 | /* |
| 1466 | * We need to map sg if the transfer_buffer is |
| 1467 | * NULL. |
| 1468 | */ |
| 1469 | if (!urb->transfer_buffer) |
Virupax Sadashivpetimath | ed74df1 | 2013-04-24 08:38:48 +0200 | [diff] [blame] | 1470 | qh->use_sg = true; |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1471 | |
Virupax Sadashivpetimath | ed74df1 | 2013-04-24 08:38:48 +0200 | [diff] [blame] | 1472 | if (qh->use_sg) { |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1473 | /* sg_miter_start is already done in musb_ep_program */ |
| 1474 | if (!sg_miter_next(&qh->sg_miter)) { |
| 1475 | dev_err(musb->controller, "error: sg list empty\n"); |
| 1476 | sg_miter_stop(&qh->sg_miter); |
| 1477 | status = -EINVAL; |
| 1478 | goto done; |
| 1479 | } |
| 1480 | urb->transfer_buffer = qh->sg_miter.addr; |
| 1481 | length = min_t(u32, length, qh->sg_miter.length); |
| 1482 | musb_write_fifo(hw_ep, length, urb->transfer_buffer); |
| 1483 | qh->sg_miter.consumed = length; |
| 1484 | sg_miter_stop(&qh->sg_miter); |
| 1485 | } else { |
| 1486 | musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); |
| 1487 | } |
| 1488 | |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1489 | qh->segsize = length; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1490 | |
Virupax Sadashivpetimath | ed74df1 | 2013-04-24 08:38:48 +0200 | [diff] [blame] | 1491 | if (qh->use_sg) { |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1492 | if (offset + length >= urb->transfer_buffer_length) |
Virupax Sadashivpetimath | ed74df1 | 2013-04-24 08:38:48 +0200 | [diff] [blame] | 1493 | qh->use_sg = false; |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1494 | } |
| 1495 | |
Sergei Shtylyov | 6b6e971 | 2009-03-26 18:29:19 -0700 | [diff] [blame] | 1496 | musb_ep_select(mbase, epnum); |
| 1497 | musb_writew(epio, MUSB_TXCSR, |
| 1498 | MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1499 | } |
| 1500 | |
| 1501 | |
| 1502 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 1503 | |
| 1504 | /* Host side RX (IN) using Mentor DMA works as follows: |
| 1505 | submit_urb -> |
| 1506 | - if queue was empty, ProgramEndpoint |
| 1507 | - first IN token is sent out (by setting ReqPkt) |
| 1508 | LinuxIsr -> RxReady() |
| 1509 | /\ => first packet is received |
| 1510 | | - Set in mode 0 (DmaEnab, ~ReqPkt) |
| 1511 | | -> DMA Isr (transfer complete) -> RxReady() |
| 1512 | | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) |
| 1513 | | - if urb not complete, send next IN token (ReqPkt) |
| 1514 | | | else complete urb. |
| 1515 | | | |
| 1516 | --------------------------- |
| 1517 | * |
| 1518 | * Nuances of mode 1: |
| 1519 | * For short packets, no ack (+RxPktRdy) is sent automatically |
| 1520 | * (even if AutoClear is ON) |
| 1521 | * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent |
| 1522 | * automatically => major problem, as collecting the next packet becomes |
| 1523 | * difficult. Hence mode 1 is not used. |
| 1524 | * |
| 1525 | * REVISIT |
| 1526 | * All we care about at this driver level is that |
| 1527 | * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; |
| 1528 | * (b) termination conditions are: short RX, or buffer full; |
| 1529 | * (c) fault modes include |
| 1530 | * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. |
| 1531 | * (and that endpoint's dma queue stops immediately) |
| 1532 | * - overflow (full, PLUS more bytes in the terminal packet) |
| 1533 | * |
| 1534 | * So for example, usb-storage sets URB_SHORT_NOT_OK, and would |
| 1535 | * thus be a great candidate for using mode 1 ... for all but the |
| 1536 | * last packet of one URB's transfer. |
| 1537 | */ |
| 1538 | |
| 1539 | #endif |
| 1540 | |
| 1541 | /* |
| 1542 | * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, |
| 1543 | * and high-bandwidth IN transfer cases. |
| 1544 | */ |
| 1545 | void musb_host_rx(struct musb *musb, u8 epnum) |
| 1546 | { |
| 1547 | struct urb *urb; |
| 1548 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 1549 | void __iomem *epio = hw_ep->regs; |
| 1550 | struct musb_qh *qh = hw_ep->in_qh; |
| 1551 | size_t xfer_len; |
| 1552 | void __iomem *mbase = musb->mregs; |
| 1553 | int pipe; |
| 1554 | u16 rx_csr, val; |
| 1555 | bool iso_err = false; |
| 1556 | bool done = false; |
| 1557 | u32 status; |
| 1558 | struct dma_channel *dma; |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1559 | unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1560 | |
| 1561 | musb_ep_select(mbase, epnum); |
| 1562 | |
| 1563 | urb = next_urb(qh); |
| 1564 | dma = is_dma_capable() ? hw_ep->rx_channel : NULL; |
| 1565 | status = 0; |
| 1566 | xfer_len = 0; |
| 1567 | |
| 1568 | rx_csr = musb_readw(epio, MUSB_RXCSR); |
| 1569 | val = rx_csr; |
| 1570 | |
| 1571 | if (unlikely(!urb)) { |
| 1572 | /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least |
| 1573 | * usbtest #11 (unlinks) triggers it regularly, sometimes |
| 1574 | * with fifo full. (Only with DMA??) |
| 1575 | */ |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1576 | dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1577 | musb_readw(epio, MUSB_RXCOUNT)); |
| 1578 | musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); |
| 1579 | return; |
| 1580 | } |
| 1581 | |
| 1582 | pipe = urb->pipe; |
| 1583 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1584 | dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1585 | epnum, rx_csr, urb->actual_length, |
| 1586 | dma ? dma->actual_len : 0); |
| 1587 | |
| 1588 | /* check for errors, concurrent stall & unlink is not really |
| 1589 | * handled yet! */ |
| 1590 | if (rx_csr & MUSB_RXCSR_H_RXSTALL) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1591 | dev_dbg(musb->controller, "RX end %d STALL\n", epnum); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1592 | |
| 1593 | /* stall; record URB status */ |
| 1594 | status = -EPIPE; |
| 1595 | |
| 1596 | } else if (rx_csr & MUSB_RXCSR_H_ERROR) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1597 | dev_dbg(musb->controller, "end %d RX proto error\n", epnum); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1598 | |
| 1599 | status = -EPROTO; |
| 1600 | musb_writeb(epio, MUSB_RXINTERVAL, 0); |
| 1601 | |
| 1602 | } else if (rx_csr & MUSB_RXCSR_DATAERROR) { |
| 1603 | |
| 1604 | if (USB_ENDPOINT_XFER_ISOC != qh->type) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1605 | dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum); |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 1606 | |
| 1607 | /* NOTE: NAKing is *NOT* an error, so we want to |
| 1608 | * continue. Except ... if there's a request for |
| 1609 | * another QH, use that instead of starving it. |
| 1610 | * |
| 1611 | * Devices like Ethernet and serial adapters keep |
| 1612 | * reads posted at all times, which will starve |
| 1613 | * other devices without this logic. |
| 1614 | */ |
| 1615 | if (usb_pipebulk(urb->pipe) |
| 1616 | && qh->mux == 1 |
| 1617 | && !list_is_singular(&musb->in_bulk)) { |
Ajay Kumar Gupta | f283862 | 2012-07-19 13:41:59 +0530 | [diff] [blame] | 1618 | musb_bulk_nak_timeout(musb, hw_ep, 1); |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 1619 | return; |
| 1620 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1621 | musb_ep_select(mbase, epnum); |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 1622 | rx_csr |= MUSB_RXCSR_H_WZC_BITS; |
| 1623 | rx_csr &= ~MUSB_RXCSR_DATAERROR; |
| 1624 | musb_writew(epio, MUSB_RXCSR, rx_csr); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1625 | |
| 1626 | goto finish; |
| 1627 | } else { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1628 | dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1629 | /* packet error reported later */ |
| 1630 | iso_err = true; |
| 1631 | } |
Ajay Kumar Gupta | a483d70 | 2009-04-03 16:16:17 -0700 | [diff] [blame] | 1632 | } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1633 | dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n", |
Ajay Kumar Gupta | a483d70 | 2009-04-03 16:16:17 -0700 | [diff] [blame] | 1634 | epnum); |
| 1635 | status = -EPROTO; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1636 | } |
| 1637 | |
| 1638 | /* faults abort the transfer */ |
| 1639 | if (status) { |
| 1640 | /* clean up dma and collect transfer count */ |
| 1641 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1642 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
Daniel Mack | 9c54769 | 2014-05-26 14:52:35 +0200 | [diff] [blame] | 1643 | musb->dma_controller->channel_abort(dma); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1644 | xfer_len = dma->actual_len; |
| 1645 | } |
| 1646 | musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); |
| 1647 | musb_writeb(epio, MUSB_RXINTERVAL, 0); |
| 1648 | done = true; |
| 1649 | goto finish; |
| 1650 | } |
| 1651 | |
| 1652 | if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { |
| 1653 | /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ |
| 1654 | ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); |
| 1655 | goto finish; |
| 1656 | } |
| 1657 | |
| 1658 | /* thorough shutdown for now ... given more precise fault handling |
| 1659 | * and better queueing support, we might keep a DMA pipeline going |
| 1660 | * while processing this irq for earlier completions. |
| 1661 | */ |
| 1662 | |
| 1663 | /* FIXME this is _way_ too much in-line logic for Mentor DMA */ |
| 1664 | |
Mian Yousaf Kaukab | aee5500 | 2013-05-15 14:03:24 +0200 | [diff] [blame] | 1665 | #if !defined(CONFIG_USB_INVENTRA_DMA) && !defined(CONFIG_USB_UX500_DMA) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1666 | if (rx_csr & MUSB_RXCSR_H_REQPKT) { |
| 1667 | /* REVISIT this happened for a while on some short reads... |
| 1668 | * the cleanup still needs investigation... looks bad... |
| 1669 | * and also duplicates dma cleanup code above ... plus, |
| 1670 | * shouldn't this be the "half full" double buffer case? |
| 1671 | */ |
| 1672 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1673 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
Daniel Mack | 9c54769 | 2014-05-26 14:52:35 +0200 | [diff] [blame] | 1674 | musb->dma_controller->channel_abort(dma); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1675 | xfer_len = dma->actual_len; |
| 1676 | done = true; |
| 1677 | } |
| 1678 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1679 | dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1680 | xfer_len, dma ? ", dma" : ""); |
| 1681 | rx_csr &= ~MUSB_RXCSR_H_REQPKT; |
| 1682 | |
| 1683 | musb_ep_select(mbase, epnum); |
| 1684 | musb_writew(epio, MUSB_RXCSR, |
| 1685 | MUSB_RXCSR_H_WZC_BITS | rx_csr); |
| 1686 | } |
| 1687 | #endif |
| 1688 | if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { |
| 1689 | xfer_len = dma->actual_len; |
| 1690 | |
| 1691 | val &= ~(MUSB_RXCSR_DMAENAB |
| 1692 | | MUSB_RXCSR_H_AUTOREQ |
| 1693 | | MUSB_RXCSR_AUTOCLEAR |
| 1694 | | MUSB_RXCSR_RXPKTRDY); |
| 1695 | musb_writew(hw_ep->regs, MUSB_RXCSR, val); |
| 1696 | |
George Cherian | c57c41d2 | 2014-01-27 15:07:24 +0530 | [diff] [blame] | 1697 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \ |
| 1698 | defined(CONFIG_USB_TI_CPPI41_DMA) |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1699 | if (usb_pipeisoc(pipe)) { |
| 1700 | struct usb_iso_packet_descriptor *d; |
| 1701 | |
| 1702 | d = urb->iso_frame_desc + qh->iso_idx; |
| 1703 | d->actual_length = xfer_len; |
| 1704 | |
| 1705 | /* even if there was an error, we did the dma |
| 1706 | * for iso_frame_desc->length |
| 1707 | */ |
Márton Németh | 72887c8 | 2011-05-30 20:45:42 +0200 | [diff] [blame] | 1708 | if (d->status != -EILSEQ && d->status != -EOVERFLOW) |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1709 | d->status = 0; |
| 1710 | |
George Cherian | c57c41d2 | 2014-01-27 15:07:24 +0530 | [diff] [blame] | 1711 | if (++qh->iso_idx >= urb->number_of_packets) { |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1712 | done = true; |
George Cherian | c57c41d2 | 2014-01-27 15:07:24 +0530 | [diff] [blame] | 1713 | } else { |
| 1714 | #if defined(CONFIG_USB_TI_CPPI41_DMA) |
| 1715 | struct dma_controller *c; |
| 1716 | dma_addr_t *buf; |
| 1717 | u32 length, ret; |
| 1718 | |
| 1719 | c = musb->dma_controller; |
| 1720 | buf = (void *) |
| 1721 | urb->iso_frame_desc[qh->iso_idx].offset |
| 1722 | + (u32)urb->transfer_dma; |
| 1723 | |
| 1724 | length = |
| 1725 | urb->iso_frame_desc[qh->iso_idx].length; |
| 1726 | |
| 1727 | val |= MUSB_RXCSR_DMAENAB; |
| 1728 | musb_writew(hw_ep->regs, MUSB_RXCSR, val); |
| 1729 | |
| 1730 | ret = c->channel_program(dma, qh->maxpacket, |
| 1731 | 0, (u32) buf, length); |
| 1732 | #endif |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1733 | done = false; |
George Cherian | c57c41d2 | 2014-01-27 15:07:24 +0530 | [diff] [blame] | 1734 | } |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1735 | |
| 1736 | } else { |
Daniel Mack | 49a9e88 | 2014-05-26 14:52:40 +0200 | [diff] [blame] | 1737 | /* done if urb buffer is full or short packet is recd */ |
| 1738 | done = (urb->actual_length + xfer_len >= |
| 1739 | urb->transfer_buffer_length |
| 1740 | || dma->actual_len < qh->maxpacket |
| 1741 | || dma->rx_packet_done); |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1742 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1743 | |
| 1744 | /* send IN token for next packet, without AUTOREQ */ |
| 1745 | if (!done) { |
| 1746 | val |= MUSB_RXCSR_H_REQPKT; |
| 1747 | musb_writew(epio, MUSB_RXCSR, |
| 1748 | MUSB_RXCSR_H_WZC_BITS | val); |
| 1749 | } |
| 1750 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1751 | dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1752 | done ? "off" : "reset", |
| 1753 | musb_readw(epio, MUSB_RXCSR), |
| 1754 | musb_readw(epio, MUSB_RXCOUNT)); |
| 1755 | #else |
| 1756 | done = true; |
| 1757 | #endif |
| 1758 | } else if (urb->status == -EINPROGRESS) { |
| 1759 | /* if no errors, be sure a packet is ready for unloading */ |
| 1760 | if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { |
| 1761 | status = -EPROTO; |
| 1762 | ERR("Rx interrupt with no errors or packet!\n"); |
| 1763 | |
| 1764 | /* FIXME this is another "SHOULD NEVER HAPPEN" */ |
| 1765 | |
| 1766 | /* SCRUB (RX) */ |
| 1767 | /* do the proper sequence to abort the transfer */ |
| 1768 | musb_ep_select(mbase, epnum); |
| 1769 | val &= ~MUSB_RXCSR_H_REQPKT; |
| 1770 | musb_writew(epio, MUSB_RXCSR, val); |
| 1771 | goto finish; |
| 1772 | } |
| 1773 | |
| 1774 | /* we are expecting IN packets */ |
George Cherian | c57c41d2 | 2014-01-27 15:07:24 +0530 | [diff] [blame] | 1775 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \ |
| 1776 | defined(CONFIG_USB_TI_CPPI41_DMA) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1777 | if (dma) { |
| 1778 | struct dma_controller *c; |
| 1779 | u16 rx_count; |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1780 | int ret, length; |
| 1781 | dma_addr_t buf; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1782 | |
| 1783 | rx_count = musb_readw(epio, MUSB_RXCOUNT); |
| 1784 | |
Felipe Balbi | 91e3af6 | 2013-05-30 03:06:27 +0300 | [diff] [blame] | 1785 | dev_dbg(musb->controller, "RX%d count %d, buffer 0x%llx len %d/%d\n", |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1786 | epnum, rx_count, |
Felipe Balbi | 91e3af6 | 2013-05-30 03:06:27 +0300 | [diff] [blame] | 1787 | (unsigned long long) urb->transfer_dma |
| 1788 | + urb->actual_length, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1789 | qh->offset, |
| 1790 | urb->transfer_buffer_length); |
| 1791 | |
| 1792 | c = musb->dma_controller; |
| 1793 | |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1794 | if (usb_pipeisoc(pipe)) { |
Felipe Balbi | 8b4959d | 2009-12-04 15:47:47 +0200 | [diff] [blame] | 1795 | int d_status = 0; |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1796 | struct usb_iso_packet_descriptor *d; |
| 1797 | |
| 1798 | d = urb->iso_frame_desc + qh->iso_idx; |
| 1799 | |
| 1800 | if (iso_err) { |
Felipe Balbi | 8b4959d | 2009-12-04 15:47:47 +0200 | [diff] [blame] | 1801 | d_status = -EILSEQ; |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1802 | urb->error_count++; |
| 1803 | } |
| 1804 | if (rx_count > d->length) { |
Felipe Balbi | 8b4959d | 2009-12-04 15:47:47 +0200 | [diff] [blame] | 1805 | if (d_status == 0) { |
| 1806 | d_status = -EOVERFLOW; |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1807 | urb->error_count++; |
| 1808 | } |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1809 | dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\ |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1810 | rx_count, d->length); |
| 1811 | |
| 1812 | length = d->length; |
| 1813 | } else |
| 1814 | length = rx_count; |
Felipe Balbi | 8b4959d | 2009-12-04 15:47:47 +0200 | [diff] [blame] | 1815 | d->status = d_status; |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1816 | buf = urb->transfer_dma + d->offset; |
| 1817 | } else { |
| 1818 | length = rx_count; |
| 1819 | buf = urb->transfer_dma + |
| 1820 | urb->actual_length; |
| 1821 | } |
| 1822 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1823 | dma->desired_mode = 0; |
| 1824 | #ifdef USE_MODE1 |
| 1825 | /* because of the issue below, mode 1 will |
| 1826 | * only rarely behave with correct semantics. |
| 1827 | */ |
| 1828 | if ((urb->transfer_flags & |
| 1829 | URB_SHORT_NOT_OK) |
| 1830 | && (urb->transfer_buffer_length - |
| 1831 | urb->actual_length) |
| 1832 | > qh->maxpacket) |
| 1833 | dma->desired_mode = 1; |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1834 | if (rx_count < hw_ep->max_packet_sz_rx) { |
| 1835 | length = rx_count; |
Sonic Zhang | ae92697 | 2010-03-08 11:26:01 -0500 | [diff] [blame] | 1836 | dma->desired_mode = 0; |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1837 | } else { |
| 1838 | length = urb->transfer_buffer_length; |
| 1839 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1840 | #endif |
| 1841 | |
| 1842 | /* Disadvantage of using mode 1: |
| 1843 | * It's basically usable only for mass storage class; essentially all |
| 1844 | * other protocols also terminate transfers on short packets. |
| 1845 | * |
| 1846 | * Details: |
| 1847 | * An extra IN token is sent at the end of the transfer (due to AUTOREQ) |
| 1848 | * If you try to use mode 1 for (transfer_buffer_length - 512), and try |
| 1849 | * to use the extra IN token to grab the last packet using mode 0, then |
| 1850 | * the problem is that you cannot be sure when the device will send the |
| 1851 | * last packet and RxPktRdy set. Sometimes the packet is recd too soon |
| 1852 | * such that it gets lost when RxCSR is re-set at the end of the mode 1 |
| 1853 | * transfer, while sometimes it is recd just a little late so that if you |
| 1854 | * try to configure for mode 0 soon after the mode 1 transfer is |
| 1855 | * completed, you will find rxcount 0. Okay, so you might think why not |
| 1856 | * wait for an interrupt when the pkt is recd. Well, you won't get any! |
| 1857 | */ |
| 1858 | |
| 1859 | val = musb_readw(epio, MUSB_RXCSR); |
| 1860 | val &= ~MUSB_RXCSR_H_REQPKT; |
| 1861 | |
| 1862 | if (dma->desired_mode == 0) |
| 1863 | val &= ~MUSB_RXCSR_H_AUTOREQ; |
| 1864 | else |
| 1865 | val |= MUSB_RXCSR_H_AUTOREQ; |
Ajay Kumar Gupta | a483d70 | 2009-04-03 16:16:17 -0700 | [diff] [blame] | 1866 | val |= MUSB_RXCSR_DMAENAB; |
| 1867 | |
| 1868 | /* autoclear shouldn't be set in high bandwidth */ |
| 1869 | if (qh->hb_mult == 1) |
| 1870 | val |= MUSB_RXCSR_AUTOCLEAR; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1871 | |
| 1872 | musb_writew(epio, MUSB_RXCSR, |
| 1873 | MUSB_RXCSR_H_WZC_BITS | val); |
| 1874 | |
| 1875 | /* REVISIT if when actual_length != 0, |
| 1876 | * transfer_buffer_length needs to be |
| 1877 | * adjusted first... |
| 1878 | */ |
| 1879 | ret = c->channel_program( |
| 1880 | dma, qh->maxpacket, |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1881 | dma->desired_mode, buf, length); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1882 | |
| 1883 | if (!ret) { |
| 1884 | c->channel_release(dma); |
| 1885 | hw_ep->rx_channel = NULL; |
| 1886 | dma = NULL; |
Mantesh Sarasetti | 2ed9127 | 2012-06-01 14:54:30 +0300 | [diff] [blame] | 1887 | val = musb_readw(epio, MUSB_RXCSR); |
| 1888 | val &= ~(MUSB_RXCSR_DMAENAB |
| 1889 | | MUSB_RXCSR_H_AUTOREQ |
| 1890 | | MUSB_RXCSR_AUTOCLEAR); |
| 1891 | musb_writew(epio, MUSB_RXCSR, val); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1892 | } |
| 1893 | } |
| 1894 | #endif /* Mentor DMA */ |
| 1895 | |
| 1896 | if (!dma) { |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1897 | unsigned int received_len; |
| 1898 | |
Maulik Mankad | 496dda7 | 2010-09-24 13:44:06 +0300 | [diff] [blame] | 1899 | /* Unmap the buffer so that CPU can use it */ |
Daniel Mack | 8b125df | 2013-04-10 21:55:50 +0200 | [diff] [blame] | 1900 | usb_hcd_unmap_urb_for_dma(musb->hcd, urb); |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1901 | |
| 1902 | /* |
| 1903 | * We need to map sg if the transfer_buffer is |
| 1904 | * NULL. |
| 1905 | */ |
| 1906 | if (!urb->transfer_buffer) { |
Virupax Sadashivpetimath | ed74df1 | 2013-04-24 08:38:48 +0200 | [diff] [blame] | 1907 | qh->use_sg = true; |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1908 | sg_miter_start(&qh->sg_miter, urb->sg, 1, |
| 1909 | sg_flags); |
| 1910 | } |
| 1911 | |
Virupax Sadashivpetimath | ed74df1 | 2013-04-24 08:38:48 +0200 | [diff] [blame] | 1912 | if (qh->use_sg) { |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1913 | if (!sg_miter_next(&qh->sg_miter)) { |
| 1914 | dev_err(musb->controller, "error: sg list empty\n"); |
| 1915 | sg_miter_stop(&qh->sg_miter); |
| 1916 | status = -EINVAL; |
| 1917 | done = true; |
| 1918 | goto finish; |
| 1919 | } |
| 1920 | urb->transfer_buffer = qh->sg_miter.addr; |
| 1921 | received_len = urb->actual_length; |
| 1922 | qh->offset = 0x0; |
| 1923 | done = musb_host_packet_rx(musb, urb, epnum, |
| 1924 | iso_err); |
| 1925 | /* Calculate the number of bytes received */ |
| 1926 | received_len = urb->actual_length - |
| 1927 | received_len; |
| 1928 | qh->sg_miter.consumed = received_len; |
| 1929 | sg_miter_stop(&qh->sg_miter); |
| 1930 | } else { |
| 1931 | done = musb_host_packet_rx(musb, urb, |
| 1932 | epnum, iso_err); |
| 1933 | } |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 1934 | dev_dbg(musb->controller, "read %spacket\n", done ? "last " : ""); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1935 | } |
| 1936 | } |
| 1937 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1938 | finish: |
| 1939 | urb->actual_length += xfer_len; |
| 1940 | qh->offset += xfer_len; |
| 1941 | if (done) { |
Virupax Sadashivpetimath | ed74df1 | 2013-04-24 08:38:48 +0200 | [diff] [blame] | 1942 | if (qh->use_sg) |
| 1943 | qh->use_sg = false; |
Virupax Sadashivpetimath | 8e8a551 | 2012-08-07 14:46:20 +0530 | [diff] [blame] | 1944 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1945 | if (urb->status == -EINPROGRESS) |
| 1946 | urb->status = status; |
| 1947 | musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); |
| 1948 | } |
| 1949 | } |
| 1950 | |
| 1951 | /* schedule nodes correspond to peripheral endpoints, like an OHCI QH. |
| 1952 | * the software schedule associates multiple such nodes with a given |
| 1953 | * host side hardware endpoint + direction; scheduling may activate |
| 1954 | * that hardware endpoint. |
| 1955 | */ |
| 1956 | static int musb_schedule( |
| 1957 | struct musb *musb, |
| 1958 | struct musb_qh *qh, |
| 1959 | int is_in) |
| 1960 | { |
Rickard Strandqvist | eac44dc | 2014-06-01 15:48:12 +0200 | [diff] [blame] | 1961 | int idle = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1962 | int best_diff; |
| 1963 | int best_end, epnum; |
| 1964 | struct musb_hw_ep *hw_ep = NULL; |
| 1965 | struct list_head *head = NULL; |
Swaminathan S | 5274dab | 2009-12-28 13:40:37 +0200 | [diff] [blame] | 1966 | u8 toggle; |
| 1967 | u8 txtype; |
| 1968 | struct urb *urb = next_urb(qh); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1969 | |
| 1970 | /* use fixed hardware for control and bulk */ |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 1971 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1972 | head = &musb->control; |
| 1973 | hw_ep = musb->control_ep; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1974 | goto success; |
| 1975 | } |
| 1976 | |
| 1977 | /* else, periodic transfers get muxed to other endpoints */ |
| 1978 | |
Sergei Shtylyov | 5d67a85 | 2009-02-24 15:23:34 -0800 | [diff] [blame] | 1979 | /* |
| 1980 | * We know this qh hasn't been scheduled, so all we need to do |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1981 | * is choose which hardware endpoint to put it on ... |
| 1982 | * |
| 1983 | * REVISIT what we really want here is a regular schedule tree |
Sergei Shtylyov | 5d67a85 | 2009-02-24 15:23:34 -0800 | [diff] [blame] | 1984 | * like e.g. OHCI uses. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1985 | */ |
| 1986 | best_diff = 4096; |
| 1987 | best_end = -1; |
| 1988 | |
Sergei Shtylyov | 5d67a85 | 2009-02-24 15:23:34 -0800 | [diff] [blame] | 1989 | for (epnum = 1, hw_ep = musb->endpoints + 1; |
| 1990 | epnum < musb->nr_endpoints; |
| 1991 | epnum++, hw_ep++) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1992 | int diff; |
| 1993 | |
Sergei Shtylyov | 3e5c6dc | 2009-03-27 12:55:16 -0700 | [diff] [blame] | 1994 | if (musb_ep_get_qh(hw_ep, is_in) != NULL) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1995 | continue; |
Sergei Shtylyov | 5d67a85 | 2009-02-24 15:23:34 -0800 | [diff] [blame] | 1996 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1997 | if (hw_ep == musb->bulk_ep) |
| 1998 | continue; |
| 1999 | |
| 2000 | if (is_in) |
Ajay Kumar Gupta | a483d70 | 2009-04-03 16:16:17 -0700 | [diff] [blame] | 2001 | diff = hw_ep->max_packet_sz_rx; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2002 | else |
Ajay Kumar Gupta | a483d70 | 2009-04-03 16:16:17 -0700 | [diff] [blame] | 2003 | diff = hw_ep->max_packet_sz_tx; |
| 2004 | diff -= (qh->maxpacket * qh->hb_mult); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2005 | |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 2006 | if (diff >= 0 && best_diff > diff) { |
Swaminathan S | 5274dab | 2009-12-28 13:40:37 +0200 | [diff] [blame] | 2007 | |
| 2008 | /* |
| 2009 | * Mentor controller has a bug in that if we schedule |
| 2010 | * a BULK Tx transfer on an endpoint that had earlier |
| 2011 | * handled ISOC then the BULK transfer has to start on |
| 2012 | * a zero toggle. If the BULK transfer starts on a 1 |
| 2013 | * toggle then this transfer will fail as the mentor |
| 2014 | * controller starts the Bulk transfer on a 0 toggle |
| 2015 | * irrespective of the programming of the toggle bits |
| 2016 | * in the TXCSR register. Check for this condition |
| 2017 | * while allocating the EP for a Tx Bulk transfer. If |
| 2018 | * so skip this EP. |
| 2019 | */ |
| 2020 | hw_ep = musb->endpoints + epnum; |
| 2021 | toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); |
| 2022 | txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) |
| 2023 | >> 4) & 0x3; |
| 2024 | if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && |
| 2025 | toggle && (txtype == USB_ENDPOINT_XFER_ISOC)) |
| 2026 | continue; |
| 2027 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2028 | best_diff = diff; |
| 2029 | best_end = epnum; |
| 2030 | } |
| 2031 | } |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 2032 | /* use bulk reserved ep1 if no other ep is free */ |
Felipe Balbi | aa5cbbe | 2008-11-17 09:08:16 +0200 | [diff] [blame] | 2033 | if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 2034 | hw_ep = musb->bulk_ep; |
| 2035 | if (is_in) |
| 2036 | head = &musb->in_bulk; |
| 2037 | else |
| 2038 | head = &musb->out_bulk; |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 2039 | |
Ajay Kumar Gupta | f283862 | 2012-07-19 13:41:59 +0530 | [diff] [blame] | 2040 | /* Enable bulk RX/TX NAK timeout scheme when bulk requests are |
Rahul Bedarkar | 5ae477b | 2014-01-02 19:27:47 +0530 | [diff] [blame] | 2041 | * multiplexed. This scheme does not work in high speed to full |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 2042 | * speed scenario as NAK interrupts are not coming from a |
| 2043 | * full speed device connected to a high speed device. |
| 2044 | * NAK timeout interval is 8 (128 uframe or 16ms) for HS and |
| 2045 | * 4 (8 frame or 8ms) for FS device. |
| 2046 | */ |
Ajay Kumar Gupta | f283862 | 2012-07-19 13:41:59 +0530 | [diff] [blame] | 2047 | if (qh->dev) |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 2048 | qh->intv_reg = |
| 2049 | (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 2050 | goto success; |
| 2051 | } else if (best_end < 0) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2052 | return -ENOSPC; |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 2053 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2054 | |
| 2055 | idle = 1; |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 2056 | qh->mux = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2057 | hw_ep = musb->endpoints + best_end; |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 2058 | dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2059 | success: |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 2060 | if (head) { |
| 2061 | idle = list_empty(head); |
| 2062 | list_add_tail(&qh->ring, head); |
| 2063 | qh->mux = 1; |
| 2064 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2065 | qh->hw_ep = hw_ep; |
| 2066 | qh->hep->hcpriv = qh; |
| 2067 | if (idle) |
| 2068 | musb_start_urb(musb, is_in, qh); |
| 2069 | return 0; |
| 2070 | } |
| 2071 | |
| 2072 | static int musb_urb_enqueue( |
| 2073 | struct usb_hcd *hcd, |
| 2074 | struct urb *urb, |
| 2075 | gfp_t mem_flags) |
| 2076 | { |
| 2077 | unsigned long flags; |
| 2078 | struct musb *musb = hcd_to_musb(hcd); |
| 2079 | struct usb_host_endpoint *hep = urb->ep; |
David Brownell | 74bb350 | 2009-03-26 17:36:57 -0700 | [diff] [blame] | 2080 | struct musb_qh *qh; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2081 | struct usb_endpoint_descriptor *epd = &hep->desc; |
| 2082 | int ret; |
| 2083 | unsigned type_reg; |
| 2084 | unsigned interval; |
| 2085 | |
| 2086 | /* host role must be active */ |
| 2087 | if (!is_host_active(musb) || !musb->is_active) |
| 2088 | return -ENODEV; |
| 2089 | |
| 2090 | spin_lock_irqsave(&musb->lock, flags); |
| 2091 | ret = usb_hcd_link_urb_to_ep(hcd, urb); |
David Brownell | 74bb350 | 2009-03-26 17:36:57 -0700 | [diff] [blame] | 2092 | qh = ret ? NULL : hep->hcpriv; |
| 2093 | if (qh) |
| 2094 | urb->hcpriv = qh; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2095 | spin_unlock_irqrestore(&musb->lock, flags); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2096 | |
| 2097 | /* DMA mapping was already done, if needed, and this urb is on |
David Brownell | 74bb350 | 2009-03-26 17:36:57 -0700 | [diff] [blame] | 2098 | * hep->urb_list now ... so we're done, unless hep wasn't yet |
| 2099 | * scheduled onto a live qh. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2100 | * |
| 2101 | * REVISIT best to keep hep->hcpriv valid until the endpoint gets |
| 2102 | * disabled, testing for empty qh->ring and avoiding qh setup costs |
| 2103 | * except for the first urb queued after a config change. |
| 2104 | */ |
David Brownell | 74bb350 | 2009-03-26 17:36:57 -0700 | [diff] [blame] | 2105 | if (qh || ret) |
| 2106 | return ret; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2107 | |
| 2108 | /* Allocate and initialize qh, minimizing the work done each time |
| 2109 | * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. |
| 2110 | * |
| 2111 | * REVISIT consider a dedicated qh kmem_cache, so it's harder |
| 2112 | * for bugs in other kernel code to break this driver... |
| 2113 | */ |
| 2114 | qh = kzalloc(sizeof *qh, mem_flags); |
| 2115 | if (!qh) { |
Ajay Kumar Gupta | 2492e67 | 2008-09-11 11:53:21 +0300 | [diff] [blame] | 2116 | spin_lock_irqsave(&musb->lock, flags); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2117 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
Ajay Kumar Gupta | 2492e67 | 2008-09-11 11:53:21 +0300 | [diff] [blame] | 2118 | spin_unlock_irqrestore(&musb->lock, flags); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2119 | return -ENOMEM; |
| 2120 | } |
| 2121 | |
| 2122 | qh->hep = hep; |
| 2123 | qh->dev = urb->dev; |
| 2124 | INIT_LIST_HEAD(&qh->ring); |
| 2125 | qh->is_ready = 1; |
| 2126 | |
Kuninori Morimoto | 29cc889 | 2011-08-23 03:12:03 -0700 | [diff] [blame] | 2127 | qh->maxpacket = usb_endpoint_maxp(epd); |
Ajay Kumar Gupta | a483d70 | 2009-04-03 16:16:17 -0700 | [diff] [blame] | 2128 | qh->type = usb_endpoint_type(epd); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2129 | |
Ajay Kumar Gupta | a483d70 | 2009-04-03 16:16:17 -0700 | [diff] [blame] | 2130 | /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier. |
| 2131 | * Some musb cores don't support high bandwidth ISO transfers; and |
| 2132 | * we don't (yet!) support high bandwidth interrupt transfers. |
| 2133 | */ |
| 2134 | qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03); |
| 2135 | if (qh->hb_mult > 1) { |
| 2136 | int ok = (qh->type == USB_ENDPOINT_XFER_ISOC); |
| 2137 | |
| 2138 | if (ok) |
| 2139 | ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx) |
| 2140 | || (usb_pipeout(urb->pipe) && musb->hb_iso_tx); |
| 2141 | if (!ok) { |
| 2142 | ret = -EMSGSIZE; |
| 2143 | goto done; |
| 2144 | } |
| 2145 | qh->maxpacket &= 0x7ff; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2146 | } |
| 2147 | |
Julia Lawall | 96bcd09 | 2009-01-24 17:57:24 -0800 | [diff] [blame] | 2148 | qh->epnum = usb_endpoint_num(epd); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2149 | |
| 2150 | /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ |
| 2151 | qh->addr_reg = (u8) usb_pipedevice(urb->pipe); |
| 2152 | |
| 2153 | /* precompute rxtype/txtype/type0 register */ |
| 2154 | type_reg = (qh->type << 4) | qh->epnum; |
| 2155 | switch (urb->dev->speed) { |
| 2156 | case USB_SPEED_LOW: |
| 2157 | type_reg |= 0xc0; |
| 2158 | break; |
| 2159 | case USB_SPEED_FULL: |
| 2160 | type_reg |= 0x80; |
| 2161 | break; |
| 2162 | default: |
| 2163 | type_reg |= 0x40; |
| 2164 | } |
| 2165 | qh->type_reg = type_reg; |
| 2166 | |
Sergei Shtylyov | 136733d | 2009-02-21 15:31:35 -0800 | [diff] [blame] | 2167 | /* Precompute RXINTERVAL/TXINTERVAL register */ |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2168 | switch (qh->type) { |
| 2169 | case USB_ENDPOINT_XFER_INT: |
Sergei Shtylyov | 136733d | 2009-02-21 15:31:35 -0800 | [diff] [blame] | 2170 | /* |
| 2171 | * Full/low speeds use the linear encoding, |
| 2172 | * high speed uses the logarithmic encoding. |
| 2173 | */ |
| 2174 | if (urb->dev->speed <= USB_SPEED_FULL) { |
| 2175 | interval = max_t(u8, epd->bInterval, 1); |
| 2176 | break; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2177 | } |
| 2178 | /* FALLTHROUGH */ |
| 2179 | case USB_ENDPOINT_XFER_ISOC: |
Sergei Shtylyov | 136733d | 2009-02-21 15:31:35 -0800 | [diff] [blame] | 2180 | /* ISO always uses logarithmic encoding */ |
| 2181 | interval = min_t(u8, epd->bInterval, 16); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2182 | break; |
| 2183 | default: |
| 2184 | /* REVISIT we actually want to use NAK limits, hinting to the |
| 2185 | * transfer scheduling logic to try some other qh, e.g. try |
| 2186 | * for 2 msec first: |
| 2187 | * |
| 2188 | * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; |
| 2189 | * |
| 2190 | * The downside of disabling this is that transfer scheduling |
| 2191 | * gets VERY unfair for nonperiodic transfers; a misbehaving |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 2192 | * peripheral could make that hurt. That's perfectly normal |
| 2193 | * for reads from network or serial adapters ... so we have |
| 2194 | * partial NAKlimit support for bulk RX. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2195 | * |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 2196 | * The upside of disabling it is simpler transfer scheduling. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2197 | */ |
| 2198 | interval = 0; |
| 2199 | } |
| 2200 | qh->intv_reg = interval; |
| 2201 | |
| 2202 | /* precompute addressing for external hub/tt ports */ |
| 2203 | if (musb->is_multipoint) { |
| 2204 | struct usb_device *parent = urb->dev->parent; |
| 2205 | |
| 2206 | if (parent != hcd->self.root_hub) { |
| 2207 | qh->h_addr_reg = (u8) parent->devnum; |
| 2208 | |
| 2209 | /* set up tt info if needed */ |
| 2210 | if (urb->dev->tt) { |
| 2211 | qh->h_port_reg = (u8) urb->dev->ttport; |
Ajay Kumar Gupta | ae5ad29 | 2008-09-11 11:53:20 +0300 | [diff] [blame] | 2212 | if (urb->dev->tt->hub) |
| 2213 | qh->h_addr_reg = |
| 2214 | (u8) urb->dev->tt->hub->devnum; |
| 2215 | if (urb->dev->tt->multi) |
| 2216 | qh->h_addr_reg |= 0x80; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2217 | } |
| 2218 | } |
| 2219 | } |
| 2220 | |
| 2221 | /* invariant: hep->hcpriv is null OR the qh that's already scheduled. |
| 2222 | * until we get real dma queues (with an entry for each urb/buffer), |
| 2223 | * we only have work to do in the former case. |
| 2224 | */ |
| 2225 | spin_lock_irqsave(&musb->lock, flags); |
yuzheng ma | 3067779 | 2012-08-15 16:11:40 +0800 | [diff] [blame] | 2226 | if (hep->hcpriv || !next_urb(qh)) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2227 | /* some concurrent activity submitted another urb to hep... |
| 2228 | * odd, rare, error prone, but legal. |
| 2229 | */ |
| 2230 | kfree(qh); |
Dan Carpenter | 714bc5e | 2010-03-25 13:14:27 +0200 | [diff] [blame] | 2231 | qh = NULL; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2232 | ret = 0; |
| 2233 | } else |
| 2234 | ret = musb_schedule(musb, qh, |
| 2235 | epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); |
| 2236 | |
| 2237 | if (ret == 0) { |
| 2238 | urb->hcpriv = qh; |
| 2239 | /* FIXME set urb->start_frame for iso/intr, it's tested in |
| 2240 | * musb_start_urb(), but otherwise only konicawc cares ... |
| 2241 | */ |
| 2242 | } |
| 2243 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2244 | |
| 2245 | done: |
| 2246 | if (ret != 0) { |
Ajay Kumar Gupta | 2492e67 | 2008-09-11 11:53:21 +0300 | [diff] [blame] | 2247 | spin_lock_irqsave(&musb->lock, flags); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2248 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
Ajay Kumar Gupta | 2492e67 | 2008-09-11 11:53:21 +0300 | [diff] [blame] | 2249 | spin_unlock_irqrestore(&musb->lock, flags); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2250 | kfree(qh); |
| 2251 | } |
| 2252 | return ret; |
| 2253 | } |
| 2254 | |
| 2255 | |
| 2256 | /* |
| 2257 | * abort a transfer that's at the head of a hardware queue. |
| 2258 | * called with controller locked, irqs blocked |
| 2259 | * that hardware queue advances to the next transfer, unless prevented |
| 2260 | */ |
Sergei Shtylyov | 81ec4e4 | 2009-03-27 12:57:50 -0700 | [diff] [blame] | 2261 | static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2262 | { |
| 2263 | struct musb_hw_ep *ep = qh->hw_ep; |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 2264 | struct musb *musb = ep->musb; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2265 | void __iomem *epio = ep->regs; |
| 2266 | unsigned hw_end = ep->epnum; |
| 2267 | void __iomem *regs = ep->musb->mregs; |
Sergei Shtylyov | 81ec4e4 | 2009-03-27 12:57:50 -0700 | [diff] [blame] | 2268 | int is_in = usb_pipein(urb->pipe); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2269 | int status = 0; |
Sergei Shtylyov | 81ec4e4 | 2009-03-27 12:57:50 -0700 | [diff] [blame] | 2270 | u16 csr; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2271 | |
| 2272 | musb_ep_select(regs, hw_end); |
| 2273 | |
| 2274 | if (is_dma_capable()) { |
| 2275 | struct dma_channel *dma; |
| 2276 | |
| 2277 | dma = is_in ? ep->rx_channel : ep->tx_channel; |
| 2278 | if (dma) { |
| 2279 | status = ep->musb->dma_controller->channel_abort(dma); |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 2280 | dev_dbg(musb->controller, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2281 | "abort %cX%d DMA for urb %p --> %d\n", |
| 2282 | is_in ? 'R' : 'T', ep->epnum, |
| 2283 | urb, status); |
| 2284 | urb->actual_length += dma->actual_len; |
| 2285 | } |
| 2286 | } |
| 2287 | |
| 2288 | /* turn off DMA requests, discard state, stop polling ... */ |
Ajay Kumar Gupta | 692933b | 2012-03-14 17:33:35 +0530 | [diff] [blame] | 2289 | if (ep->epnum && is_in) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2290 | /* giveback saves bulk toggle */ |
| 2291 | csr = musb_h_flush_rxfifo(ep, 0); |
| 2292 | |
| 2293 | /* REVISIT we still get an irq; should likely clear the |
| 2294 | * endpoint's irq status here to avoid bogus irqs. |
| 2295 | * clearing that status is platform-specific... |
| 2296 | */ |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 2297 | } else if (ep->epnum) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2298 | musb_h_tx_flush_fifo(ep); |
| 2299 | csr = musb_readw(epio, MUSB_TXCSR); |
| 2300 | csr &= ~(MUSB_TXCSR_AUTOSET |
| 2301 | | MUSB_TXCSR_DMAENAB |
| 2302 | | MUSB_TXCSR_H_RXSTALL |
| 2303 | | MUSB_TXCSR_H_NAKTIMEOUT |
| 2304 | | MUSB_TXCSR_H_ERROR |
| 2305 | | MUSB_TXCSR_TXPKTRDY); |
| 2306 | musb_writew(epio, MUSB_TXCSR, csr); |
| 2307 | /* REVISIT may need to clear FLUSHFIFO ... */ |
| 2308 | musb_writew(epio, MUSB_TXCSR, csr); |
| 2309 | /* flush cpu writebuffer */ |
| 2310 | csr = musb_readw(epio, MUSB_TXCSR); |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 2311 | } else { |
| 2312 | musb_h_ep0_flush_fifo(ep); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2313 | } |
| 2314 | if (status == 0) |
| 2315 | musb_advance_schedule(ep->musb, urb, ep, is_in); |
| 2316 | return status; |
| 2317 | } |
| 2318 | |
| 2319 | static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
| 2320 | { |
| 2321 | struct musb *musb = hcd_to_musb(hcd); |
| 2322 | struct musb_qh *qh; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2323 | unsigned long flags; |
Sergei Shtylyov | 22a0d6f | 2009-03-27 12:56:26 -0700 | [diff] [blame] | 2324 | int is_in = usb_pipein(urb->pipe); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2325 | int ret; |
| 2326 | |
Felipe Balbi | 5c8a86e | 2011-05-11 12:44:08 +0300 | [diff] [blame] | 2327 | dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2328 | usb_pipedevice(urb->pipe), |
| 2329 | usb_pipeendpoint(urb->pipe), |
Sergei Shtylyov | 22a0d6f | 2009-03-27 12:56:26 -0700 | [diff] [blame] | 2330 | is_in ? "in" : "out"); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2331 | |
| 2332 | spin_lock_irqsave(&musb->lock, flags); |
| 2333 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); |
| 2334 | if (ret) |
| 2335 | goto done; |
| 2336 | |
| 2337 | qh = urb->hcpriv; |
| 2338 | if (!qh) |
| 2339 | goto done; |
| 2340 | |
Sergei Shtylyov | 22a0d6f | 2009-03-27 12:56:26 -0700 | [diff] [blame] | 2341 | /* |
| 2342 | * Any URB not actively programmed into endpoint hardware can be |
Sergei Shtylyov | a2fd814 | 2009-02-21 15:30:45 -0800 | [diff] [blame] | 2343 | * immediately given back; that's any URB not at the head of an |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2344 | * endpoint queue, unless someday we get real DMA queues. And even |
Sergei Shtylyov | a2fd814 | 2009-02-21 15:30:45 -0800 | [diff] [blame] | 2345 | * if it's at the head, it might not be known to the hardware... |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2346 | * |
Sergei Shtylyov | 22a0d6f | 2009-03-27 12:56:26 -0700 | [diff] [blame] | 2347 | * Otherwise abort current transfer, pending DMA, etc.; urb->status |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2348 | * has already been updated. This is a synchronous abort; it'd be |
| 2349 | * OK to hold off until after some IRQ, though. |
Sergei Shtylyov | 22a0d6f | 2009-03-27 12:56:26 -0700 | [diff] [blame] | 2350 | * |
| 2351 | * NOTE: qh is invalid unless !list_empty(&hep->urb_list) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2352 | */ |
Sergei Shtylyov | 22a0d6f | 2009-03-27 12:56:26 -0700 | [diff] [blame] | 2353 | if (!qh->is_ready |
| 2354 | || urb->urb_list.prev != &qh->hep->urb_list |
| 2355 | || musb_ep_get_qh(qh->hw_ep, is_in) != qh) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2356 | int ready = qh->is_ready; |
| 2357 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2358 | qh->is_ready = 0; |
Sergei Shtylyov | c9cd06b | 2009-03-27 12:58:31 -0700 | [diff] [blame] | 2359 | musb_giveback(musb, urb, 0); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2360 | qh->is_ready = ready; |
Sergei Shtylyov | a2fd814 | 2009-02-21 15:30:45 -0800 | [diff] [blame] | 2361 | |
| 2362 | /* If nothing else (usually musb_giveback) is using it |
| 2363 | * and its URB list has emptied, recycle this qh. |
| 2364 | */ |
| 2365 | if (ready && list_empty(&qh->hep->urb_list)) { |
| 2366 | qh->hep->hcpriv = NULL; |
| 2367 | list_del(&qh->ring); |
| 2368 | kfree(qh); |
| 2369 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2370 | } else |
Sergei Shtylyov | 81ec4e4 | 2009-03-27 12:57:50 -0700 | [diff] [blame] | 2371 | ret = musb_cleanup_urb(urb, qh); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2372 | done: |
| 2373 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2374 | return ret; |
| 2375 | } |
| 2376 | |
| 2377 | /* disable an endpoint */ |
| 2378 | static void |
| 2379 | musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) |
| 2380 | { |
Sergei Shtylyov | 22a0d6f | 2009-03-27 12:56:26 -0700 | [diff] [blame] | 2381 | u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2382 | unsigned long flags; |
| 2383 | struct musb *musb = hcd_to_musb(hcd); |
Sergei Shtylyov | dc61d23 | 2009-02-21 15:31:01 -0800 | [diff] [blame] | 2384 | struct musb_qh *qh; |
| 2385 | struct urb *urb; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2386 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2387 | spin_lock_irqsave(&musb->lock, flags); |
| 2388 | |
Sergei Shtylyov | dc61d23 | 2009-02-21 15:31:01 -0800 | [diff] [blame] | 2389 | qh = hep->hcpriv; |
| 2390 | if (qh == NULL) |
| 2391 | goto exit; |
| 2392 | |
Sergei Shtylyov | 22a0d6f | 2009-03-27 12:56:26 -0700 | [diff] [blame] | 2393 | /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2394 | |
Sergei Shtylyov | 22a0d6f | 2009-03-27 12:56:26 -0700 | [diff] [blame] | 2395 | /* Kick the first URB off the hardware, if needed */ |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2396 | qh->is_ready = 0; |
Sergei Shtylyov | 22a0d6f | 2009-03-27 12:56:26 -0700 | [diff] [blame] | 2397 | if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2398 | urb = next_urb(qh); |
| 2399 | |
| 2400 | /* make software (then hardware) stop ASAP */ |
| 2401 | if (!urb->unlinked) |
| 2402 | urb->status = -ESHUTDOWN; |
| 2403 | |
| 2404 | /* cleanup */ |
Sergei Shtylyov | 81ec4e4 | 2009-03-27 12:57:50 -0700 | [diff] [blame] | 2405 | musb_cleanup_urb(urb, qh); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2406 | |
Sergei Shtylyov | dc61d23 | 2009-02-21 15:31:01 -0800 | [diff] [blame] | 2407 | /* Then nuke all the others ... and advance the |
| 2408 | * queue on hw_ep (e.g. bulk ring) when we're done. |
| 2409 | */ |
| 2410 | while (!list_empty(&hep->urb_list)) { |
| 2411 | urb = next_urb(qh); |
| 2412 | urb->status = -ESHUTDOWN; |
| 2413 | musb_advance_schedule(musb, urb, qh->hw_ep, is_in); |
| 2414 | } |
| 2415 | } else { |
| 2416 | /* Just empty the queue; the hardware is busy with |
| 2417 | * other transfers, and since !qh->is_ready nothing |
| 2418 | * will activate any of these as it advances. |
| 2419 | */ |
| 2420 | while (!list_empty(&hep->urb_list)) |
Sergei Shtylyov | c9cd06b | 2009-03-27 12:58:31 -0700 | [diff] [blame] | 2421 | musb_giveback(musb, next_urb(qh), -ESHUTDOWN); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2422 | |
Sergei Shtylyov | dc61d23 | 2009-02-21 15:31:01 -0800 | [diff] [blame] | 2423 | hep->hcpriv = NULL; |
| 2424 | list_del(&qh->ring); |
| 2425 | kfree(qh); |
| 2426 | } |
| 2427 | exit: |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2428 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2429 | } |
| 2430 | |
| 2431 | static int musb_h_get_frame_number(struct usb_hcd *hcd) |
| 2432 | { |
| 2433 | struct musb *musb = hcd_to_musb(hcd); |
| 2434 | |
| 2435 | return musb_readw(musb->mregs, MUSB_FRAME); |
| 2436 | } |
| 2437 | |
| 2438 | static int musb_h_start(struct usb_hcd *hcd) |
| 2439 | { |
| 2440 | struct musb *musb = hcd_to_musb(hcd); |
| 2441 | |
| 2442 | /* NOTE: musb_start() is called when the hub driver turns |
| 2443 | * on port power, or when (OTG) peripheral starts. |
| 2444 | */ |
| 2445 | hcd->state = HC_STATE_RUNNING; |
| 2446 | musb->port1_status = 0; |
| 2447 | return 0; |
| 2448 | } |
| 2449 | |
| 2450 | static void musb_h_stop(struct usb_hcd *hcd) |
| 2451 | { |
| 2452 | musb_stop(hcd_to_musb(hcd)); |
| 2453 | hcd->state = HC_STATE_HALT; |
| 2454 | } |
| 2455 | |
| 2456 | static int musb_bus_suspend(struct usb_hcd *hcd) |
| 2457 | { |
| 2458 | struct musb *musb = hcd_to_musb(hcd); |
David Brownell | 89368d3 | 2009-07-01 03:36:16 -0700 | [diff] [blame] | 2459 | u8 devctl; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2460 | |
Daniel Mack | 94f7213 | 2013-11-25 22:26:41 +0100 | [diff] [blame] | 2461 | musb_port_suspend(musb, true); |
| 2462 | |
David Brownell | 89368d3 | 2009-07-01 03:36:16 -0700 | [diff] [blame] | 2463 | if (!is_host_active(musb)) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2464 | return 0; |
| 2465 | |
Antoine Tenart | e47d925 | 2014-10-30 18:41:13 +0100 | [diff] [blame] | 2466 | switch (musb->xceiv->otg->state) { |
David Brownell | 89368d3 | 2009-07-01 03:36:16 -0700 | [diff] [blame] | 2467 | case OTG_STATE_A_SUSPEND: |
| 2468 | return 0; |
| 2469 | case OTG_STATE_A_WAIT_VRISE: |
| 2470 | /* ID could be grounded even if there's no device |
| 2471 | * on the other end of the cable. NOTE that the |
| 2472 | * A_WAIT_VRISE timers are messy with MUSB... |
| 2473 | */ |
| 2474 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
| 2475 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) |
Antoine Tenart | e47d925 | 2014-10-30 18:41:13 +0100 | [diff] [blame] | 2476 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; |
David Brownell | 89368d3 | 2009-07-01 03:36:16 -0700 | [diff] [blame] | 2477 | break; |
| 2478 | default: |
| 2479 | break; |
| 2480 | } |
| 2481 | |
| 2482 | if (musb->is_active) { |
| 2483 | WARNING("trying to suspend as %s while active\n", |
Antoine Tenart | e47d925 | 2014-10-30 18:41:13 +0100 | [diff] [blame] | 2484 | usb_otg_state_string(musb->xceiv->otg->state)); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2485 | return -EBUSY; |
| 2486 | } else |
| 2487 | return 0; |
| 2488 | } |
| 2489 | |
| 2490 | static int musb_bus_resume(struct usb_hcd *hcd) |
| 2491 | { |
Daniel Mack | 869c597 | 2013-11-26 13:31:14 +0100 | [diff] [blame] | 2492 | struct musb *musb = hcd_to_musb(hcd); |
| 2493 | |
| 2494 | if (musb->config && |
| 2495 | musb->config->host_port_deassert_reset_at_resume) |
| 2496 | musb_port_reset(musb, false); |
| 2497 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2498 | return 0; |
| 2499 | } |
| 2500 | |
Ruslan Bilovol | 8408fd1 | 2013-03-29 19:15:21 +0200 | [diff] [blame] | 2501 | #ifndef CONFIG_MUSB_PIO_ONLY |
| 2502 | |
| 2503 | #define MUSB_USB_DMA_ALIGN 4 |
| 2504 | |
| 2505 | struct musb_temp_buffer { |
| 2506 | void *kmalloc_ptr; |
| 2507 | void *old_xfer_buffer; |
| 2508 | u8 data[0]; |
| 2509 | }; |
| 2510 | |
| 2511 | static void musb_free_temp_buffer(struct urb *urb) |
| 2512 | { |
| 2513 | enum dma_data_direction dir; |
| 2514 | struct musb_temp_buffer *temp; |
| 2515 | |
| 2516 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) |
| 2517 | return; |
| 2518 | |
| 2519 | dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; |
| 2520 | |
| 2521 | temp = container_of(urb->transfer_buffer, struct musb_temp_buffer, |
| 2522 | data); |
| 2523 | |
| 2524 | if (dir == DMA_FROM_DEVICE) { |
| 2525 | memcpy(temp->old_xfer_buffer, temp->data, |
| 2526 | urb->transfer_buffer_length); |
| 2527 | } |
| 2528 | urb->transfer_buffer = temp->old_xfer_buffer; |
| 2529 | kfree(temp->kmalloc_ptr); |
| 2530 | |
| 2531 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; |
| 2532 | } |
| 2533 | |
| 2534 | static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) |
| 2535 | { |
| 2536 | enum dma_data_direction dir; |
| 2537 | struct musb_temp_buffer *temp; |
| 2538 | void *kmalloc_ptr; |
| 2539 | size_t kmalloc_size; |
| 2540 | |
| 2541 | if (urb->num_sgs || urb->sg || |
| 2542 | urb->transfer_buffer_length == 0 || |
| 2543 | !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1))) |
| 2544 | return 0; |
| 2545 | |
| 2546 | dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; |
| 2547 | |
| 2548 | /* Allocate a buffer with enough padding for alignment */ |
| 2549 | kmalloc_size = urb->transfer_buffer_length + |
| 2550 | sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1; |
| 2551 | |
| 2552 | kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); |
| 2553 | if (!kmalloc_ptr) |
| 2554 | return -ENOMEM; |
| 2555 | |
| 2556 | /* Position our struct temp_buffer such that data is aligned */ |
| 2557 | temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN); |
| 2558 | |
| 2559 | |
| 2560 | temp->kmalloc_ptr = kmalloc_ptr; |
| 2561 | temp->old_xfer_buffer = urb->transfer_buffer; |
| 2562 | if (dir == DMA_TO_DEVICE) |
| 2563 | memcpy(temp->data, urb->transfer_buffer, |
| 2564 | urb->transfer_buffer_length); |
| 2565 | urb->transfer_buffer = temp->data; |
| 2566 | |
| 2567 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; |
| 2568 | |
| 2569 | return 0; |
| 2570 | } |
| 2571 | |
| 2572 | static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, |
| 2573 | gfp_t mem_flags) |
| 2574 | { |
| 2575 | struct musb *musb = hcd_to_musb(hcd); |
| 2576 | int ret; |
| 2577 | |
| 2578 | /* |
| 2579 | * The DMA engine in RTL1.8 and above cannot handle |
| 2580 | * DMA addresses that are not aligned to a 4 byte boundary. |
| 2581 | * For such engine implemented (un)map_urb_for_dma hooks. |
| 2582 | * Do not use these hooks for RTL<1.8 |
| 2583 | */ |
| 2584 | if (musb->hwvers < MUSB_HWVERS_1800) |
| 2585 | return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); |
| 2586 | |
| 2587 | ret = musb_alloc_temp_buffer(urb, mem_flags); |
| 2588 | if (ret) |
| 2589 | return ret; |
| 2590 | |
| 2591 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); |
| 2592 | if (ret) |
| 2593 | musb_free_temp_buffer(urb); |
| 2594 | |
| 2595 | return ret; |
| 2596 | } |
| 2597 | |
| 2598 | static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) |
| 2599 | { |
| 2600 | struct musb *musb = hcd_to_musb(hcd); |
| 2601 | |
| 2602 | usb_hcd_unmap_urb_for_dma(hcd, urb); |
| 2603 | |
| 2604 | /* Do not use this hook for RTL<1.8 (see description above) */ |
| 2605 | if (musb->hwvers < MUSB_HWVERS_1800) |
| 2606 | return; |
| 2607 | |
| 2608 | musb_free_temp_buffer(urb); |
| 2609 | } |
| 2610 | #endif /* !CONFIG_MUSB_PIO_ONLY */ |
| 2611 | |
Daniel Mack | 74c2e93 | 2013-04-10 21:55:45 +0200 | [diff] [blame] | 2612 | static const struct hc_driver musb_hc_driver = { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2613 | .description = "musb-hcd", |
| 2614 | .product_desc = "MUSB HDRC host driver", |
Daniel Mack | 74c2e93 | 2013-04-10 21:55:45 +0200 | [diff] [blame] | 2615 | .hcd_priv_size = sizeof(struct musb *), |
George Cherian | 2035772 | 2014-03-05 14:01:43 +0530 | [diff] [blame] | 2616 | .flags = HCD_USB2 | HCD_MEMORY | HCD_BH, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2617 | |
| 2618 | /* not using irq handler or reset hooks from usbcore, since |
| 2619 | * those must be shared with peripheral code for OTG configs |
| 2620 | */ |
| 2621 | |
| 2622 | .start = musb_h_start, |
| 2623 | .stop = musb_h_stop, |
| 2624 | |
| 2625 | .get_frame_number = musb_h_get_frame_number, |
| 2626 | |
| 2627 | .urb_enqueue = musb_urb_enqueue, |
| 2628 | .urb_dequeue = musb_urb_dequeue, |
| 2629 | .endpoint_disable = musb_h_disable, |
| 2630 | |
Ruslan Bilovol | 8408fd1 | 2013-03-29 19:15:21 +0200 | [diff] [blame] | 2631 | #ifndef CONFIG_MUSB_PIO_ONLY |
| 2632 | .map_urb_for_dma = musb_map_urb_for_dma, |
| 2633 | .unmap_urb_for_dma = musb_unmap_urb_for_dma, |
| 2634 | #endif |
| 2635 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2636 | .hub_status_data = musb_hub_status_data, |
| 2637 | .hub_control = musb_hub_control, |
| 2638 | .bus_suspend = musb_bus_suspend, |
| 2639 | .bus_resume = musb_bus_resume, |
| 2640 | /* .start_port_reset = NULL, */ |
| 2641 | /* .hub_irq_enable = NULL, */ |
| 2642 | }; |
Daniel Mack | 0b3eba4 | 2013-04-10 21:55:42 +0200 | [diff] [blame] | 2643 | |
Daniel Mack | 74c2e93 | 2013-04-10 21:55:45 +0200 | [diff] [blame] | 2644 | int musb_host_alloc(struct musb *musb) |
| 2645 | { |
| 2646 | struct device *dev = musb->controller; |
| 2647 | |
| 2648 | /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ |
| 2649 | musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); |
| 2650 | if (!musb->hcd) |
| 2651 | return -EINVAL; |
| 2652 | |
| 2653 | *musb->hcd->hcd_priv = (unsigned long) musb; |
| 2654 | musb->hcd->self.uses_pio_for_control = 1; |
| 2655 | musb->hcd->uses_new_polling = 1; |
| 2656 | musb->hcd->has_tt = 1; |
| 2657 | |
| 2658 | return 0; |
| 2659 | } |
| 2660 | |
| 2661 | void musb_host_cleanup(struct musb *musb) |
| 2662 | { |
Sebastian Andrzej Siewior | 9047428 | 2013-08-20 18:35:44 +0200 | [diff] [blame] | 2663 | if (musb->port_mode == MUSB_PORT_MODE_GADGET) |
| 2664 | return; |
Daniel Mack | 74c2e93 | 2013-04-10 21:55:45 +0200 | [diff] [blame] | 2665 | usb_remove_hcd(musb->hcd); |
Daniel Mack | 74c2e93 | 2013-04-10 21:55:45 +0200 | [diff] [blame] | 2666 | } |
| 2667 | |
| 2668 | void musb_host_free(struct musb *musb) |
| 2669 | { |
| 2670 | usb_put_hcd(musb->hcd); |
| 2671 | } |
| 2672 | |
Daniel Mack | 2cc65fe | 2013-04-10 21:55:47 +0200 | [diff] [blame] | 2673 | int musb_host_setup(struct musb *musb, int power_budget) |
| 2674 | { |
| 2675 | int ret; |
| 2676 | struct usb_hcd *hcd = musb->hcd; |
| 2677 | |
| 2678 | MUSB_HST_MODE(musb); |
| 2679 | musb->xceiv->otg->default_a = 1; |
Antoine Tenart | e47d925 | 2014-10-30 18:41:13 +0100 | [diff] [blame] | 2680 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
Daniel Mack | 2cc65fe | 2013-04-10 21:55:47 +0200 | [diff] [blame] | 2681 | |
| 2682 | otg_set_host(musb->xceiv->otg, &hcd->self); |
| 2683 | hcd->self.otg_port = 1; |
| 2684 | musb->xceiv->otg->host = &hcd->self; |
| 2685 | hcd->power_budget = 2 * (power_budget ? : 250); |
| 2686 | |
| 2687 | ret = usb_add_hcd(hcd, 0, 0); |
| 2688 | if (ret < 0) |
| 2689 | return ret; |
| 2690 | |
Peter Chen | 3c9740a | 2013-11-05 10:46:02 +0800 | [diff] [blame] | 2691 | device_wakeup_enable(hcd->self.controller); |
Daniel Mack | 2cc65fe | 2013-04-10 21:55:47 +0200 | [diff] [blame] | 2692 | return 0; |
| 2693 | } |
| 2694 | |
Daniel Mack | 0b3eba4 | 2013-04-10 21:55:42 +0200 | [diff] [blame] | 2695 | void musb_host_resume_root_hub(struct musb *musb) |
| 2696 | { |
Daniel Mack | 74c2e93 | 2013-04-10 21:55:45 +0200 | [diff] [blame] | 2697 | usb_hcd_resume_root_hub(musb->hcd); |
Daniel Mack | 0b3eba4 | 2013-04-10 21:55:42 +0200 | [diff] [blame] | 2698 | } |
| 2699 | |
| 2700 | void musb_host_poke_root_hub(struct musb *musb) |
| 2701 | { |
| 2702 | MUSB_HST_MODE(musb); |
Daniel Mack | 74c2e93 | 2013-04-10 21:55:45 +0200 | [diff] [blame] | 2703 | if (musb->hcd->status_urb) |
| 2704 | usb_hcd_poll_rh_status(musb->hcd); |
Daniel Mack | 0b3eba4 | 2013-04-10 21:55:42 +0200 | [diff] [blame] | 2705 | else |
Daniel Mack | 74c2e93 | 2013-04-10 21:55:45 +0200 | [diff] [blame] | 2706 | usb_hcd_resume_root_hub(musb->hcd); |
Daniel Mack | 0b3eba4 | 2013-04-10 21:55:42 +0200 | [diff] [blame] | 2707 | } |