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Chris Leech0bbd5f42006-05-23 17:35:34 -07001/*
Shannon Nelson7bb67c12007-11-14 16:59:51 -08002 * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved.
Chris Leech0bbd5f42006-05-23 17:35:34 -07003 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef IOATDMA_H
22#define IOATDMA_H
23
24#include <linux/dmaengine.h>
25#include "ioatdma_hw.h"
26#include <linux/init.h>
27#include <linux/dmapool.h>
28#include <linux/cache.h>
David S. Miller57c651f2006-05-23 17:39:49 -070029#include <linux/pci_ids.h>
Chris Leech0bbd5f42006-05-23 17:35:34 -070030
Maciej Sosnowski09177e82008-07-22 10:07:33 -070031#define IOAT_DMA_VERSION "2.18"
Shannon Nelson5149fd02007-10-18 03:07:13 -070032
Shannon Nelson3e037452007-10-16 01:27:40 -070033enum ioat_interrupt {
34 none = 0,
35 msix_multi_vector = 1,
36 msix_single_vector = 2,
37 msi = 3,
38 intx = 4,
39};
40
Chris Leech0bbd5f42006-05-23 17:35:34 -070041#define IOAT_LOW_COMPLETION_MASK 0xffffffc0
Shannon Nelson7bb67c12007-11-14 16:59:51 -080042#define IOAT_DMA_DCA_ANY_CPU ~0
Maciej Sosnowski09177e82008-07-22 10:07:33 -070043#define IOAT_WATCHDOG_PERIOD (2 * HZ)
Shannon Nelson7bb67c12007-11-14 16:59:51 -080044
Chris Leech0bbd5f42006-05-23 17:35:34 -070045
Chris Leech0bbd5f42006-05-23 17:35:34 -070046/**
Shannon Nelson8ab89562007-10-16 01:27:39 -070047 * struct ioatdma_device - internal representation of a IOAT device
Chris Leech0bbd5f42006-05-23 17:35:34 -070048 * @pdev: PCI-Express device
49 * @reg_base: MMIO register space base address
50 * @dma_pool: for allocating DMA descriptors
51 * @common: embedded struct dma_device
Shannon Nelson8ab89562007-10-16 01:27:39 -070052 * @version: version of ioatdma device
Shannon Nelson7bb67c12007-11-14 16:59:51 -080053 * @irq_mode: which style irq to use
54 * @msix_entries: irq handlers
55 * @idx: per channel data
Chris Leech0bbd5f42006-05-23 17:35:34 -070056 */
57
Shannon Nelson8ab89562007-10-16 01:27:39 -070058struct ioatdma_device {
Chris Leech0bbd5f42006-05-23 17:35:34 -070059 struct pci_dev *pdev;
Al Viro47b16532006-10-10 22:45:47 +010060 void __iomem *reg_base;
Chris Leech0bbd5f42006-05-23 17:35:34 -070061 struct pci_pool *dma_pool;
62 struct pci_pool *completion_pool;
Chris Leech0bbd5f42006-05-23 17:35:34 -070063 struct dma_device common;
Shannon Nelson8ab89562007-10-16 01:27:39 -070064 u8 version;
Shannon Nelson3e037452007-10-16 01:27:40 -070065 enum ioat_interrupt irq_mode;
Maciej Sosnowski09177e82008-07-22 10:07:33 -070066 struct delayed_work work;
Shannon Nelson3e037452007-10-16 01:27:40 -070067 struct msix_entry msix_entries[4];
68 struct ioat_dma_chan *idx[4];
Chris Leech0bbd5f42006-05-23 17:35:34 -070069};
70
71/**
72 * struct ioat_dma_chan - internal representation of a DMA channel
Chris Leech0bbd5f42006-05-23 17:35:34 -070073 */
Chris Leech0bbd5f42006-05-23 17:35:34 -070074struct ioat_dma_chan {
75
Al Viro47b16532006-10-10 22:45:47 +010076 void __iomem *reg_base;
Chris Leech0bbd5f42006-05-23 17:35:34 -070077
78 dma_cookie_t completed_cookie;
79 unsigned long last_completion;
Maciej Sosnowski09177e82008-07-22 10:07:33 -070080 unsigned long last_completion_time;
Chris Leech0bbd5f42006-05-23 17:35:34 -070081
Shannon Nelson711924b2007-12-17 16:20:08 -080082 size_t xfercap; /* XFERCAP register value expanded out */
Chris Leech0bbd5f42006-05-23 17:35:34 -070083
84 spinlock_t cleanup_lock;
85 spinlock_t desc_lock;
86 struct list_head free_desc;
87 struct list_head used_desc;
Maciej Sosnowski09177e82008-07-22 10:07:33 -070088 unsigned long watchdog_completion;
89 int watchdog_tcp_cookie;
90 u32 watchdog_last_tcp_cookie;
91 struct delayed_work work;
Chris Leech0bbd5f42006-05-23 17:35:34 -070092
93 int pending;
Shannon Nelson7bb67c12007-11-14 16:59:51 -080094 int dmacount;
95 int desccount;
Chris Leech0bbd5f42006-05-23 17:35:34 -070096
Shannon Nelson8ab89562007-10-16 01:27:39 -070097 struct ioatdma_device *device;
Chris Leech0bbd5f42006-05-23 17:35:34 -070098 struct dma_chan common;
99
100 dma_addr_t completion_addr;
101 union {
102 u64 full; /* HW completion writeback */
103 struct {
104 u32 low;
105 u32 high;
106 };
107 } *completion_virt;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700108 unsigned long last_compl_desc_addr_hw;
Shannon Nelson3e037452007-10-16 01:27:40 -0700109 struct tasklet_struct cleanup_task;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700110};
111
112/* wrapper around hardware descriptor format + additional software fields */
113
114/**
115 * struct ioat_desc_sw - wrapper around hardware descriptor
116 * @hw: hardware DMA descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700117 * @node: this descriptor will either be on the free list,
118 * or attached to a transaction list (async_tx.tx_list)
119 * @tx_cnt: number of descriptors required to complete the transaction
120 * @async_tx: the generic software descriptor for all engines
Chris Leech0bbd5f42006-05-23 17:35:34 -0700121 */
Chris Leech0bbd5f42006-05-23 17:35:34 -0700122struct ioat_desc_sw {
123 struct ioat_dma_descriptor *hw;
124 struct list_head node;
Dan Williams7405f742007-01-02 11:10:43 -0700125 int tx_cnt;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700126 size_t len;
127 dma_addr_t src;
128 dma_addr_t dst;
Dan Williams7405f742007-01-02 11:10:43 -0700129 struct dma_async_tx_descriptor async_tx;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700130};
131
Shannon Nelson8ab89562007-10-16 01:27:39 -0700132#if defined(CONFIG_INTEL_IOATDMA) || defined(CONFIG_INTEL_IOATDMA_MODULE)
133struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
134 void __iomem *iobase);
135void ioat_dma_remove(struct ioatdma_device *device);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800136struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
137struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
Shannon Nelson8ab89562007-10-16 01:27:39 -0700138#else
139#define ioat_dma_probe(pdev, iobase) NULL
140#define ioat_dma_remove(device) do { } while (0)
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700141#define ioat_dca_init(pdev, iobase) NULL
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800142#define ioat2_dca_init(pdev, iobase) NULL
Shannon Nelson8ab89562007-10-16 01:27:39 -0700143#endif
144
Chris Leech0bbd5f42006-05-23 17:35:34 -0700145#endif /* IOATDMA_H */