Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock.c |
| 3 | * |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2004-2008 Nokia Corporation |
| 6 | * |
| 7 | * Contacts: |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 9 | * Paul Walmsley |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 10 | * |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, |
| 12 | * Gordon McNutt and RidgeRun, Inc. |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. |
| 17 | */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 18 | #undef DEBUG |
| 19 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 20 | #include <linux/module.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/device.h> |
| 23 | #include <linux/list.h> |
| 24 | #include <linux/errno.h> |
| 25 | #include <linux/delay.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 26 | #include <linux/clk.h> |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 27 | #include <linux/io.h> |
| 28 | #include <linux/cpufreq.h> |
Russell King | fbd3bdb | 2008-09-06 12:13:59 +0100 | [diff] [blame] | 29 | #include <linux/bitops.h> |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 30 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 31 | #include <mach/clock.h> |
| 32 | #include <mach/sram.h> |
Tony Lindgren | 7663148 | 2006-12-12 23:02:43 -0800 | [diff] [blame] | 33 | #include <asm/div64.h> |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 34 | #include <asm/clkdev.h> |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 35 | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 36 | #include "memory.h" |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 37 | #include "clock.h" |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 38 | #include "prm.h" |
| 39 | #include "prm-regbits-24xx.h" |
| 40 | #include "cm.h" |
| 41 | #include "cm-regbits-24xx.h" |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 42 | |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 43 | static const struct clkops clkops_oscck; |
| 44 | static const struct clkops clkops_fixed; |
| 45 | |
| 46 | #include "clock24xx.h" |
| 47 | |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 48 | struct omap_clk { |
| 49 | u32 cpu; |
| 50 | struct clk_lookup lk; |
| 51 | }; |
| 52 | |
| 53 | #define CLK(dev, con, ck, cp) \ |
| 54 | { \ |
| 55 | .cpu = cp, \ |
| 56 | .lk = { \ |
| 57 | .dev_id = dev, \ |
| 58 | .con_id = con, \ |
| 59 | .clk = ck, \ |
| 60 | }, \ |
| 61 | } |
| 62 | |
| 63 | #define CK_243X (1 << 0) |
| 64 | #define CK_242X (1 << 1) |
| 65 | |
| 66 | static struct omap_clk omap24xx_clks[] = { |
| 67 | /* external root sources */ |
| 68 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), |
| 69 | CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), |
| 70 | CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), |
| 71 | CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), |
| 72 | /* internal analog sources */ |
| 73 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), |
| 74 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), |
| 75 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), |
| 76 | /* internal prcm root sources */ |
| 77 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), |
| 78 | CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), |
| 79 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), |
| 80 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), |
| 81 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), |
| 82 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), |
| 83 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), |
| 84 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), |
| 85 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), |
| 86 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), |
| 87 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), |
| 88 | /* mpu domain clocks */ |
| 89 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), |
| 90 | /* dsp domain clocks */ |
| 91 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), |
| 92 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), |
| 93 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), |
| 94 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), |
| 95 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), |
| 96 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), |
| 97 | /* GFX domain clocks */ |
| 98 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), |
| 99 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), |
| 100 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), |
| 101 | /* Modem domain clocks */ |
| 102 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), |
| 103 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), |
| 104 | /* DSS domain clocks */ |
| 105 | CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X), |
| 106 | CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X), |
| 107 | CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X), |
| 108 | CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X), |
| 109 | /* L3 domain clocks */ |
| 110 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), |
| 111 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), |
| 112 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), |
| 113 | /* L4 domain clocks */ |
| 114 | CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), |
| 115 | /* virtual meta-group clock */ |
| 116 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), |
| 117 | /* general l4 interface ck, multi-parent functional clk */ |
| 118 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), |
| 119 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), |
| 120 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), |
| 121 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), |
| 122 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), |
| 123 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), |
| 124 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), |
| 125 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), |
| 126 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), |
| 127 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), |
| 128 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), |
| 129 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), |
| 130 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), |
| 131 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), |
| 132 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), |
| 133 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), |
| 134 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), |
| 135 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), |
| 136 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), |
| 137 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), |
| 138 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), |
| 139 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), |
| 140 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), |
| 141 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), |
Russell King | b820ce4 | 2009-01-23 10:26:46 +0000 | [diff] [blame] | 142 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), |
| 143 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), |
| 144 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), |
| 145 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), |
| 146 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), |
| 147 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), |
| 148 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), |
| 149 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), |
| 150 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), |
| 151 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), |
Russell King | 1b5715e | 2009-01-19 20:49:37 +0000 | [diff] [blame] | 152 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), |
| 153 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), |
| 154 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), |
| 155 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), |
| 156 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), |
| 157 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 158 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), |
| 159 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), |
| 160 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), |
| 161 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), |
| 162 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), |
| 163 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), |
| 164 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), |
| 165 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), |
Russell King | 39a80c7 | 2009-01-19 20:44:33 +0000 | [diff] [blame] | 166 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), |
| 167 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 168 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), |
| 169 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), |
| 170 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), |
| 171 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), |
Russell King | 6c5dbb4 | 2009-01-24 16:27:06 +0000 | [diff] [blame] | 172 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), |
| 173 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 174 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), |
| 175 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), |
| 176 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), |
| 177 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), |
| 178 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), |
| 179 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), |
| 180 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), |
Russell King | 5c9e02b | 2009-01-19 20:53:30 +0000 | [diff] [blame] | 181 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), |
| 182 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 183 | CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), |
| 184 | CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), |
| 185 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), |
| 186 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), |
Russell King | cc51c9d | 2009-01-22 10:12:04 +0000 | [diff] [blame] | 187 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), |
| 188 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), |
Russell King | 1d14de0 | 2009-01-19 21:02:29 +0000 | [diff] [blame] | 189 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), |
| 190 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), |
| 191 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), |
| 192 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), |
| 193 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), |
| 194 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 195 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), |
| 196 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), |
| 197 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), |
| 198 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), |
| 199 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), |
| 200 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), |
| 201 | CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), |
| 202 | CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), |
Russell King | eeec7c8 | 2009-01-19 20:58:56 +0000 | [diff] [blame] | 203 | CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 204 | CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), |
| 205 | CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), |
| 206 | CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), |
| 207 | CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), |
Russell King | 6f7607c | 2009-01-28 10:22:50 +0000 | [diff] [blame] | 208 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), |
| 209 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), |
| 210 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), |
| 211 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 212 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), |
| 213 | CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), |
| 214 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), |
| 215 | CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), |
| 216 | CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), |
| 217 | }; |
| 218 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 219 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ |
| 220 | #define EN_APLL_STOPPED 0 |
| 221 | #define EN_APLL_LOCKED 3 |
Juha Yrjola | ddc32a8 | 2006-09-25 12:41:50 +0300 | [diff] [blame] | 222 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 223 | /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ |
| 224 | #define APLLS_CLKIN_19_2MHZ 0 |
| 225 | #define APLLS_CLKIN_13MHZ 2 |
| 226 | #define APLLS_CLKIN_12MHZ 3 |
| 227 | |
| 228 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 229 | |
| 230 | static struct prcm_config *curr_prcm_set; |
Tony Lindgren | ae78dcf | 2006-09-25 12:41:20 +0300 | [diff] [blame] | 231 | static struct clk *vclk; |
| 232 | static struct clk *sclk; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 233 | |
| 234 | /*------------------------------------------------------------------------- |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 235 | * Omap24xx specific clock functions |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 236 | *-------------------------------------------------------------------------*/ |
| 237 | |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 238 | /* This actually returns the rate of core_ck, not dpll_ck. */ |
| 239 | static u32 omap2_get_dpll_rate_24xx(struct clk *tclk) |
| 240 | { |
| 241 | long long dpll_clk; |
| 242 | u8 amult; |
| 243 | |
| 244 | dpll_clk = omap2_get_dpll_rate(tclk); |
| 245 | |
| 246 | amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 247 | amult &= OMAP24XX_CORE_CLK_SRC_MASK; |
| 248 | dpll_clk *= amult; |
| 249 | |
| 250 | return dpll_clk; |
| 251 | } |
| 252 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 253 | static int omap2_enable_osc_ck(struct clk *clk) |
| 254 | { |
| 255 | u32 pcc; |
| 256 | |
| 257 | pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); |
| 258 | |
| 259 | __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, |
| 260 | OMAP24XX_PRCM_CLKSRC_CTRL); |
| 261 | |
| 262 | return 0; |
| 263 | } |
| 264 | |
| 265 | static void omap2_disable_osc_ck(struct clk *clk) |
| 266 | { |
| 267 | u32 pcc; |
| 268 | |
| 269 | pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); |
| 270 | |
| 271 | __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, |
| 272 | OMAP24XX_PRCM_CLKSRC_CTRL); |
| 273 | } |
| 274 | |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 275 | static const struct clkops clkops_oscck = { |
| 276 | .enable = &omap2_enable_osc_ck, |
| 277 | .disable = &omap2_disable_osc_ck, |
| 278 | }; |
| 279 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 280 | #ifdef OLD_CK |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 281 | /* Recalculate SYST_CLK */ |
| 282 | static void omap2_sys_clk_recalc(struct clk * clk) |
| 283 | { |
| 284 | u32 div = PRCM_CLKSRC_CTRL; |
| 285 | div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ |
| 286 | div >>= clk->rate_offset; |
| 287 | clk->rate = (clk->parent->rate / div); |
| 288 | propagate_rate(clk); |
| 289 | } |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 290 | #endif /* OLD_CK */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 291 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 292 | /* Enable an APLL if off */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 293 | static int omap2_clk_fixed_enable(struct clk *clk) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 294 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 295 | u32 cval, apll_mask; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 296 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 297 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 298 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 299 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 300 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 301 | if ((cval & apll_mask) == apll_mask) |
| 302 | return 0; /* apll already enabled */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 303 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 304 | cval &= ~apll_mask; |
| 305 | cval |= apll_mask; |
| 306 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 307 | |
| 308 | if (clk == &apll96_ck) |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 309 | cval = OMAP24XX_ST_96M_APLL; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 310 | else if (clk == &apll54_ck) |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 311 | cval = OMAP24XX_ST_54M_APLL; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 312 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 313 | omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, |
| 314 | clk->name); |
| 315 | |
| 316 | /* |
| 317 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() |
| 318 | * fails? |
| 319 | */ |
| 320 | return 0; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 321 | } |
| 322 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 323 | /* Stop APLL */ |
| 324 | static void omap2_clk_fixed_disable(struct clk *clk) |
| 325 | { |
| 326 | u32 cval; |
| 327 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 328 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
| 329 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); |
| 330 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 331 | } |
| 332 | |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 333 | static const struct clkops clkops_fixed = { |
| 334 | .enable = &omap2_clk_fixed_enable, |
| 335 | .disable = &omap2_clk_fixed_disable, |
| 336 | }; |
| 337 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 338 | /* |
| 339 | * Uses the current prcm set to tell if a rate is valid. |
| 340 | * You can go slower, but not faster within a given rate set. |
| 341 | */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 342 | long omap2_dpllcore_round_rate(unsigned long target_rate) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 343 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 344 | u32 high, low, core_clk_src; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 345 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 346 | core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 347 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; |
| 348 | |
| 349 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 350 | high = curr_prcm_set->dpll_speed * 2; |
| 351 | low = curr_prcm_set->dpll_speed; |
| 352 | } else { /* DPLL clockout x 2 */ |
| 353 | high = curr_prcm_set->dpll_speed; |
| 354 | low = curr_prcm_set->dpll_speed / 2; |
| 355 | } |
| 356 | |
| 357 | #ifdef DOWN_VARIABLE_DPLL |
| 358 | if (target_rate > high) |
| 359 | return high; |
| 360 | else |
| 361 | return target_rate; |
| 362 | #else |
| 363 | if (target_rate > low) |
| 364 | return high; |
| 365 | else |
| 366 | return low; |
| 367 | #endif |
| 368 | |
| 369 | } |
| 370 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 371 | static void omap2_dpllcore_recalc(struct clk *clk) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 372 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 373 | clk->rate = omap2_get_dpll_rate_24xx(clk); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 374 | } |
| 375 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 376 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 377 | { |
| 378 | u32 cur_rate, low, mult, div, valid_rate, done_rate; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 379 | u32 bypass = 0; |
| 380 | struct prcm_config tmpset; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 381 | const struct dpll_data *dd; |
| 382 | unsigned long flags; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 383 | int ret = -EINVAL; |
| 384 | |
| 385 | local_irq_save(flags); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 386 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); |
| 387 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 388 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 389 | |
| 390 | if ((rate == (cur_rate / 2)) && (mult == 2)) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 391 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 392 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 393 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 394 | } else if (rate != cur_rate) { |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 395 | valid_rate = omap2_dpllcore_round_rate(rate); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 396 | if (valid_rate != rate) |
| 397 | goto dpll_exit; |
| 398 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 399 | if (mult == 1) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 400 | low = curr_prcm_set->dpll_speed; |
| 401 | else |
| 402 | low = curr_prcm_set->dpll_speed / 2; |
| 403 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 404 | dd = clk->dpll_data; |
| 405 | if (!dd) |
| 406 | goto dpll_exit; |
| 407 | |
| 408 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); |
| 409 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | |
| 410 | dd->div1_mask); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 411 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 412 | tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 413 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 414 | if (rate > low) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 415 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 416 | mult = ((rate / 2) / 1000000); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 417 | done_rate = CORE_CLK_SRC_DPLL_X2; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 418 | } else { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 419 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 420 | mult = (rate / 1000000); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 421 | done_rate = CORE_CLK_SRC_DPLL; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 422 | } |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 423 | tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); |
| 424 | tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 425 | |
| 426 | /* Worst case */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 427 | tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 428 | |
| 429 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ |
| 430 | bypass = 1; |
| 431 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 432 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 433 | |
| 434 | /* Force dll lock mode */ |
| 435 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, |
| 436 | bypass); |
| 437 | |
| 438 | /* Errata: ret dll entry state */ |
| 439 | omap2_init_memory_params(omap2_dll_force_needed()); |
| 440 | omap2_reprogram_sdrc(done_rate, 0); |
| 441 | } |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 442 | omap2_dpllcore_recalc(&dpll_ck); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 443 | ret = 0; |
| 444 | |
| 445 | dpll_exit: |
| 446 | local_irq_restore(flags); |
| 447 | return(ret); |
| 448 | } |
| 449 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 450 | /** |
| 451 | * omap2_table_mpu_recalc - just return the MPU speed |
| 452 | * @clk: virt_prcm_set struct clk |
| 453 | * |
| 454 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. |
| 455 | */ |
| 456 | static void omap2_table_mpu_recalc(struct clk *clk) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 457 | { |
| 458 | clk->rate = curr_prcm_set->mpu_speed; |
| 459 | } |
| 460 | |
| 461 | /* |
| 462 | * Look for a rate equal or less than the target rate given a configuration set. |
| 463 | * |
| 464 | * What's not entirely clear is "which" field represents the key field. |
| 465 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and |
| 466 | * just uses the ARM rates. |
| 467 | */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 468 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 469 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 470 | struct prcm_config *ptr; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 471 | long highest_rate; |
| 472 | |
| 473 | if (clk != &virt_prcm_set) |
| 474 | return -EINVAL; |
| 475 | |
| 476 | highest_rate = -EINVAL; |
| 477 | |
| 478 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 479 | if (!(ptr->flags & cpu_mask)) |
| 480 | continue; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 481 | if (ptr->xtal_speed != sys_ck.rate) |
| 482 | continue; |
| 483 | |
| 484 | highest_rate = ptr->mpu_speed; |
| 485 | |
| 486 | /* Can check only after xtal frequency check */ |
| 487 | if (ptr->mpu_speed <= rate) |
| 488 | break; |
| 489 | } |
| 490 | return highest_rate; |
| 491 | } |
| 492 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 493 | /* Sets basic clocks based on the specified rate */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 494 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 495 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 496 | u32 cur_rate, done_rate, bypass = 0, tmp; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 497 | struct prcm_config *prcm; |
| 498 | unsigned long found_speed = 0; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 499 | unsigned long flags; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 500 | |
| 501 | if (clk != &virt_prcm_set) |
| 502 | return -EINVAL; |
| 503 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 504 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
| 505 | if (!(prcm->flags & cpu_mask)) |
| 506 | continue; |
| 507 | |
| 508 | if (prcm->xtal_speed != sys_ck.rate) |
| 509 | continue; |
| 510 | |
| 511 | if (prcm->mpu_speed <= rate) { |
| 512 | found_speed = prcm->mpu_speed; |
| 513 | break; |
| 514 | } |
| 515 | } |
| 516 | |
| 517 | if (!found_speed) { |
| 518 | printk(KERN_INFO "Could not set MPU rate to %luMHz\n", |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 519 | rate / 1000000); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 520 | return -EINVAL; |
| 521 | } |
| 522 | |
| 523 | curr_prcm_set = prcm; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 524 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 525 | |
| 526 | if (prcm->dpll_speed == cur_rate / 2) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 527 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 528 | } else if (prcm->dpll_speed == cur_rate * 2) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 529 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 530 | } else if (prcm->dpll_speed != cur_rate) { |
| 531 | local_irq_save(flags); |
| 532 | |
| 533 | if (prcm->dpll_speed == prcm->xtal_speed) |
| 534 | bypass = 1; |
| 535 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 536 | if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == |
| 537 | CORE_CLK_SRC_DPLL_X2) |
| 538 | done_rate = CORE_CLK_SRC_DPLL_X2; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 539 | else |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 540 | done_rate = CORE_CLK_SRC_DPLL; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 541 | |
| 542 | /* MPU divider */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 543 | cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 544 | |
| 545 | /* dsp + iva1 div(2420), iva2.1(2430) */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 546 | cm_write_mod_reg(prcm->cm_clksel_dsp, |
| 547 | OMAP24XX_DSP_MOD, CM_CLKSEL); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 548 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 549 | cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 550 | |
| 551 | /* Major subsystem dividers */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 552 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; |
| 553 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 554 | if (cpu_is_omap2430()) |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 555 | cm_write_mod_reg(prcm->cm_clksel_mdm, |
| 556 | OMAP2430_MDM_MOD, CM_CLKSEL); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 557 | |
| 558 | /* x2 to enter init_mem */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 559 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 560 | |
| 561 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, |
| 562 | bypass); |
| 563 | |
| 564 | omap2_init_memory_params(omap2_dll_force_needed()); |
| 565 | omap2_reprogram_sdrc(done_rate, 0); |
| 566 | |
| 567 | local_irq_restore(flags); |
| 568 | } |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 569 | omap2_dpllcore_recalc(&dpll_ck); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 570 | |
| 571 | return 0; |
| 572 | } |
| 573 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 574 | static struct clk_functions omap2_clk_functions = { |
| 575 | .clk_enable = omap2_clk_enable, |
| 576 | .clk_disable = omap2_clk_disable, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 577 | .clk_round_rate = omap2_clk_round_rate, |
| 578 | .clk_set_rate = omap2_clk_set_rate, |
| 579 | .clk_set_parent = omap2_clk_set_parent, |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 580 | .clk_disable_unused = omap2_clk_disable_unused, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 581 | }; |
| 582 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 583 | static u32 omap2_get_apll_clkin(void) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 584 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 585 | u32 aplls, sclk = 0; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 586 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 587 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); |
| 588 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; |
| 589 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 590 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 591 | if (aplls == APLLS_CLKIN_19_2MHZ) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 592 | sclk = 19200000; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 593 | else if (aplls == APLLS_CLKIN_13MHZ) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 594 | sclk = 13000000; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 595 | else if (aplls == APLLS_CLKIN_12MHZ) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 596 | sclk = 12000000; |
| 597 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 598 | return sclk; |
| 599 | } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 600 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 601 | static u32 omap2_get_sysclkdiv(void) |
| 602 | { |
| 603 | u32 div; |
| 604 | |
| 605 | div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); |
| 606 | div &= OMAP_SYSCLKDIV_MASK; |
| 607 | div >>= OMAP_SYSCLKDIV_SHIFT; |
| 608 | |
| 609 | return div; |
| 610 | } |
| 611 | |
| 612 | static void omap2_osc_clk_recalc(struct clk *clk) |
| 613 | { |
| 614 | clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 615 | } |
| 616 | |
| 617 | static void omap2_sys_clk_recalc(struct clk *clk) |
| 618 | { |
| 619 | clk->rate = clk->parent->rate / omap2_get_sysclkdiv(); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 620 | } |
| 621 | |
Tony Lindgren | ae78dcf | 2006-09-25 12:41:20 +0300 | [diff] [blame] | 622 | /* |
| 623 | * Set clocks for bypass mode for reboot to work. |
| 624 | */ |
| 625 | void omap2_clk_prepare_for_reboot(void) |
| 626 | { |
| 627 | u32 rate; |
| 628 | |
| 629 | if (vclk == NULL || sclk == NULL) |
| 630 | return; |
| 631 | |
| 632 | rate = clk_get_rate(sclk); |
| 633 | clk_set_rate(vclk, rate); |
| 634 | } |
| 635 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 636 | /* |
| 637 | * Switch the MPU rate if specified on cmdline. |
| 638 | * We cannot do this early until cmdline is parsed. |
| 639 | */ |
| 640 | static int __init omap2_clk_arch_init(void) |
| 641 | { |
| 642 | if (!mpurate) |
| 643 | return -EINVAL; |
| 644 | |
| 645 | if (omap2_select_table_rate(&virt_prcm_set, mpurate)) |
| 646 | printk(KERN_ERR "Could not find matching MPU rate\n"); |
| 647 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 648 | recalculate_root_clocks(); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 649 | |
| 650 | printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " |
| 651 | "%ld.%01ld/%ld/%ld MHz\n", |
| 652 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, |
| 653 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; |
| 654 | |
| 655 | return 0; |
| 656 | } |
| 657 | arch_initcall(omap2_clk_arch_init); |
| 658 | |
| 659 | int __init omap2_clk_init(void) |
| 660 | { |
| 661 | struct prcm_config *prcm; |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 662 | struct omap_clk *c; |
| 663 | u32 clkrate, cpu_mask; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 664 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 665 | if (cpu_is_omap242x()) |
| 666 | cpu_mask = RATE_IN_242X; |
| 667 | else if (cpu_is_omap2430()) |
| 668 | cpu_mask = RATE_IN_243X; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 669 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 670 | clk_init(&omap2_clk_functions); |
| 671 | |
| 672 | omap2_osc_clk_recalc(&osc_ck); |
Russell King | 9a5feda | 2008-11-13 13:44:15 +0000 | [diff] [blame] | 673 | propagate_rate(&osc_ck); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 674 | omap2_sys_clk_recalc(&sys_ck); |
Russell King | 9a5feda | 2008-11-13 13:44:15 +0000 | [diff] [blame] | 675 | propagate_rate(&sys_ck); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 676 | |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 677 | cpu_mask = 0; |
| 678 | if (cpu_is_omap2420()) |
| 679 | cpu_mask |= CK_242X; |
| 680 | if (cpu_is_omap2430()) |
| 681 | cpu_mask |= CK_243X; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 682 | |
Russell King | 8ad8ff6 | 2009-01-19 15:27:29 +0000 | [diff] [blame] | 683 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) |
| 684 | if (c->cpu & cpu_mask) { |
| 685 | clkdev_add(&c->lk); |
| 686 | clk_register(c->lk.clk); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 687 | } |
| 688 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 689 | /* Check the MPU rate set by bootloader */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 690 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 691 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 692 | if (!(prcm->flags & cpu_mask)) |
| 693 | continue; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 694 | if (prcm->xtal_speed != sys_ck.rate) |
| 695 | continue; |
| 696 | if (prcm->dpll_speed <= clkrate) |
| 697 | break; |
| 698 | } |
| 699 | curr_prcm_set = prcm; |
| 700 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 701 | recalculate_root_clocks(); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 702 | |
| 703 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " |
| 704 | "%ld.%01ld/%ld/%ld MHz\n", |
| 705 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, |
| 706 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; |
| 707 | |
| 708 | /* |
| 709 | * Only enable those clocks we will need, let the drivers |
| 710 | * enable other clocks as necessary |
| 711 | */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 712 | clk_enable_init_clocks(); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 713 | |
Tony Lindgren | ae78dcf | 2006-09-25 12:41:20 +0300 | [diff] [blame] | 714 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ |
| 715 | vclk = clk_get(NULL, "virt_prcm_set"); |
| 716 | sclk = clk_get(NULL, "sys_ck"); |
| 717 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 718 | return 0; |
| 719 | } |