| Vineet Gupta | a12ebe1 | 2015-03-09 14:30:19 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
| Vineet Gupta | 2e8cd93 | 2016-01-19 16:00:42 +0530 | [diff] [blame] | 10 | /include/ "skeleton_hs.dtsi" |
| Vineet Gupta | a12ebe1 | 2015-03-09 14:30:19 +0530 | [diff] [blame] | 11 | |
| 12 | / { |
| 13 | compatible = "snps,nsimosci_hs"; |
| 14 | clock-frequency = <20000000>; /* 20 MHZ */ |
| 15 | #address-cells = <1>; |
| 16 | #size-cells = <1>; |
| 17 | interrupt-parent = <&core_intc>; |
| 18 | |
| 19 | chosen { |
| 20 | /* this is for console on PGU */ |
| 21 | /* bootargs = "console=tty0 consoleblank=0"; */ |
| 22 | /* this is for console on serial */ |
| 23 | bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug"; |
| 24 | }; |
| 25 | |
| 26 | aliases { |
| 27 | serial0 = &uart0; |
| 28 | }; |
| 29 | |
| 30 | fpga { |
| 31 | compatible = "simple-bus"; |
| 32 | #address-cells = <1>; |
| 33 | #size-cells = <1>; |
| 34 | |
| 35 | /* child and parent address space 1:1 mapped */ |
| 36 | ranges; |
| 37 | |
| Vineet Gupta | b3d6aba | 2016-01-01 18:48:40 +0530 | [diff] [blame] | 38 | core_clk: core_clk { |
| 39 | #clock-cells = <0>; |
| 40 | compatible = "fixed-clock"; |
| 41 | clock-frequency = <20000000>; |
| 42 | }; |
| 43 | |
| Vineet Gupta | a12ebe1 | 2015-03-09 14:30:19 +0530 | [diff] [blame] | 44 | core_intc: core-interrupt-controller { |
| 45 | compatible = "snps,archs-intc"; |
| 46 | interrupt-controller; |
| 47 | #interrupt-cells = <1>; |
| 48 | }; |
| 49 | |
| 50 | uart0: serial@f0000000 { |
| 51 | compatible = "ns8250"; |
| 52 | reg = <0xf0000000 0x2000>; |
| 53 | interrupts = <24>; |
| 54 | clock-frequency = <3686400>; |
| 55 | baud = <115200>; |
| 56 | reg-shift = <2>; |
| 57 | reg-io-width = <4>; |
| 58 | no-loopback-test = <1>; |
| 59 | }; |
| 60 | |
| 61 | pgu0: pgu@f9000000 { |
| 62 | compatible = "snps,arcpgufb"; |
| 63 | reg = <0xf9000000 0x400>; |
| 64 | }; |
| 65 | |
| 66 | ps2: ps2@f9001000 { |
| 67 | compatible = "snps,arc_ps2"; |
| 68 | reg = <0xf9000400 0x14>; |
| 69 | interrupts = <27>; |
| 70 | interrupt-names = "arc_ps2_irq"; |
| 71 | }; |
| 72 | |
| 73 | eth0: ethernet@f0003000 { |
| Lada Trimasova | df420fd | 2016-03-14 17:11:57 +0300 | [diff] [blame] | 74 | compatible = "ezchip,nps-mgt-enet"; |
| Vineet Gupta | a12ebe1 | 2015-03-09 14:30:19 +0530 | [diff] [blame] | 75 | reg = <0xf0003000 0x44>; |
| Lada Trimasova | df420fd | 2016-03-14 17:11:57 +0300 | [diff] [blame] | 76 | interrupts = <25>; |
| Vineet Gupta | a12ebe1 | 2015-03-09 14:30:19 +0530 | [diff] [blame] | 77 | }; |
| 78 | |
| 79 | arcpct0: pct { |
| 80 | compatible = "snps,archs-pct"; |
| 81 | #interrupt-cells = <1>; |
| 82 | interrupts = <20>; |
| 83 | }; |
| 84 | }; |
| 85 | }; |