Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 1 | /* |
| 2 | * TI DaVinci GPIO Support |
| 3 | * |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 4 | * Copyright (c) 2006-2007 David Brownell |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
Russell King | 2f8163b | 2011-07-26 10:53:52 +0100 | [diff] [blame] | 12 | #include <linux/gpio.h> |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 13 | #include <linux/errno.h> |
| 14 | #include <linux/kernel.h> |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 15 | #include <linux/clk.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/io.h> |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 18 | #include <linux/irq.h> |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 19 | #include <linux/irqdomain.h> |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame] | 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_device.h> |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/platform_data/gpio-davinci.h> |
Grygorii Strashko | 0d978eb | 2013-11-26 21:40:09 +0200 | [diff] [blame] | 25 | #include <linux/irqchip/chained_irq.h> |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 26 | |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 27 | struct davinci_gpio_regs { |
| 28 | u32 dir; |
| 29 | u32 out_data; |
| 30 | u32 set_data; |
| 31 | u32 clr_data; |
| 32 | u32 in_data; |
| 33 | u32 set_rising; |
| 34 | u32 clr_rising; |
| 35 | u32 set_falling; |
| 36 | u32 clr_falling; |
| 37 | u32 intstat; |
| 38 | }; |
| 39 | |
Grygorii Strashko | 0c6feb0 | 2014-02-13 17:58:45 +0200 | [diff] [blame] | 40 | typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); |
| 41 | |
Philip Avinash | 131a10a | 2013-08-18 10:48:57 +0530 | [diff] [blame] | 42 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
| 43 | |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 44 | #define chip2controller(chip) \ |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 45 | container_of(chip, struct davinci_gpio_controller, chip) |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 46 | |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 47 | static void __iomem *gpio_base; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 48 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 49 | static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 50 | { |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 51 | void __iomem *ptr; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 52 | |
| 53 | if (gpio < 32 * 1) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 54 | ptr = gpio_base + 0x10; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 55 | else if (gpio < 32 * 2) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 56 | ptr = gpio_base + 0x38; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 57 | else if (gpio < 32 * 3) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 58 | ptr = gpio_base + 0x60; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 59 | else if (gpio < 32 * 4) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 60 | ptr = gpio_base + 0x88; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 61 | else if (gpio < 32 * 5) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 62 | ptr = gpio_base + 0xb0; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 63 | else |
| 64 | ptr = NULL; |
| 65 | return ptr; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 66 | } |
| 67 | |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 68 | static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) |
Kevin Hilman | 21ce873 | 2010-02-25 16:49:56 -0800 | [diff] [blame] | 69 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 70 | struct davinci_gpio_regs __iomem *g; |
Kevin Hilman | 21ce873 | 2010-02-25 16:49:56 -0800 | [diff] [blame] | 71 | |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 72 | g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); |
Kevin Hilman | 21ce873 | 2010-02-25 16:49:56 -0800 | [diff] [blame] | 73 | |
| 74 | return g; |
| 75 | } |
| 76 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 77 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 78 | |
| 79 | /*--------------------------------------------------------------------------*/ |
| 80 | |
Cyril Chemparathy | 5b3a05c | 2010-05-01 18:38:27 -0400 | [diff] [blame] | 81 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 82 | static inline int __davinci_direction(struct gpio_chip *chip, |
| 83 | unsigned offset, bool out, int value) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 84 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 85 | struct davinci_gpio_controller *d = chip2controller(chip); |
| 86 | struct davinci_gpio_regs __iomem *g = d->regs; |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 87 | unsigned long flags; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 88 | u32 temp; |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 89 | u32 mask = 1 << offset; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 90 | |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 91 | spin_lock_irqsave(&d->lock, flags); |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 92 | temp = readl_relaxed(&g->dir); |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 93 | if (out) { |
| 94 | temp &= ~mask; |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 95 | writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 96 | } else { |
| 97 | temp |= mask; |
| 98 | } |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 99 | writel_relaxed(temp, &g->dir); |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 100 | spin_unlock_irqrestore(&d->lock, flags); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 101 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 102 | return 0; |
| 103 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 104 | |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 105 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
| 106 | { |
| 107 | return __davinci_direction(chip, offset, false, 0); |
| 108 | } |
| 109 | |
| 110 | static int |
| 111 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) |
| 112 | { |
| 113 | return __davinci_direction(chip, offset, true, value); |
| 114 | } |
| 115 | |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 116 | /* |
| 117 | * Read the pin's value (works even if it's set up as output); |
| 118 | * returns zero/nonzero. |
| 119 | * |
| 120 | * Note that changes are synched to the GPIO clock, so reading values back |
| 121 | * right after you've set them may give old values. |
| 122 | */ |
| 123 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 124 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 125 | struct davinci_gpio_controller *d = chip2controller(chip); |
| 126 | struct davinci_gpio_regs __iomem *g = d->regs; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 127 | |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 128 | return (1 << offset) & readl_relaxed(&g->in_data); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 129 | } |
| 130 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 131 | /* |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 132 | * Assuming the pin is muxed as a gpio output, set its output value. |
| 133 | */ |
| 134 | static void |
| 135 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 136 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 137 | struct davinci_gpio_controller *d = chip2controller(chip); |
| 138 | struct davinci_gpio_regs __iomem *g = d->regs; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 139 | |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 140 | writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 141 | } |
| 142 | |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame] | 143 | static struct davinci_gpio_platform_data * |
| 144 | davinci_gpio_get_pdata(struct platform_device *pdev) |
| 145 | { |
| 146 | struct device_node *dn = pdev->dev.of_node; |
| 147 | struct davinci_gpio_platform_data *pdata; |
| 148 | int ret; |
| 149 | u32 val; |
| 150 | |
| 151 | if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) |
| 152 | return pdev->dev.platform_data; |
| 153 | |
| 154 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
| 155 | if (!pdata) |
| 156 | return NULL; |
| 157 | |
| 158 | ret = of_property_read_u32(dn, "ti,ngpio", &val); |
| 159 | if (ret) |
| 160 | goto of_err; |
| 161 | |
| 162 | pdata->ngpio = val; |
| 163 | |
| 164 | ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); |
| 165 | if (ret) |
| 166 | goto of_err; |
| 167 | |
| 168 | pdata->gpio_unbanked = val; |
| 169 | |
| 170 | return pdata; |
| 171 | |
| 172 | of_err: |
| 173 | dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); |
| 174 | return NULL; |
| 175 | } |
| 176 | |
Alexander Holler | 758afe4 | 2014-03-05 12:21:01 +0100 | [diff] [blame] | 177 | #ifdef CONFIG_OF_GPIO |
| 178 | static int davinci_gpio_of_xlate(struct gpio_chip *gc, |
| 179 | const struct of_phandle_args *gpiospec, |
| 180 | u32 *flags) |
| 181 | { |
| 182 | struct davinci_gpio_controller *chips = dev_get_drvdata(gc->dev); |
| 183 | struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->dev); |
| 184 | |
| 185 | if (gpiospec->args[0] > pdata->ngpio) |
| 186 | return -EINVAL; |
| 187 | |
| 188 | if (gc != &chips[gpiospec->args[0] / 32].chip) |
| 189 | return -EINVAL; |
| 190 | |
| 191 | if (flags) |
| 192 | *flags = gpiospec->args[1]; |
| 193 | |
| 194 | return gpiospec->args[0] % 32; |
| 195 | } |
| 196 | #endif |
| 197 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 198 | static int davinci_gpio_probe(struct platform_device *pdev) |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 199 | { |
| 200 | int i, base; |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 201 | unsigned ngpio; |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 202 | struct davinci_gpio_controller *chips; |
| 203 | struct davinci_gpio_platform_data *pdata; |
| 204 | struct davinci_gpio_regs __iomem *regs; |
| 205 | struct device *dev = &pdev->dev; |
| 206 | struct resource *res; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 207 | |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame] | 208 | pdata = davinci_gpio_get_pdata(pdev); |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 209 | if (!pdata) { |
| 210 | dev_err(dev, "No platform data found\n"); |
| 211 | return -EINVAL; |
| 212 | } |
Cyril Chemparathy | 686b634 | 2010-05-01 18:37:54 -0400 | [diff] [blame] | 213 | |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame] | 214 | dev->platform_data = pdata; |
| 215 | |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 216 | /* |
| 217 | * The gpio banks conceptually expose a segmented bitmap, |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 218 | * and "ngpio" is one more than the largest zero-based |
| 219 | * bit index that's valid. |
| 220 | */ |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 221 | ngpio = pdata->ngpio; |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 222 | if (ngpio == 0) { |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 223 | dev_err(dev, "How many GPIOs?\n"); |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 224 | return -EINVAL; |
| 225 | } |
| 226 | |
Grygorii Strashko | c21d500 | 2013-11-21 17:34:35 +0200 | [diff] [blame] | 227 | if (WARN_ON(ARCH_NR_GPIOS < ngpio)) |
| 228 | ngpio = ARCH_NR_GPIOS; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 229 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 230 | chips = devm_kzalloc(dev, |
| 231 | ngpio * sizeof(struct davinci_gpio_controller), |
| 232 | GFP_KERNEL); |
Jingoo Han | 9ea9363c | 2014-04-29 17:33:26 +0900 | [diff] [blame] | 233 | if (!chips) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 234 | return -ENOMEM; |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 235 | |
| 236 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 237 | gpio_base = devm_ioremap_resource(dev, res); |
| 238 | if (IS_ERR(gpio_base)) |
| 239 | return PTR_ERR(gpio_base); |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 240 | |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 241 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 242 | chips[i].chip.label = "DaVinci"; |
| 243 | |
| 244 | chips[i].chip.direction_input = davinci_direction_in; |
| 245 | chips[i].chip.get = davinci_gpio_get; |
| 246 | chips[i].chip.direction_output = davinci_direction_out; |
| 247 | chips[i].chip.set = davinci_gpio_set; |
| 248 | |
| 249 | chips[i].chip.base = base; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 250 | chips[i].chip.ngpio = ngpio - base; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 251 | if (chips[i].chip.ngpio > 32) |
| 252 | chips[i].chip.ngpio = 32; |
| 253 | |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame] | 254 | #ifdef CONFIG_OF_GPIO |
Alexander Holler | 758afe4 | 2014-03-05 12:21:01 +0100 | [diff] [blame] | 255 | chips[i].chip.of_gpio_n_cells = 2; |
| 256 | chips[i].chip.of_xlate = davinci_gpio_of_xlate; |
| 257 | chips[i].chip.dev = dev; |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame] | 258 | chips[i].chip.of_node = dev->of_node; |
| 259 | #endif |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 260 | spin_lock_init(&chips[i].lock); |
| 261 | |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 262 | regs = gpio2regs(base); |
| 263 | chips[i].regs = regs; |
| 264 | chips[i].set_data = ®s->set_data; |
| 265 | chips[i].clr_data = ®s->clr_data; |
| 266 | chips[i].in_data = ®s->in_data; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 267 | |
| 268 | gpiochip_add(&chips[i].chip); |
| 269 | } |
| 270 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 271 | platform_set_drvdata(pdev, chips); |
| 272 | davinci_gpio_irq_setup(pdev); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 273 | return 0; |
| 274 | } |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 275 | |
| 276 | /*--------------------------------------------------------------------------*/ |
| 277 | /* |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 278 | * We expect irqs will normally be set up as input pins, but they can also be |
| 279 | * used as output pins ... which is convenient for testing. |
| 280 | * |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 281 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 282 | * to their GPIOBNK0 irq, with a bit less overhead. |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 283 | * |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 284 | * All those INTC hookups (direct, plus several IRQ banks) can also |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 285 | * serve as EDMA event triggers. |
| 286 | */ |
| 287 | |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 288 | static void gpio_irq_disable(struct irq_data *d) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 289 | { |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 290 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 291 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 292 | |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 293 | writel_relaxed(mask, &g->clr_falling); |
| 294 | writel_relaxed(mask, &g->clr_rising); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 295 | } |
| 296 | |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 297 | static void gpio_irq_enable(struct irq_data *d) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 298 | { |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 299 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 300 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
Thomas Gleixner | 5093aec | 2011-03-24 12:47:04 +0100 | [diff] [blame] | 301 | unsigned status = irqd_get_trigger_type(d); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 302 | |
David Brownell | df4aab4 | 2009-05-04 13:14:27 -0700 | [diff] [blame] | 303 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
| 304 | if (!status) |
| 305 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
| 306 | |
| 307 | if (status & IRQ_TYPE_EDGE_FALLING) |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 308 | writel_relaxed(mask, &g->set_falling); |
David Brownell | df4aab4 | 2009-05-04 13:14:27 -0700 | [diff] [blame] | 309 | if (status & IRQ_TYPE_EDGE_RISING) |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 310 | writel_relaxed(mask, &g->set_rising); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 311 | } |
| 312 | |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 313 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 314 | { |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 315 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
| 316 | return -EINVAL; |
| 317 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | static struct irq_chip gpio_irqchip = { |
| 322 | .name = "GPIO", |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 323 | .irq_enable = gpio_irq_enable, |
| 324 | .irq_disable = gpio_irq_disable, |
| 325 | .irq_set_type = gpio_irq_type, |
Thomas Gleixner | 5093aec | 2011-03-24 12:47:04 +0100 | [diff] [blame] | 326 | .flags = IRQCHIP_SET_TYPE_MASKED, |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 327 | }; |
| 328 | |
| 329 | static void |
Thomas Gleixner | c3ca1e6 | 2015-07-12 23:47:32 +0200 | [diff] [blame] | 330 | gpio_irq_handler(unsigned __irq, struct irq_desc *desc) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 331 | { |
Thomas Gleixner | c3ca1e6 | 2015-07-12 23:47:32 +0200 | [diff] [blame] | 332 | unsigned int irq = irq_desc_get_irq(desc); |
Thomas Gleixner | 7416401 | 2011-06-06 11:51:43 +0200 | [diff] [blame] | 333 | struct davinci_gpio_regs __iomem *g; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 334 | u32 mask = 0xffff; |
Ido Yariv | f299bb9 | 2011-07-12 00:03:11 +0300 | [diff] [blame] | 335 | struct davinci_gpio_controller *d; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 336 | |
Ido Yariv | f299bb9 | 2011-07-12 00:03:11 +0300 | [diff] [blame] | 337 | d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); |
| 338 | g = (struct davinci_gpio_regs __iomem *)d->regs; |
Thomas Gleixner | 7416401 | 2011-06-06 11:51:43 +0200 | [diff] [blame] | 339 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 340 | /* we only care about one bank */ |
| 341 | if (irq & 1) |
| 342 | mask <<= 16; |
| 343 | |
| 344 | /* temporarily mask (level sensitive) parent IRQ */ |
Grygorii Strashko | 0d978eb | 2013-11-26 21:40:09 +0200 | [diff] [blame] | 345 | chained_irq_enter(irq_desc_get_chip(desc), desc); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 346 | while (1) { |
| 347 | u32 status; |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 348 | int bit; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 349 | |
| 350 | /* ack any irqs */ |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 351 | status = readl_relaxed(&g->intstat) & mask; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 352 | if (!status) |
| 353 | break; |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 354 | writel_relaxed(status, &g->intstat); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 355 | |
| 356 | /* now demux them to the right lowlevel handler */ |
Ido Yariv | f299bb9 | 2011-07-12 00:03:11 +0300 | [diff] [blame] | 357 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 358 | while (status) { |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 359 | bit = __ffs(status); |
| 360 | status &= ~BIT(bit); |
| 361 | generic_handle_irq( |
| 362 | irq_find_mapping(d->irq_domain, |
| 363 | d->chip.base + bit)); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 364 | } |
| 365 | } |
Grygorii Strashko | 0d978eb | 2013-11-26 21:40:09 +0200 | [diff] [blame] | 366 | chained_irq_exit(irq_desc_get_chip(desc), desc); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 367 | /* now it may re-trigger */ |
| 368 | } |
| 369 | |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 370 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
| 371 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 372 | struct davinci_gpio_controller *d = chip2controller(chip); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 373 | |
Grygorii Strashko | 6075a8b | 2013-12-18 12:07:51 +0200 | [diff] [blame] | 374 | if (d->irq_domain) |
| 375 | return irq_create_mapping(d->irq_domain, d->chip.base + offset); |
| 376 | else |
| 377 | return -ENXIO; |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 378 | } |
| 379 | |
| 380 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) |
| 381 | { |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 382 | struct davinci_gpio_controller *d = chip2controller(chip); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 383 | |
Philip Avinash | 131a10a | 2013-08-18 10:48:57 +0530 | [diff] [blame] | 384 | /* |
| 385 | * NOTE: we assume for now that only irqs in the first gpio_chip |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 386 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
| 387 | */ |
Lad, Prabhakar | 34af1ab | 2013-11-08 12:15:55 +0530 | [diff] [blame] | 388 | if (offset < d->gpio_unbanked) |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 389 | return d->gpio_irq + offset; |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 390 | else |
| 391 | return -ENODEV; |
| 392 | } |
| 393 | |
Sekhar Nori | ab2dde9 | 2012-03-11 18:16:11 +0530 | [diff] [blame] | 394 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 395 | { |
Sekhar Nori | ab2dde9 | 2012-03-11 18:16:11 +0530 | [diff] [blame] | 396 | struct davinci_gpio_controller *d; |
| 397 | struct davinci_gpio_regs __iomem *g; |
Sekhar Nori | ab2dde9 | 2012-03-11 18:16:11 +0530 | [diff] [blame] | 398 | u32 mask; |
| 399 | |
Jiang Liu | c16edb8 | 2015-06-01 16:05:19 +0800 | [diff] [blame] | 400 | d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); |
Sekhar Nori | ab2dde9 | 2012-03-11 18:16:11 +0530 | [diff] [blame] | 401 | g = (struct davinci_gpio_regs __iomem *)d->regs; |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 402 | mask = __gpio_mask(data->irq - d->gpio_irq); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 403 | |
| 404 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
| 405 | return -EINVAL; |
| 406 | |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 407 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 408 | ? &g->set_falling : &g->clr_falling); |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 409 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 410 | ? &g->set_rising : &g->clr_rising); |
| 411 | |
| 412 | return 0; |
| 413 | } |
| 414 | |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 415 | static int |
| 416 | davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
| 417 | irq_hw_number_t hw) |
| 418 | { |
| 419 | struct davinci_gpio_regs __iomem *g = gpio2regs(hw); |
| 420 | |
| 421 | irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, |
| 422 | "davinci_gpio"); |
| 423 | irq_set_irq_type(irq, IRQ_TYPE_NONE); |
| 424 | irq_set_chip_data(irq, (__force void *)g); |
| 425 | irq_set_handler_data(irq, (void *)__gpio_mask(hw)); |
| 426 | set_irq_flags(irq, IRQF_VALID); |
| 427 | |
| 428 | return 0; |
| 429 | } |
| 430 | |
| 431 | static const struct irq_domain_ops davinci_gpio_irq_ops = { |
| 432 | .map = davinci_gpio_irq_map, |
| 433 | .xlate = irq_domain_xlate_onetwocell, |
| 434 | }; |
| 435 | |
Grygorii Strashko | 0c6feb0 | 2014-02-13 17:58:45 +0200 | [diff] [blame] | 436 | static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) |
| 437 | { |
| 438 | static struct irq_chip_type gpio_unbanked; |
| 439 | |
| 440 | gpio_unbanked = *container_of(irq_get_chip(irq), |
| 441 | struct irq_chip_type, chip); |
| 442 | |
| 443 | return &gpio_unbanked.chip; |
| 444 | }; |
| 445 | |
| 446 | static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) |
| 447 | { |
| 448 | static struct irq_chip gpio_unbanked; |
| 449 | |
| 450 | gpio_unbanked = *irq_get_chip(irq); |
| 451 | return &gpio_unbanked; |
| 452 | }; |
| 453 | |
| 454 | static const struct of_device_id davinci_gpio_ids[]; |
| 455 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 456 | /* |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 457 | * NOTE: for suspend/resume, probably best to make a platform_device with |
| 458 | * suspend_late/resume_resume calls hooking into results of the set_wake() |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 459 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
| 460 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 461 | * (dm6446) can be set appropriately for GPIOV33 pins. |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 462 | */ |
| 463 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 464 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 465 | { |
Alexander Shiyan | 58c0f5a | 2014-02-15 17:12:05 +0400 | [diff] [blame] | 466 | unsigned gpio, bank; |
| 467 | int irq; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 468 | struct clk *clk; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 469 | u32 binten = 0; |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 470 | unsigned ngpio, bank_irq; |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 471 | struct device *dev = &pdev->dev; |
| 472 | struct resource *res; |
| 473 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); |
| 474 | struct davinci_gpio_platform_data *pdata = dev->platform_data; |
| 475 | struct davinci_gpio_regs __iomem *g; |
Grygorii Strashko | 6075a8b | 2013-12-18 12:07:51 +0200 | [diff] [blame] | 476 | struct irq_domain *irq_domain = NULL; |
Grygorii Strashko | 0c6feb0 | 2014-02-13 17:58:45 +0200 | [diff] [blame] | 477 | const struct of_device_id *match; |
| 478 | struct irq_chip *irq_chip; |
| 479 | gpio_get_irq_chip_cb_t gpio_get_irq_chip; |
| 480 | |
| 481 | /* |
| 482 | * Use davinci_gpio_get_irq_chip by default to handle non DT cases |
| 483 | */ |
| 484 | gpio_get_irq_chip = davinci_gpio_get_irq_chip; |
| 485 | match = of_match_device(of_match_ptr(davinci_gpio_ids), |
| 486 | dev); |
| 487 | if (match) |
| 488 | gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 489 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 490 | ngpio = pdata->ngpio; |
| 491 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 492 | if (!res) { |
| 493 | dev_err(dev, "Invalid IRQ resource\n"); |
| 494 | return -EBUSY; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 495 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 496 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 497 | bank_irq = res->start; |
| 498 | |
| 499 | if (!bank_irq) { |
| 500 | dev_err(dev, "Invalid IRQ resource\n"); |
| 501 | return -ENODEV; |
| 502 | } |
| 503 | |
| 504 | clk = devm_clk_get(dev, "gpio"); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 505 | if (IS_ERR(clk)) { |
| 506 | printk(KERN_ERR "Error %ld getting gpio clock?\n", |
| 507 | PTR_ERR(clk)); |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 508 | return PTR_ERR(clk); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 509 | } |
Murali Karicheri | ce6b658 | 2012-08-30 14:03:57 -0400 | [diff] [blame] | 510 | clk_prepare_enable(clk); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 511 | |
Grygorii Strashko | 6075a8b | 2013-12-18 12:07:51 +0200 | [diff] [blame] | 512 | if (!pdata->gpio_unbanked) { |
| 513 | irq = irq_alloc_descs(-1, 0, ngpio, 0); |
| 514 | if (irq < 0) { |
| 515 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); |
| 516 | return irq; |
| 517 | } |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 518 | |
Grygorii Strashko | 6075a8b | 2013-12-18 12:07:51 +0200 | [diff] [blame] | 519 | irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0, |
| 520 | &davinci_gpio_irq_ops, |
| 521 | chips); |
| 522 | if (!irq_domain) { |
| 523 | dev_err(dev, "Couldn't register an IRQ domain\n"); |
| 524 | return -ENODEV; |
| 525 | } |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 526 | } |
| 527 | |
Philip Avinash | 131a10a | 2013-08-18 10:48:57 +0530 | [diff] [blame] | 528 | /* |
| 529 | * Arrange gpio_to_irq() support, handling either direct IRQs or |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 530 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
| 531 | * IRQs, while the others use banked IRQs, would need some setup |
| 532 | * tweaks to recognize hardware which can do that. |
| 533 | */ |
| 534 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { |
| 535 | chips[bank].chip.to_irq = gpio_to_irq_banked; |
Grygorii Strashko | 6075a8b | 2013-12-18 12:07:51 +0200 | [diff] [blame] | 536 | chips[bank].irq_domain = irq_domain; |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 537 | } |
| 538 | |
| 539 | /* |
| 540 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO |
| 541 | * controller only handling trigger modes. We currently assume no |
| 542 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. |
| 543 | */ |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 544 | if (pdata->gpio_unbanked) { |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 545 | /* pass "bank 0" GPIO IRQs to AINTC */ |
| 546 | chips[0].chip.to_irq = gpio_to_irq_unbanked; |
Lad, Prabhakar | 34af1ab | 2013-11-08 12:15:55 +0530 | [diff] [blame] | 547 | chips[0].gpio_irq = bank_irq; |
| 548 | chips[0].gpio_unbanked = pdata->gpio_unbanked; |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 549 | binten = BIT(0); |
| 550 | |
| 551 | /* AINTC handles mask/unmask; GPIO handles triggering */ |
| 552 | irq = bank_irq; |
Grygorii Strashko | 0c6feb0 | 2014-02-13 17:58:45 +0200 | [diff] [blame] | 553 | irq_chip = gpio_get_irq_chip(irq); |
| 554 | irq_chip->name = "GPIO-AINTC"; |
| 555 | irq_chip->irq_set_type = gpio_irq_type_unbanked; |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 556 | |
| 557 | /* default trigger: both edges */ |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 558 | g = gpio2regs(0); |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 559 | writel_relaxed(~0, &g->set_falling); |
| 560 | writel_relaxed(~0, &g->set_rising); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 561 | |
| 562 | /* set the direct IRQs up to use that irqchip */ |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 563 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { |
Grygorii Strashko | 0c6feb0 | 2014-02-13 17:58:45 +0200 | [diff] [blame] | 564 | irq_set_chip(irq, irq_chip); |
Sekhar Nori | ab2dde9 | 2012-03-11 18:16:11 +0530 | [diff] [blame] | 565 | irq_set_handler_data(irq, &chips[gpio / 32]); |
Thomas Gleixner | 5093aec | 2011-03-24 12:47:04 +0100 | [diff] [blame] | 566 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 567 | } |
| 568 | |
| 569 | goto done; |
| 570 | } |
| 571 | |
| 572 | /* |
| 573 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we |
| 574 | * then chain through our own handler. |
| 575 | */ |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 576 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 577 | /* disabled by default, enabled only as needed */ |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 578 | g = gpio2regs(gpio); |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 579 | writel_relaxed(~0, &g->clr_falling); |
| 580 | writel_relaxed(~0, &g->clr_rising); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 581 | |
| 582 | /* set up all irqs in this bank */ |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 583 | irq_set_chained_handler(bank_irq, gpio_irq_handler); |
Ido Yariv | f299bb9 | 2011-07-12 00:03:11 +0300 | [diff] [blame] | 584 | |
| 585 | /* |
| 586 | * Each chip handles 32 gpios, and each irq bank consists of 16 |
| 587 | * gpio irqs. Pass the irq bank's corresponding controller to |
| 588 | * the chained irq handler. |
| 589 | */ |
| 590 | irq_set_handler_data(bank_irq, &chips[gpio / 32]); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 591 | |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 592 | binten |= BIT(bank); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 593 | } |
| 594 | |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 595 | done: |
Philip Avinash | 131a10a | 2013-08-18 10:48:57 +0530 | [diff] [blame] | 596 | /* |
| 597 | * BINTEN -- per-bank interrupt enable. genirq would also let these |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 598 | * bits be set/cleared dynamically. |
| 599 | */ |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 600 | writel_relaxed(binten, gpio_base + BINTEN); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 601 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 602 | return 0; |
| 603 | } |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 604 | |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame] | 605 | #if IS_ENABLED(CONFIG_OF) |
| 606 | static const struct of_device_id davinci_gpio_ids[] = { |
Grygorii Strashko | 0c6feb0 | 2014-02-13 17:58:45 +0200 | [diff] [blame] | 607 | { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, |
| 608 | { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame] | 609 | { /* sentinel */ }, |
| 610 | }; |
| 611 | MODULE_DEVICE_TABLE(of, davinci_gpio_ids); |
| 612 | #endif |
| 613 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 614 | static struct platform_driver davinci_gpio_driver = { |
| 615 | .probe = davinci_gpio_probe, |
| 616 | .driver = { |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame] | 617 | .name = "davinci_gpio", |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame] | 618 | .of_match_table = of_match_ptr(davinci_gpio_ids), |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 619 | }, |
| 620 | }; |
| 621 | |
| 622 | /** |
| 623 | * GPIO driver registration needs to be done before machine_init functions |
| 624 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. |
| 625 | */ |
| 626 | static int __init davinci_gpio_drv_reg(void) |
| 627 | { |
| 628 | return platform_driver_register(&davinci_gpio_driver); |
| 629 | } |
| 630 | postcore_initcall(davinci_gpio_drv_reg); |