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Changhwan Youn30d8bea2011-03-11 10:39:57 +09001/* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
Stephen Boydee98d272013-02-15 16:40:51 -080019#include <linux/cpu.h>
Changhwan Youn30d8bea2011-03-11 10:39:57 +090020#include <linux/platform_device.h>
21#include <linux/delay.h>
22#include <linux/percpu.h>
Kukjin Kim2edb36c2012-11-15 15:48:56 +090023#include <linux/of.h>
Thomas Abraham36ba5d52013-03-09 16:01:52 +090024#include <linux/of_irq.h>
25#include <linux/of_address.h>
Thomas Abraham9fbf0c82013-03-09 16:10:03 +090026#include <linux/clocksource.h>
Vincent Guittot93bfb762014-05-02 22:27:01 +090027#include <linux/sched_clock.h>
Changhwan Youn30d8bea2011-03-11 10:39:57 +090028
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090029#define EXYNOS4_MCTREG(x) (x)
30#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
31#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
32#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
33#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
34#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
35#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
36#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
37#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
38#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
39#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
40#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
41#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
42#define EXYNOS4_MCT_L_MASK (0xffffff00)
43
44#define MCT_L_TCNTB_OFFSET (0x00)
45#define MCT_L_ICNTB_OFFSET (0x08)
46#define MCT_L_TCON_OFFSET (0x20)
47#define MCT_L_INT_CSTAT_OFFSET (0x30)
48#define MCT_L_INT_ENB_OFFSET (0x34)
49#define MCT_L_WSTAT_OFFSET (0x40)
50#define MCT_G_TCON_START (1 << 8)
51#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
52#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
53#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
54#define MCT_L_TCON_INT_START (1 << 1)
55#define MCT_L_TCON_TIMER_START (1 << 0)
56
Changhwan Youn4d2e4d72012-03-09 15:09:21 -080057#define TICK_BASE_CNT 1
58
Changhwan Youn3a062282011-10-04 17:02:58 +090059enum {
60 MCT_INT_SPI,
61 MCT_INT_PPI
62};
63
Thomas Abrahamc371dc62013-03-09 16:01:50 +090064enum {
65 MCT_G0_IRQ,
66 MCT_G1_IRQ,
67 MCT_G2_IRQ,
68 MCT_G3_IRQ,
69 MCT_L0_IRQ,
70 MCT_L1_IRQ,
71 MCT_L2_IRQ,
72 MCT_L3_IRQ,
Chander Kashyap6c16ded2013-12-02 07:48:23 +090073 MCT_L4_IRQ,
74 MCT_L5_IRQ,
75 MCT_L6_IRQ,
76 MCT_L7_IRQ,
Thomas Abrahamc371dc62013-03-09 16:01:50 +090077 MCT_NR_IRQS,
78};
79
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090080static void __iomem *reg_base;
Changhwan Youn30d8bea2011-03-11 10:39:57 +090081static unsigned long clk_rate;
Changhwan Youn3a062282011-10-04 17:02:58 +090082static unsigned int mct_int_type;
Thomas Abrahamc371dc62013-03-09 16:01:50 +090083static int mct_irqs[MCT_NR_IRQS];
Changhwan Youn30d8bea2011-03-11 10:39:57 +090084
85struct mct_clock_event_device {
Stephen Boydee98d272013-02-15 16:40:51 -080086 struct clock_event_device evt;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090087 unsigned long base;
Changhwan Younc8987472011-10-04 17:09:26 +090088 char name[10];
Changhwan Youn30d8bea2011-03-11 10:39:57 +090089};
90
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090091static void exynos4_mct_write(unsigned int value, unsigned long offset)
Changhwan Youn30d8bea2011-03-11 10:39:57 +090092{
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090093 unsigned long stat_addr;
Changhwan Youn30d8bea2011-03-11 10:39:57 +090094 u32 mask;
95 u32 i;
96
Doug Andersonfdb06f62014-07-05 06:43:20 +090097 writel_relaxed(value, reg_base + offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +090098
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090099 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
Tobias Jakobi8c38d282014-10-22 03:37:08 +0200100 stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
101 switch (offset & ~EXYNOS4_MCT_L_MASK) {
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900102 case MCT_L_TCON_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900103 mask = 1 << 3; /* L_TCON write status */
104 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900105 case MCT_L_ICNTB_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900106 mask = 1 << 1; /* L_ICNTB write status */
107 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900108 case MCT_L_TCNTB_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900109 mask = 1 << 0; /* L_TCNTB write status */
110 break;
111 default:
112 return;
113 }
114 } else {
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900115 switch (offset) {
116 case EXYNOS4_MCT_G_TCON:
Changhwan Younc8987472011-10-04 17:09:26 +0900117 stat_addr = EXYNOS4_MCT_G_WSTAT;
118 mask = 1 << 16; /* G_TCON write status */
119 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900120 case EXYNOS4_MCT_G_COMP0_L:
Changhwan Younc8987472011-10-04 17:09:26 +0900121 stat_addr = EXYNOS4_MCT_G_WSTAT;
122 mask = 1 << 0; /* G_COMP0_L write status */
123 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900124 case EXYNOS4_MCT_G_COMP0_U:
Changhwan Younc8987472011-10-04 17:09:26 +0900125 stat_addr = EXYNOS4_MCT_G_WSTAT;
126 mask = 1 << 1; /* G_COMP0_U write status */
127 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900128 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
Changhwan Younc8987472011-10-04 17:09:26 +0900129 stat_addr = EXYNOS4_MCT_G_WSTAT;
130 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
131 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900132 case EXYNOS4_MCT_G_CNT_L:
Changhwan Younc8987472011-10-04 17:09:26 +0900133 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
134 mask = 1 << 0; /* G_CNT_L write status */
135 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900136 case EXYNOS4_MCT_G_CNT_U:
Changhwan Younc8987472011-10-04 17:09:26 +0900137 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
138 mask = 1 << 1; /* G_CNT_U write status */
139 break;
140 default:
141 return;
142 }
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900143 }
144
145 /* Wait maximum 1 ms until written values are applied */
146 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
Doug Andersonfdb06f62014-07-05 06:43:20 +0900147 if (readl_relaxed(reg_base + stat_addr) & mask) {
148 writel_relaxed(mask, reg_base + stat_addr);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900149 return;
150 }
151
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900152 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900153}
154
155/* Clocksource handling */
Chirantan Ekbote1d804152014-06-12 00:18:48 +0900156static void exynos4_mct_frc_start(void)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900157{
158 u32 reg;
159
Doug Andersonfdb06f62014-07-05 06:43:20 +0900160 reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900161 reg |= MCT_G_TCON_START;
162 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
163}
164
Doug Anderson3252a642014-07-05 06:43:26 +0900165/**
166 * exynos4_read_count_64 - Read all 64-bits of the global counter
167 *
168 * This will read all 64-bits of the global counter taking care to make sure
169 * that the upper and lower half match. Note that reading the MCT can be quite
170 * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
171 * only) version when possible.
172 *
173 * Returns the number of cycles in the global counter.
174 */
175static u64 exynos4_read_count_64(void)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900176{
177 unsigned int lo, hi;
Doug Andersonfdb06f62014-07-05 06:43:20 +0900178 u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900179
180 do {
181 hi = hi2;
Doug Andersonfdb06f62014-07-05 06:43:20 +0900182 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
183 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900184 } while (hi != hi2);
185
186 return ((cycle_t)hi << 32) | lo;
187}
188
Doug Anderson3252a642014-07-05 06:43:26 +0900189/**
190 * exynos4_read_count_32 - Read the lower 32-bits of the global counter
191 *
192 * This will read just the lower 32-bits of the global counter. This is marked
193 * as notrace so it can be used by the scheduler clock.
194 *
195 * Returns the number of cycles in the global counter (lower 32 bits).
196 */
197static u32 notrace exynos4_read_count_32(void)
198{
199 return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
200}
201
Doug Anderson89e6a132014-07-05 06:38:55 +0900202static cycle_t exynos4_frc_read(struct clocksource *cs)
203{
Doug Anderson3252a642014-07-05 06:43:26 +0900204 return exynos4_read_count_32();
Doug Anderson89e6a132014-07-05 06:38:55 +0900205}
206
Changhwan Younaa421c12011-09-02 14:10:52 +0900207static void exynos4_frc_resume(struct clocksource *cs)
208{
Chirantan Ekbote1d804152014-06-12 00:18:48 +0900209 exynos4_mct_frc_start();
Changhwan Younaa421c12011-09-02 14:10:52 +0900210}
211
Krzysztof Kozlowski6c10bf62015-04-30 13:42:52 +0900212static struct clocksource mct_frc = {
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900213 .name = "mct-frc",
214 .rating = 400,
215 .read = exynos4_frc_read,
Doug Anderson3252a642014-07-05 06:43:26 +0900216 .mask = CLOCKSOURCE_MASK(32),
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900217 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
Changhwan Younaa421c12011-09-02 14:10:52 +0900218 .resume = exynos4_frc_resume,
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900219};
220
Vincent Guittot93bfb762014-05-02 22:27:01 +0900221static u64 notrace exynos4_read_sched_clock(void)
222{
Doug Anderson3252a642014-07-05 06:43:26 +0900223 return exynos4_read_count_32();
Vincent Guittot93bfb762014-05-02 22:27:01 +0900224}
225
Amit Daniel Kachhap8bf13a42014-07-05 06:40:23 +0900226static struct delay_timer exynos4_delay_timer;
227
228static cycles_t exynos4_read_current_timer(void)
229{
Doug Anderson3252a642014-07-05 06:43:26 +0900230 BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32),
231 "cycles_t needs to move to 32-bit for ARM64 usage");
232 return exynos4_read_count_32();
Amit Daniel Kachhap8bf13a42014-07-05 06:40:23 +0900233}
234
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200235static int __init exynos4_clocksource_init(void)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900236{
Chirantan Ekbote1d804152014-06-12 00:18:48 +0900237 exynos4_mct_frc_start();
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900238
Amit Daniel Kachhap8bf13a42014-07-05 06:40:23 +0900239 exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
240 exynos4_delay_timer.freq = clk_rate;
241 register_current_timer_delay(&exynos4_delay_timer);
242
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900243 if (clocksource_register_hz(&mct_frc, clk_rate))
244 panic("%s: can't register clocksource\n", mct_frc.name);
Vincent Guittot93bfb762014-05-02 22:27:01 +0900245
Doug Anderson3252a642014-07-05 06:43:26 +0900246 sched_clock_register(exynos4_read_sched_clock, 32, clk_rate);
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200247
248 return 0;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900249}
250
251static void exynos4_mct_comp0_stop(void)
252{
253 unsigned int tcon;
254
Doug Andersonfdb06f62014-07-05 06:43:20 +0900255 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900256 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
257
258 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
259 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
260}
261
Viresh Kumar79e436d2015-06-18 16:24:20 +0530262static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900263{
264 unsigned int tcon;
265 cycle_t comp_cycle;
266
Doug Andersonfdb06f62014-07-05 06:43:20 +0900267 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900268
Viresh Kumar79e436d2015-06-18 16:24:20 +0530269 if (periodic) {
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900270 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
271 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
272 }
273
Doug Anderson3252a642014-07-05 06:43:26 +0900274 comp_cycle = exynos4_read_count_64() + cycles;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900275 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
276 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
277
278 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
279
280 tcon |= MCT_G_TCON_COMP0_ENABLE;
281 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
282}
283
284static int exynos4_comp_set_next_event(unsigned long cycles,
285 struct clock_event_device *evt)
286{
Viresh Kumar79e436d2015-06-18 16:24:20 +0530287 exynos4_mct_comp0_start(false, cycles);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900288
289 return 0;
290}
291
Viresh Kumar79e436d2015-06-18 16:24:20 +0530292static int mct_set_state_shutdown(struct clock_event_device *evt)
293{
294 exynos4_mct_comp0_stop();
295 return 0;
296}
297
298static int mct_set_state_periodic(struct clock_event_device *evt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900299{
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800300 unsigned long cycles_per_jiffy;
Viresh Kumar79e436d2015-06-18 16:24:20 +0530301
302 cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
303 >> evt->shift);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900304 exynos4_mct_comp0_stop();
Viresh Kumar79e436d2015-06-18 16:24:20 +0530305 exynos4_mct_comp0_start(true, cycles_per_jiffy);
306 return 0;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900307}
308
309static struct clock_event_device mct_comp_device = {
Viresh Kumar79e436d2015-06-18 16:24:20 +0530310 .name = "mct-comp",
311 .features = CLOCK_EVT_FEAT_PERIODIC |
312 CLOCK_EVT_FEAT_ONESHOT,
313 .rating = 250,
314 .set_next_event = exynos4_comp_set_next_event,
315 .set_state_periodic = mct_set_state_periodic,
316 .set_state_shutdown = mct_set_state_shutdown,
317 .set_state_oneshot = mct_set_state_shutdown,
Viresh Kumar07f101d2015-12-23 16:59:14 +0530318 .set_state_oneshot_stopped = mct_set_state_shutdown,
Viresh Kumar79e436d2015-06-18 16:24:20 +0530319 .tick_resume = mct_set_state_shutdown,
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900320};
321
322static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
323{
324 struct clock_event_device *evt = dev_id;
325
326 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
327
328 evt->event_handler(evt);
329
330 return IRQ_HANDLED;
331}
332
333static struct irqaction mct_comp_event_irq = {
334 .name = "mct_comp_irq",
335 .flags = IRQF_TIMER | IRQF_IRQPOLL,
336 .handler = exynos4_mct_comp_isr,
337 .dev_id = &mct_comp_device,
338};
339
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200340static int exynos4_clockevent_init(void)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900341{
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900342 mct_comp_device.cpumask = cpumask_of(0);
Shawn Guo838a2ae2013-01-12 11:50:05 +0000343 clockevents_config_and_register(&mct_comp_device, clk_rate,
344 0xf, 0xffffffff);
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900345 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200346
347 return 0;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900348}
349
Kukjin Kim991a6c72011-12-08 10:04:49 +0900350static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
351
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900352/* Clock event handling */
353static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
354{
355 unsigned long tmp;
356 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900357 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900358
Doug Andersonfdb06f62014-07-05 06:43:20 +0900359 tmp = readl_relaxed(reg_base + offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900360 if (tmp & mask) {
361 tmp &= ~mask;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900362 exynos4_mct_write(tmp, offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900363 }
364}
365
366static void exynos4_mct_tick_start(unsigned long cycles,
367 struct mct_clock_event_device *mevt)
368{
369 unsigned long tmp;
370
371 exynos4_mct_tick_stop(mevt);
372
373 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
374
375 /* update interrupt count buffer */
376 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
377
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300378 /* enable MCT tick interrupt */
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900379 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
380
Doug Andersonfdb06f62014-07-05 06:43:20 +0900381 tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900382 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
383 MCT_L_TCON_INTERVAL_MODE;
384 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
385}
386
387static int exynos4_tick_set_next_event(unsigned long cycles,
388 struct clock_event_device *evt)
389{
Alexey Klimov31f79872015-09-04 02:49:58 +0300390 struct mct_clock_event_device *mevt;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900391
Alexey Klimov31f79872015-09-04 02:49:58 +0300392 mevt = container_of(evt, struct mct_clock_event_device, evt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900393 exynos4_mct_tick_start(cycles, mevt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900394 return 0;
395}
396
Viresh Kumar79e436d2015-06-18 16:24:20 +0530397static int set_state_shutdown(struct clock_event_device *evt)
398{
Alexey Klimov31f79872015-09-04 02:49:58 +0300399 struct mct_clock_event_device *mevt;
400
401 mevt = container_of(evt, struct mct_clock_event_device, evt);
402 exynos4_mct_tick_stop(mevt);
Viresh Kumar79e436d2015-06-18 16:24:20 +0530403 return 0;
404}
405
406static int set_state_periodic(struct clock_event_device *evt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900407{
Alexey Klimov31f79872015-09-04 02:49:58 +0300408 struct mct_clock_event_device *mevt;
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800409 unsigned long cycles_per_jiffy;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900410
Alexey Klimov31f79872015-09-04 02:49:58 +0300411 mevt = container_of(evt, struct mct_clock_event_device, evt);
Viresh Kumar79e436d2015-06-18 16:24:20 +0530412 cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
413 >> evt->shift);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900414 exynos4_mct_tick_stop(mevt);
Viresh Kumar79e436d2015-06-18 16:24:20 +0530415 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
416 return 0;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900417}
418
Krzysztof Kozlowski37285672015-04-30 13:42:51 +0900419static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900420{
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900421 /*
422 * This is for supporting oneshot mode.
423 * Mct would generate interrupt periodically
424 * without explicit stopping.
425 */
Viresh Kumar79e436d2015-06-18 16:24:20 +0530426 if (!clockevent_state_periodic(&mevt->evt))
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900427 exynos4_mct_tick_stop(mevt);
428
429 /* Clear the MCT tick interrupt */
Krzysztof Kozlowski37285672015-04-30 13:42:51 +0900430 if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)
Changhwan Youn3a062282011-10-04 17:02:58 +0900431 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
Changhwan Youn3a062282011-10-04 17:02:58 +0900432}
433
434static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
435{
436 struct mct_clock_event_device *mevt = dev_id;
Stephen Boydee98d272013-02-15 16:40:51 -0800437 struct clock_event_device *evt = &mevt->evt;
Changhwan Youn3a062282011-10-04 17:02:58 +0900438
439 exynos4_mct_tick_clear(mevt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900440
441 evt->event_handler(evt);
442
443 return IRQ_HANDLED;
444}
445
Alexey Klimov479a9322015-06-21 23:41:39 +0300446static int exynos4_local_timer_setup(struct mct_clock_event_device *mevt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900447{
Alexey Klimov479a9322015-06-21 23:41:39 +0300448 struct clock_event_device *evt = &mevt->evt;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900449 unsigned int cpu = smp_processor_id();
450
Marc Zyngiere700e412011-11-03 11:13:12 +0900451 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
Dan Carpenter09e15172014-03-01 16:57:14 +0300452 snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900453
Marc Zyngiere700e412011-11-03 11:13:12 +0900454 evt->name = mevt->name;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900455 evt->cpumask = cpumask_of(cpu);
456 evt->set_next_event = exynos4_tick_set_next_event;
Viresh Kumar79e436d2015-06-18 16:24:20 +0530457 evt->set_state_periodic = set_state_periodic;
458 evt->set_state_shutdown = set_state_shutdown;
459 evt->set_state_oneshot = set_state_shutdown;
Viresh Kumar07f101d2015-12-23 16:59:14 +0530460 evt->set_state_oneshot_stopped = set_state_shutdown;
Viresh Kumar79e436d2015-06-18 16:24:20 +0530461 evt->tick_resume = set_state_shutdown;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900462 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
463 evt->rating = 450;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900464
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800465 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900466
Changhwan Youn3a062282011-10-04 17:02:58 +0900467 if (mct_int_type == MCT_INT_SPI) {
Damian Eppel56a94f12015-06-26 15:23:04 +0200468
469 if (evt->irq == -1)
Chander Kashyap7114cd72013-06-19 00:29:35 +0900470 return -EIO;
Damian Eppel56a94f12015-06-26 15:23:04 +0200471
472 irq_force_affinity(evt->irq, cpumask_of(cpu));
473 enable_irq(evt->irq);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900474 } else {
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900475 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900476 }
Krzysztof Kozlowski8db6e512014-04-16 14:36:45 +0000477 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
478 0xf, 0x7fffffff);
Kukjin Kim4d487d72011-08-24 16:07:39 +0900479
480 return 0;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900481}
482
Alexey Klimov479a9322015-06-21 23:41:39 +0300483static void exynos4_local_timer_stop(struct mct_clock_event_device *mevt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900484{
Alexey Klimov479a9322015-06-21 23:41:39 +0300485 struct clock_event_device *evt = &mevt->evt;
486
Viresh Kumar79e436d2015-06-18 16:24:20 +0530487 evt->set_state_shutdown(evt);
Damian Eppel56a94f12015-06-26 15:23:04 +0200488 if (mct_int_type == MCT_INT_SPI) {
489 if (evt->irq != -1)
490 disable_irq_nosync(evt->irq);
491 } else {
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900492 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
Damian Eppel56a94f12015-06-26 15:23:04 +0200493 }
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900494}
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000495
Olof Johansson47dcd352013-07-23 14:51:34 -0700496static int exynos4_mct_cpu_notify(struct notifier_block *self,
Stephen Boydee98d272013-02-15 16:40:51 -0800497 unsigned long action, void *hcpu)
498{
499 struct mct_clock_event_device *mevt;
500
501 /*
502 * Grab cpu pointer in each case to avoid spurious
503 * preemptible warnings
504 */
505 switch (action & ~CPU_TASKS_FROZEN) {
506 case CPU_STARTING:
507 mevt = this_cpu_ptr(&percpu_mct_tick);
Alexey Klimov479a9322015-06-21 23:41:39 +0300508 exynos4_local_timer_setup(mevt);
Stephen Boydee98d272013-02-15 16:40:51 -0800509 break;
510 case CPU_DYING:
511 mevt = this_cpu_ptr(&percpu_mct_tick);
Alexey Klimov479a9322015-06-21 23:41:39 +0300512 exynos4_local_timer_stop(mevt);
Stephen Boydee98d272013-02-15 16:40:51 -0800513 break;
514 }
515
516 return NOTIFY_OK;
517}
518
Olof Johansson47dcd352013-07-23 14:51:34 -0700519static struct notifier_block exynos4_mct_cpu_nb = {
Stephen Boydee98d272013-02-15 16:40:51 -0800520 .notifier_call = exynos4_mct_cpu_notify,
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000521};
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900522
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200523static int __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900524{
Damian Eppel56a94f12015-06-26 15:23:04 +0200525 int err, cpu;
Stephen Boydee98d272013-02-15 16:40:51 -0800526 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
Thomas Abrahamca9048e2013-03-09 17:10:37 +0900527 struct clk *mct_clk, *tick_clk;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900528
Thomas Abraham415ac2e2013-03-09 17:10:31 +0900529 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
530 clk_get(NULL, "fin_pll");
531 if (IS_ERR(tick_clk))
532 panic("%s: unable to determine tick clock rate\n", __func__);
533 clk_rate = clk_get_rate(tick_clk);
Marc Zyngiere700e412011-11-03 11:13:12 +0900534
Thomas Abrahamca9048e2013-03-09 17:10:37 +0900535 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
536 if (IS_ERR(mct_clk))
537 panic("%s: unable to retrieve mct clock instance\n", __func__);
538 clk_prepare_enable(mct_clk);
Marc Zyngiere700e412011-11-03 11:13:12 +0900539
Arnd Bergmann228e3022013-04-09 22:07:37 +0200540 reg_base = base;
Thomas Abraham36ba5d52013-03-09 16:01:52 +0900541 if (!reg_base)
542 panic("%s: unable to ioremap mct address space\n", __func__);
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900543
Marc Zyngiere700e412011-11-03 11:13:12 +0900544 if (mct_int_type == MCT_INT_PPI) {
Marc Zyngiere700e412011-11-03 11:13:12 +0900545
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900546 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
Marc Zyngiere700e412011-11-03 11:13:12 +0900547 exynos4_mct_tick_isr, "MCT",
548 &percpu_mct_tick);
549 WARN(err, "MCT: can't request IRQ %d (%d)\n",
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900550 mct_irqs[MCT_L0_IRQ], err);
Tomasz Figa5df718d2013-09-25 12:00:59 +0200551 } else {
Damian Eppel56a94f12015-06-26 15:23:04 +0200552 for_each_possible_cpu(cpu) {
553 int mct_irq = mct_irqs[MCT_L0_IRQ + cpu];
554 struct mct_clock_event_device *pcpu_mevt =
555 per_cpu_ptr(&percpu_mct_tick, cpu);
556
557 pcpu_mevt->evt.irq = -1;
558
559 irq_set_status_flags(mct_irq, IRQ_NOAUTOEN);
560 if (request_irq(mct_irq,
561 exynos4_mct_tick_isr,
562 IRQF_TIMER | IRQF_NOBALANCING,
563 pcpu_mevt->name, pcpu_mevt)) {
564 pr_err("exynos-mct: cannot register IRQ (cpu%d)\n",
565 cpu);
566
567 continue;
568 }
569 pcpu_mevt->evt.irq = mct_irq;
570 }
Marc Zyngiere700e412011-11-03 11:13:12 +0900571 }
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000572
Stephen Boydee98d272013-02-15 16:40:51 -0800573 err = register_cpu_notifier(&exynos4_mct_cpu_nb);
574 if (err)
575 goto out_irq;
576
577 /* Immediately configure the timer on the boot CPU */
Alexey Klimov479a9322015-06-21 23:41:39 +0300578 exynos4_local_timer_setup(mevt);
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200579 return 0;
Stephen Boydee98d272013-02-15 16:40:51 -0800580
581out_irq:
582 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200583 return err;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900584}
585
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200586static int __init mct_init_dt(struct device_node *np, unsigned int int_type)
Arnd Bergmann228e3022013-04-09 22:07:37 +0200587{
588 u32 nr_irqs, i;
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200589 int ret;
Arnd Bergmann228e3022013-04-09 22:07:37 +0200590
591 mct_int_type = int_type;
592
593 /* This driver uses only one global timer interrupt */
594 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
595
596 /*
597 * Find out the number of local irqs specified. The local
598 * timer irqs are specified after the four global timer
599 * irqs are specified.
600 */
Arnd Bergmannf4636d02013-04-19 22:00:04 +0200601#ifdef CONFIG_OF
Arnd Bergmann228e3022013-04-09 22:07:37 +0200602 nr_irqs = of_irq_count(np);
Arnd Bergmannf4636d02013-04-19 22:00:04 +0200603#else
604 nr_irqs = 0;
605#endif
Arnd Bergmann228e3022013-04-09 22:07:37 +0200606 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
607 mct_irqs[i] = irq_of_parse_and_map(np, i);
608
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200609 ret = exynos4_timer_resources(np, of_iomap(np, 0));
610 if (ret)
611 return ret;
612
613 ret = exynos4_clocksource_init();
614 if (ret)
615 return ret;
616
617 return exynos4_clockevent_init();
Arnd Bergmann228e3022013-04-09 22:07:37 +0200618}
619
620
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200621static int __init mct_init_spi(struct device_node *np)
Arnd Bergmann228e3022013-04-09 22:07:37 +0200622{
623 return mct_init_dt(np, MCT_INT_SPI);
624}
625
Daniel Lezcano5e558eb2016-05-31 19:26:55 +0200626static int __init mct_init_ppi(struct device_node *np)
Arnd Bergmann228e3022013-04-09 22:07:37 +0200627{
628 return mct_init_dt(np, MCT_INT_PPI);
629}
Daniel Lezcano177cf6e2016-06-07 00:27:44 +0200630CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
631CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);