Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 1 | /* linux/arch/arm/mach-exynos4/mct.c |
| 2 | * |
| 3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com |
| 5 | * |
| 6 | * EXYNOS4 MCT(Multi-Core Timer) support |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/sched.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/irq.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/clockchips.h> |
Stephen Boyd | ee98d27 | 2013-02-15 16:40:51 -0800 | [diff] [blame] | 19 | #include <linux/cpu.h> |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/percpu.h> |
Kukjin Kim | 2edb36c | 2012-11-15 15:48:56 +0900 | [diff] [blame] | 23 | #include <linux/of.h> |
Thomas Abraham | 36ba5d5 | 2013-03-09 16:01:52 +0900 | [diff] [blame] | 24 | #include <linux/of_irq.h> |
| 25 | #include <linux/of_address.h> |
Thomas Abraham | 9fbf0c8 | 2013-03-09 16:10:03 +0900 | [diff] [blame] | 26 | #include <linux/clocksource.h> |
Vincent Guittot | 93bfb76 | 2014-05-02 22:27:01 +0900 | [diff] [blame] | 27 | #include <linux/sched_clock.h> |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 28 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 29 | #define EXYNOS4_MCTREG(x) (x) |
| 30 | #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) |
| 31 | #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) |
| 32 | #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) |
| 33 | #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) |
| 34 | #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) |
| 35 | #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) |
| 36 | #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) |
| 37 | #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) |
| 38 | #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) |
| 39 | #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) |
| 40 | #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) |
| 41 | #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) |
| 42 | #define EXYNOS4_MCT_L_MASK (0xffffff00) |
| 43 | |
| 44 | #define MCT_L_TCNTB_OFFSET (0x00) |
| 45 | #define MCT_L_ICNTB_OFFSET (0x08) |
| 46 | #define MCT_L_TCON_OFFSET (0x20) |
| 47 | #define MCT_L_INT_CSTAT_OFFSET (0x30) |
| 48 | #define MCT_L_INT_ENB_OFFSET (0x34) |
| 49 | #define MCT_L_WSTAT_OFFSET (0x40) |
| 50 | #define MCT_G_TCON_START (1 << 8) |
| 51 | #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) |
| 52 | #define MCT_G_TCON_COMP0_ENABLE (1 << 0) |
| 53 | #define MCT_L_TCON_INTERVAL_MODE (1 << 2) |
| 54 | #define MCT_L_TCON_INT_START (1 << 1) |
| 55 | #define MCT_L_TCON_TIMER_START (1 << 0) |
| 56 | |
Changhwan Youn | 4d2e4d7 | 2012-03-09 15:09:21 -0800 | [diff] [blame] | 57 | #define TICK_BASE_CNT 1 |
| 58 | |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 59 | enum { |
| 60 | MCT_INT_SPI, |
| 61 | MCT_INT_PPI |
| 62 | }; |
| 63 | |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 64 | enum { |
| 65 | MCT_G0_IRQ, |
| 66 | MCT_G1_IRQ, |
| 67 | MCT_G2_IRQ, |
| 68 | MCT_G3_IRQ, |
| 69 | MCT_L0_IRQ, |
| 70 | MCT_L1_IRQ, |
| 71 | MCT_L2_IRQ, |
| 72 | MCT_L3_IRQ, |
Chander Kashyap | 6c16ded | 2013-12-02 07:48:23 +0900 | [diff] [blame] | 73 | MCT_L4_IRQ, |
| 74 | MCT_L5_IRQ, |
| 75 | MCT_L6_IRQ, |
| 76 | MCT_L7_IRQ, |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 77 | MCT_NR_IRQS, |
| 78 | }; |
| 79 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 80 | static void __iomem *reg_base; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 81 | static unsigned long clk_rate; |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 82 | static unsigned int mct_int_type; |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 83 | static int mct_irqs[MCT_NR_IRQS]; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 84 | |
| 85 | struct mct_clock_event_device { |
Stephen Boyd | ee98d27 | 2013-02-15 16:40:51 -0800 | [diff] [blame] | 86 | struct clock_event_device evt; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 87 | unsigned long base; |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 88 | char name[10]; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 89 | }; |
| 90 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 91 | static void exynos4_mct_write(unsigned int value, unsigned long offset) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 92 | { |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 93 | unsigned long stat_addr; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 94 | u32 mask; |
| 95 | u32 i; |
| 96 | |
Doug Anderson | fdb06f6 | 2014-07-05 06:43:20 +0900 | [diff] [blame] | 97 | writel_relaxed(value, reg_base + offset); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 98 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 99 | if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { |
Tobias Jakobi | 8c38d28 | 2014-10-22 03:37:08 +0200 | [diff] [blame] | 100 | stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; |
| 101 | switch (offset & ~EXYNOS4_MCT_L_MASK) { |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 102 | case MCT_L_TCON_OFFSET: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 103 | mask = 1 << 3; /* L_TCON write status */ |
| 104 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 105 | case MCT_L_ICNTB_OFFSET: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 106 | mask = 1 << 1; /* L_ICNTB write status */ |
| 107 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 108 | case MCT_L_TCNTB_OFFSET: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 109 | mask = 1 << 0; /* L_TCNTB write status */ |
| 110 | break; |
| 111 | default: |
| 112 | return; |
| 113 | } |
| 114 | } else { |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 115 | switch (offset) { |
| 116 | case EXYNOS4_MCT_G_TCON: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 117 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
| 118 | mask = 1 << 16; /* G_TCON write status */ |
| 119 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 120 | case EXYNOS4_MCT_G_COMP0_L: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 121 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
| 122 | mask = 1 << 0; /* G_COMP0_L write status */ |
| 123 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 124 | case EXYNOS4_MCT_G_COMP0_U: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 125 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
| 126 | mask = 1 << 1; /* G_COMP0_U write status */ |
| 127 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 128 | case EXYNOS4_MCT_G_COMP0_ADD_INCR: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 129 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
| 130 | mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ |
| 131 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 132 | case EXYNOS4_MCT_G_CNT_L: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 133 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; |
| 134 | mask = 1 << 0; /* G_CNT_L write status */ |
| 135 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 136 | case EXYNOS4_MCT_G_CNT_U: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 137 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; |
| 138 | mask = 1 << 1; /* G_CNT_U write status */ |
| 139 | break; |
| 140 | default: |
| 141 | return; |
| 142 | } |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | /* Wait maximum 1 ms until written values are applied */ |
| 146 | for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) |
Doug Anderson | fdb06f6 | 2014-07-05 06:43:20 +0900 | [diff] [blame] | 147 | if (readl_relaxed(reg_base + stat_addr) & mask) { |
| 148 | writel_relaxed(mask, reg_base + stat_addr); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 149 | return; |
| 150 | } |
| 151 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 152 | panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | /* Clocksource handling */ |
Chirantan Ekbote | 1d80415 | 2014-06-12 00:18:48 +0900 | [diff] [blame] | 156 | static void exynos4_mct_frc_start(void) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 157 | { |
| 158 | u32 reg; |
| 159 | |
Doug Anderson | fdb06f6 | 2014-07-05 06:43:20 +0900 | [diff] [blame] | 160 | reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 161 | reg |= MCT_G_TCON_START; |
| 162 | exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); |
| 163 | } |
| 164 | |
Doug Anderson | 3252a64 | 2014-07-05 06:43:26 +0900 | [diff] [blame] | 165 | /** |
| 166 | * exynos4_read_count_64 - Read all 64-bits of the global counter |
| 167 | * |
| 168 | * This will read all 64-bits of the global counter taking care to make sure |
| 169 | * that the upper and lower half match. Note that reading the MCT can be quite |
| 170 | * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half |
| 171 | * only) version when possible. |
| 172 | * |
| 173 | * Returns the number of cycles in the global counter. |
| 174 | */ |
| 175 | static u64 exynos4_read_count_64(void) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 176 | { |
| 177 | unsigned int lo, hi; |
Doug Anderson | fdb06f6 | 2014-07-05 06:43:20 +0900 | [diff] [blame] | 178 | u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 179 | |
| 180 | do { |
| 181 | hi = hi2; |
Doug Anderson | fdb06f6 | 2014-07-05 06:43:20 +0900 | [diff] [blame] | 182 | lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); |
| 183 | hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 184 | } while (hi != hi2); |
| 185 | |
| 186 | return ((cycle_t)hi << 32) | lo; |
| 187 | } |
| 188 | |
Doug Anderson | 3252a64 | 2014-07-05 06:43:26 +0900 | [diff] [blame] | 189 | /** |
| 190 | * exynos4_read_count_32 - Read the lower 32-bits of the global counter |
| 191 | * |
| 192 | * This will read just the lower 32-bits of the global counter. This is marked |
| 193 | * as notrace so it can be used by the scheduler clock. |
| 194 | * |
| 195 | * Returns the number of cycles in the global counter (lower 32 bits). |
| 196 | */ |
| 197 | static u32 notrace exynos4_read_count_32(void) |
| 198 | { |
| 199 | return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); |
| 200 | } |
| 201 | |
Doug Anderson | 89e6a13 | 2014-07-05 06:38:55 +0900 | [diff] [blame] | 202 | static cycle_t exynos4_frc_read(struct clocksource *cs) |
| 203 | { |
Doug Anderson | 3252a64 | 2014-07-05 06:43:26 +0900 | [diff] [blame] | 204 | return exynos4_read_count_32(); |
Doug Anderson | 89e6a13 | 2014-07-05 06:38:55 +0900 | [diff] [blame] | 205 | } |
| 206 | |
Changhwan Youn | aa421c1 | 2011-09-02 14:10:52 +0900 | [diff] [blame] | 207 | static void exynos4_frc_resume(struct clocksource *cs) |
| 208 | { |
Chirantan Ekbote | 1d80415 | 2014-06-12 00:18:48 +0900 | [diff] [blame] | 209 | exynos4_mct_frc_start(); |
Changhwan Youn | aa421c1 | 2011-09-02 14:10:52 +0900 | [diff] [blame] | 210 | } |
| 211 | |
Krzysztof Kozlowski | 6c10bf6 | 2015-04-30 13:42:52 +0900 | [diff] [blame] | 212 | static struct clocksource mct_frc = { |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 213 | .name = "mct-frc", |
| 214 | .rating = 400, |
| 215 | .read = exynos4_frc_read, |
Doug Anderson | 3252a64 | 2014-07-05 06:43:26 +0900 | [diff] [blame] | 216 | .mask = CLOCKSOURCE_MASK(32), |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 217 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
Changhwan Youn | aa421c1 | 2011-09-02 14:10:52 +0900 | [diff] [blame] | 218 | .resume = exynos4_frc_resume, |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 219 | }; |
| 220 | |
Vincent Guittot | 93bfb76 | 2014-05-02 22:27:01 +0900 | [diff] [blame] | 221 | static u64 notrace exynos4_read_sched_clock(void) |
| 222 | { |
Doug Anderson | 3252a64 | 2014-07-05 06:43:26 +0900 | [diff] [blame] | 223 | return exynos4_read_count_32(); |
Vincent Guittot | 93bfb76 | 2014-05-02 22:27:01 +0900 | [diff] [blame] | 224 | } |
| 225 | |
Amit Daniel Kachhap | 8bf13a4 | 2014-07-05 06:40:23 +0900 | [diff] [blame] | 226 | static struct delay_timer exynos4_delay_timer; |
| 227 | |
| 228 | static cycles_t exynos4_read_current_timer(void) |
| 229 | { |
Doug Anderson | 3252a64 | 2014-07-05 06:43:26 +0900 | [diff] [blame] | 230 | BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32), |
| 231 | "cycles_t needs to move to 32-bit for ARM64 usage"); |
| 232 | return exynos4_read_count_32(); |
Amit Daniel Kachhap | 8bf13a4 | 2014-07-05 06:40:23 +0900 | [diff] [blame] | 233 | } |
| 234 | |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 235 | static int __init exynos4_clocksource_init(void) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 236 | { |
Chirantan Ekbote | 1d80415 | 2014-06-12 00:18:48 +0900 | [diff] [blame] | 237 | exynos4_mct_frc_start(); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 238 | |
Amit Daniel Kachhap | 8bf13a4 | 2014-07-05 06:40:23 +0900 | [diff] [blame] | 239 | exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; |
| 240 | exynos4_delay_timer.freq = clk_rate; |
| 241 | register_current_timer_delay(&exynos4_delay_timer); |
| 242 | |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 243 | if (clocksource_register_hz(&mct_frc, clk_rate)) |
| 244 | panic("%s: can't register clocksource\n", mct_frc.name); |
Vincent Guittot | 93bfb76 | 2014-05-02 22:27:01 +0900 | [diff] [blame] | 245 | |
Doug Anderson | 3252a64 | 2014-07-05 06:43:26 +0900 | [diff] [blame] | 246 | sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 247 | |
| 248 | return 0; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | static void exynos4_mct_comp0_stop(void) |
| 252 | { |
| 253 | unsigned int tcon; |
| 254 | |
Doug Anderson | fdb06f6 | 2014-07-05 06:43:20 +0900 | [diff] [blame] | 255 | tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 256 | tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); |
| 257 | |
| 258 | exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); |
| 259 | exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB); |
| 260 | } |
| 261 | |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 262 | static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 263 | { |
| 264 | unsigned int tcon; |
| 265 | cycle_t comp_cycle; |
| 266 | |
Doug Anderson | fdb06f6 | 2014-07-05 06:43:20 +0900 | [diff] [blame] | 267 | tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 268 | |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 269 | if (periodic) { |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 270 | tcon |= MCT_G_TCON_COMP0_AUTO_INC; |
| 271 | exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); |
| 272 | } |
| 273 | |
Doug Anderson | 3252a64 | 2014-07-05 06:43:26 +0900 | [diff] [blame] | 274 | comp_cycle = exynos4_read_count_64() + cycles; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 275 | exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L); |
| 276 | exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U); |
| 277 | |
| 278 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); |
| 279 | |
| 280 | tcon |= MCT_G_TCON_COMP0_ENABLE; |
| 281 | exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); |
| 282 | } |
| 283 | |
| 284 | static int exynos4_comp_set_next_event(unsigned long cycles, |
| 285 | struct clock_event_device *evt) |
| 286 | { |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 287 | exynos4_mct_comp0_start(false, cycles); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 288 | |
| 289 | return 0; |
| 290 | } |
| 291 | |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 292 | static int mct_set_state_shutdown(struct clock_event_device *evt) |
| 293 | { |
| 294 | exynos4_mct_comp0_stop(); |
| 295 | return 0; |
| 296 | } |
| 297 | |
| 298 | static int mct_set_state_periodic(struct clock_event_device *evt) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 299 | { |
Changhwan Youn | 4d2e4d7 | 2012-03-09 15:09:21 -0800 | [diff] [blame] | 300 | unsigned long cycles_per_jiffy; |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 301 | |
| 302 | cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) |
| 303 | >> evt->shift); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 304 | exynos4_mct_comp0_stop(); |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 305 | exynos4_mct_comp0_start(true, cycles_per_jiffy); |
| 306 | return 0; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 307 | } |
| 308 | |
| 309 | static struct clock_event_device mct_comp_device = { |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 310 | .name = "mct-comp", |
| 311 | .features = CLOCK_EVT_FEAT_PERIODIC | |
| 312 | CLOCK_EVT_FEAT_ONESHOT, |
| 313 | .rating = 250, |
| 314 | .set_next_event = exynos4_comp_set_next_event, |
| 315 | .set_state_periodic = mct_set_state_periodic, |
| 316 | .set_state_shutdown = mct_set_state_shutdown, |
| 317 | .set_state_oneshot = mct_set_state_shutdown, |
Viresh Kumar | 07f101d | 2015-12-23 16:59:14 +0530 | [diff] [blame] | 318 | .set_state_oneshot_stopped = mct_set_state_shutdown, |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 319 | .tick_resume = mct_set_state_shutdown, |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 320 | }; |
| 321 | |
| 322 | static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) |
| 323 | { |
| 324 | struct clock_event_device *evt = dev_id; |
| 325 | |
| 326 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT); |
| 327 | |
| 328 | evt->event_handler(evt); |
| 329 | |
| 330 | return IRQ_HANDLED; |
| 331 | } |
| 332 | |
| 333 | static struct irqaction mct_comp_event_irq = { |
| 334 | .name = "mct_comp_irq", |
| 335 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
| 336 | .handler = exynos4_mct_comp_isr, |
| 337 | .dev_id = &mct_comp_device, |
| 338 | }; |
| 339 | |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 340 | static int exynos4_clockevent_init(void) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 341 | { |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 342 | mct_comp_device.cpumask = cpumask_of(0); |
Shawn Guo | 838a2ae | 2013-01-12 11:50:05 +0000 | [diff] [blame] | 343 | clockevents_config_and_register(&mct_comp_device, clk_rate, |
| 344 | 0xf, 0xffffffff); |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 345 | setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq); |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 346 | |
| 347 | return 0; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 348 | } |
| 349 | |
Kukjin Kim | 991a6c7 | 2011-12-08 10:04:49 +0900 | [diff] [blame] | 350 | static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick); |
| 351 | |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 352 | /* Clock event handling */ |
| 353 | static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) |
| 354 | { |
| 355 | unsigned long tmp; |
| 356 | unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 357 | unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 358 | |
Doug Anderson | fdb06f6 | 2014-07-05 06:43:20 +0900 | [diff] [blame] | 359 | tmp = readl_relaxed(reg_base + offset); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 360 | if (tmp & mask) { |
| 361 | tmp &= ~mask; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 362 | exynos4_mct_write(tmp, offset); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 363 | } |
| 364 | } |
| 365 | |
| 366 | static void exynos4_mct_tick_start(unsigned long cycles, |
| 367 | struct mct_clock_event_device *mevt) |
| 368 | { |
| 369 | unsigned long tmp; |
| 370 | |
| 371 | exynos4_mct_tick_stop(mevt); |
| 372 | |
| 373 | tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ |
| 374 | |
| 375 | /* update interrupt count buffer */ |
| 376 | exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); |
| 377 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 378 | /* enable MCT tick interrupt */ |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 379 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); |
| 380 | |
Doug Anderson | fdb06f6 | 2014-07-05 06:43:20 +0900 | [diff] [blame] | 381 | tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 382 | tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | |
| 383 | MCT_L_TCON_INTERVAL_MODE; |
| 384 | exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); |
| 385 | } |
| 386 | |
| 387 | static int exynos4_tick_set_next_event(unsigned long cycles, |
| 388 | struct clock_event_device *evt) |
| 389 | { |
Alexey Klimov | 31f7987 | 2015-09-04 02:49:58 +0300 | [diff] [blame] | 390 | struct mct_clock_event_device *mevt; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 391 | |
Alexey Klimov | 31f7987 | 2015-09-04 02:49:58 +0300 | [diff] [blame] | 392 | mevt = container_of(evt, struct mct_clock_event_device, evt); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 393 | exynos4_mct_tick_start(cycles, mevt); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 394 | return 0; |
| 395 | } |
| 396 | |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 397 | static int set_state_shutdown(struct clock_event_device *evt) |
| 398 | { |
Alexey Klimov | 31f7987 | 2015-09-04 02:49:58 +0300 | [diff] [blame] | 399 | struct mct_clock_event_device *mevt; |
| 400 | |
| 401 | mevt = container_of(evt, struct mct_clock_event_device, evt); |
| 402 | exynos4_mct_tick_stop(mevt); |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 403 | return 0; |
| 404 | } |
| 405 | |
| 406 | static int set_state_periodic(struct clock_event_device *evt) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 407 | { |
Alexey Klimov | 31f7987 | 2015-09-04 02:49:58 +0300 | [diff] [blame] | 408 | struct mct_clock_event_device *mevt; |
Changhwan Youn | 4d2e4d7 | 2012-03-09 15:09:21 -0800 | [diff] [blame] | 409 | unsigned long cycles_per_jiffy; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 410 | |
Alexey Klimov | 31f7987 | 2015-09-04 02:49:58 +0300 | [diff] [blame] | 411 | mevt = container_of(evt, struct mct_clock_event_device, evt); |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 412 | cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) |
| 413 | >> evt->shift); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 414 | exynos4_mct_tick_stop(mevt); |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 415 | exynos4_mct_tick_start(cycles_per_jiffy, mevt); |
| 416 | return 0; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 417 | } |
| 418 | |
Krzysztof Kozlowski | 3728567 | 2015-04-30 13:42:51 +0900 | [diff] [blame] | 419 | static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 420 | { |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 421 | /* |
| 422 | * This is for supporting oneshot mode. |
| 423 | * Mct would generate interrupt periodically |
| 424 | * without explicit stopping. |
| 425 | */ |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 426 | if (!clockevent_state_periodic(&mevt->evt)) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 427 | exynos4_mct_tick_stop(mevt); |
| 428 | |
| 429 | /* Clear the MCT tick interrupt */ |
Krzysztof Kozlowski | 3728567 | 2015-04-30 13:42:51 +0900 | [diff] [blame] | 430 | if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 431 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) |
| 435 | { |
| 436 | struct mct_clock_event_device *mevt = dev_id; |
Stephen Boyd | ee98d27 | 2013-02-15 16:40:51 -0800 | [diff] [blame] | 437 | struct clock_event_device *evt = &mevt->evt; |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 438 | |
| 439 | exynos4_mct_tick_clear(mevt); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 440 | |
| 441 | evt->event_handler(evt); |
| 442 | |
| 443 | return IRQ_HANDLED; |
| 444 | } |
| 445 | |
Alexey Klimov | 479a932 | 2015-06-21 23:41:39 +0300 | [diff] [blame] | 446 | static int exynos4_local_timer_setup(struct mct_clock_event_device *mevt) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 447 | { |
Alexey Klimov | 479a932 | 2015-06-21 23:41:39 +0300 | [diff] [blame] | 448 | struct clock_event_device *evt = &mevt->evt; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 449 | unsigned int cpu = smp_processor_id(); |
| 450 | |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 451 | mevt->base = EXYNOS4_MCT_L_BASE(cpu); |
Dan Carpenter | 09e1517 | 2014-03-01 16:57:14 +0300 | [diff] [blame] | 452 | snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 453 | |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 454 | evt->name = mevt->name; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 455 | evt->cpumask = cpumask_of(cpu); |
| 456 | evt->set_next_event = exynos4_tick_set_next_event; |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 457 | evt->set_state_periodic = set_state_periodic; |
| 458 | evt->set_state_shutdown = set_state_shutdown; |
| 459 | evt->set_state_oneshot = set_state_shutdown; |
Viresh Kumar | 07f101d | 2015-12-23 16:59:14 +0530 | [diff] [blame] | 460 | evt->set_state_oneshot_stopped = set_state_shutdown; |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 461 | evt->tick_resume = set_state_shutdown; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 462 | evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
| 463 | evt->rating = 450; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 464 | |
Changhwan Youn | 4d2e4d7 | 2012-03-09 15:09:21 -0800 | [diff] [blame] | 465 | exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 466 | |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 467 | if (mct_int_type == MCT_INT_SPI) { |
Damian Eppel | 56a94f1 | 2015-06-26 15:23:04 +0200 | [diff] [blame] | 468 | |
| 469 | if (evt->irq == -1) |
Chander Kashyap | 7114cd7 | 2013-06-19 00:29:35 +0900 | [diff] [blame] | 470 | return -EIO; |
Damian Eppel | 56a94f1 | 2015-06-26 15:23:04 +0200 | [diff] [blame] | 471 | |
| 472 | irq_force_affinity(evt->irq, cpumask_of(cpu)); |
| 473 | enable_irq(evt->irq); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 474 | } else { |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 475 | enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 476 | } |
Krzysztof Kozlowski | 8db6e51 | 2014-04-16 14:36:45 +0000 | [diff] [blame] | 477 | clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), |
| 478 | 0xf, 0x7fffffff); |
Kukjin Kim | 4d487d7 | 2011-08-24 16:07:39 +0900 | [diff] [blame] | 479 | |
| 480 | return 0; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 481 | } |
| 482 | |
Alexey Klimov | 479a932 | 2015-06-21 23:41:39 +0300 | [diff] [blame] | 483 | static void exynos4_local_timer_stop(struct mct_clock_event_device *mevt) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 484 | { |
Alexey Klimov | 479a932 | 2015-06-21 23:41:39 +0300 | [diff] [blame] | 485 | struct clock_event_device *evt = &mevt->evt; |
| 486 | |
Viresh Kumar | 79e436d | 2015-06-18 16:24:20 +0530 | [diff] [blame] | 487 | evt->set_state_shutdown(evt); |
Damian Eppel | 56a94f1 | 2015-06-26 15:23:04 +0200 | [diff] [blame] | 488 | if (mct_int_type == MCT_INT_SPI) { |
| 489 | if (evt->irq != -1) |
| 490 | disable_irq_nosync(evt->irq); |
| 491 | } else { |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 492 | disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); |
Damian Eppel | 56a94f1 | 2015-06-26 15:23:04 +0200 | [diff] [blame] | 493 | } |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 494 | } |
Marc Zyngier | a8cb604 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 495 | |
Olof Johansson | 47dcd35 | 2013-07-23 14:51:34 -0700 | [diff] [blame] | 496 | static int exynos4_mct_cpu_notify(struct notifier_block *self, |
Stephen Boyd | ee98d27 | 2013-02-15 16:40:51 -0800 | [diff] [blame] | 497 | unsigned long action, void *hcpu) |
| 498 | { |
| 499 | struct mct_clock_event_device *mevt; |
| 500 | |
| 501 | /* |
| 502 | * Grab cpu pointer in each case to avoid spurious |
| 503 | * preemptible warnings |
| 504 | */ |
| 505 | switch (action & ~CPU_TASKS_FROZEN) { |
| 506 | case CPU_STARTING: |
| 507 | mevt = this_cpu_ptr(&percpu_mct_tick); |
Alexey Klimov | 479a932 | 2015-06-21 23:41:39 +0300 | [diff] [blame] | 508 | exynos4_local_timer_setup(mevt); |
Stephen Boyd | ee98d27 | 2013-02-15 16:40:51 -0800 | [diff] [blame] | 509 | break; |
| 510 | case CPU_DYING: |
| 511 | mevt = this_cpu_ptr(&percpu_mct_tick); |
Alexey Klimov | 479a932 | 2015-06-21 23:41:39 +0300 | [diff] [blame] | 512 | exynos4_local_timer_stop(mevt); |
Stephen Boyd | ee98d27 | 2013-02-15 16:40:51 -0800 | [diff] [blame] | 513 | break; |
| 514 | } |
| 515 | |
| 516 | return NOTIFY_OK; |
| 517 | } |
| 518 | |
Olof Johansson | 47dcd35 | 2013-07-23 14:51:34 -0700 | [diff] [blame] | 519 | static struct notifier_block exynos4_mct_cpu_nb = { |
Stephen Boyd | ee98d27 | 2013-02-15 16:40:51 -0800 | [diff] [blame] | 520 | .notifier_call = exynos4_mct_cpu_notify, |
Marc Zyngier | a8cb604 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 521 | }; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 522 | |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 523 | static int __init exynos4_timer_resources(struct device_node *np, void __iomem *base) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 524 | { |
Damian Eppel | 56a94f1 | 2015-06-26 15:23:04 +0200 | [diff] [blame] | 525 | int err, cpu; |
Stephen Boyd | ee98d27 | 2013-02-15 16:40:51 -0800 | [diff] [blame] | 526 | struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); |
Thomas Abraham | ca9048e | 2013-03-09 17:10:37 +0900 | [diff] [blame] | 527 | struct clk *mct_clk, *tick_clk; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 528 | |
Thomas Abraham | 415ac2e | 2013-03-09 17:10:31 +0900 | [diff] [blame] | 529 | tick_clk = np ? of_clk_get_by_name(np, "fin_pll") : |
| 530 | clk_get(NULL, "fin_pll"); |
| 531 | if (IS_ERR(tick_clk)) |
| 532 | panic("%s: unable to determine tick clock rate\n", __func__); |
| 533 | clk_rate = clk_get_rate(tick_clk); |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 534 | |
Thomas Abraham | ca9048e | 2013-03-09 17:10:37 +0900 | [diff] [blame] | 535 | mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct"); |
| 536 | if (IS_ERR(mct_clk)) |
| 537 | panic("%s: unable to retrieve mct clock instance\n", __func__); |
| 538 | clk_prepare_enable(mct_clk); |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 539 | |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 540 | reg_base = base; |
Thomas Abraham | 36ba5d5 | 2013-03-09 16:01:52 +0900 | [diff] [blame] | 541 | if (!reg_base) |
| 542 | panic("%s: unable to ioremap mct address space\n", __func__); |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 543 | |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 544 | if (mct_int_type == MCT_INT_PPI) { |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 545 | |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 546 | err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 547 | exynos4_mct_tick_isr, "MCT", |
| 548 | &percpu_mct_tick); |
| 549 | WARN(err, "MCT: can't request IRQ %d (%d)\n", |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 550 | mct_irqs[MCT_L0_IRQ], err); |
Tomasz Figa | 5df718d | 2013-09-25 12:00:59 +0200 | [diff] [blame] | 551 | } else { |
Damian Eppel | 56a94f1 | 2015-06-26 15:23:04 +0200 | [diff] [blame] | 552 | for_each_possible_cpu(cpu) { |
| 553 | int mct_irq = mct_irqs[MCT_L0_IRQ + cpu]; |
| 554 | struct mct_clock_event_device *pcpu_mevt = |
| 555 | per_cpu_ptr(&percpu_mct_tick, cpu); |
| 556 | |
| 557 | pcpu_mevt->evt.irq = -1; |
| 558 | |
| 559 | irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); |
| 560 | if (request_irq(mct_irq, |
| 561 | exynos4_mct_tick_isr, |
| 562 | IRQF_TIMER | IRQF_NOBALANCING, |
| 563 | pcpu_mevt->name, pcpu_mevt)) { |
| 564 | pr_err("exynos-mct: cannot register IRQ (cpu%d)\n", |
| 565 | cpu); |
| 566 | |
| 567 | continue; |
| 568 | } |
| 569 | pcpu_mevt->evt.irq = mct_irq; |
| 570 | } |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 571 | } |
Marc Zyngier | a8cb604 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 572 | |
Stephen Boyd | ee98d27 | 2013-02-15 16:40:51 -0800 | [diff] [blame] | 573 | err = register_cpu_notifier(&exynos4_mct_cpu_nb); |
| 574 | if (err) |
| 575 | goto out_irq; |
| 576 | |
| 577 | /* Immediately configure the timer on the boot CPU */ |
Alexey Klimov | 479a932 | 2015-06-21 23:41:39 +0300 | [diff] [blame] | 578 | exynos4_local_timer_setup(mevt); |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 579 | return 0; |
Stephen Boyd | ee98d27 | 2013-02-15 16:40:51 -0800 | [diff] [blame] | 580 | |
| 581 | out_irq: |
| 582 | free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 583 | return err; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 584 | } |
| 585 | |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 586 | static int __init mct_init_dt(struct device_node *np, unsigned int int_type) |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 587 | { |
| 588 | u32 nr_irqs, i; |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 589 | int ret; |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 590 | |
| 591 | mct_int_type = int_type; |
| 592 | |
| 593 | /* This driver uses only one global timer interrupt */ |
| 594 | mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); |
| 595 | |
| 596 | /* |
| 597 | * Find out the number of local irqs specified. The local |
| 598 | * timer irqs are specified after the four global timer |
| 599 | * irqs are specified. |
| 600 | */ |
Arnd Bergmann | f4636d0 | 2013-04-19 22:00:04 +0200 | [diff] [blame] | 601 | #ifdef CONFIG_OF |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 602 | nr_irqs = of_irq_count(np); |
Arnd Bergmann | f4636d0 | 2013-04-19 22:00:04 +0200 | [diff] [blame] | 603 | #else |
| 604 | nr_irqs = 0; |
| 605 | #endif |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 606 | for (i = MCT_L0_IRQ; i < nr_irqs; i++) |
| 607 | mct_irqs[i] = irq_of_parse_and_map(np, i); |
| 608 | |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 609 | ret = exynos4_timer_resources(np, of_iomap(np, 0)); |
| 610 | if (ret) |
| 611 | return ret; |
| 612 | |
| 613 | ret = exynos4_clocksource_init(); |
| 614 | if (ret) |
| 615 | return ret; |
| 616 | |
| 617 | return exynos4_clockevent_init(); |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 621 | static int __init mct_init_spi(struct device_node *np) |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 622 | { |
| 623 | return mct_init_dt(np, MCT_INT_SPI); |
| 624 | } |
| 625 | |
Daniel Lezcano | 5e558eb | 2016-05-31 19:26:55 +0200 | [diff] [blame] | 626 | static int __init mct_init_ppi(struct device_node *np) |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 627 | { |
| 628 | return mct_init_dt(np, MCT_INT_PPI); |
| 629 | } |
Daniel Lezcano | 177cf6e | 2016-06-07 00:27:44 +0200 | [diff] [blame^] | 630 | CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); |
| 631 | CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); |