Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on |
| 3 | * AVR32 systems.) |
| 4 | * |
| 5 | * Copyright (C) 2007 Atmel Corporation |
Viresh Kumar | aecb7b6 | 2011-05-24 14:04:09 +0530 | [diff] [blame] | 6 | * Copyright (C) 2010-2011 ST Microelectronics |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | #ifndef DW_DMAC_H |
| 13 | #define DW_DMAC_H |
| 14 | |
| 15 | #include <linux/dmaengine.h> |
| 16 | |
| 17 | /** |
| 18 | * struct dw_dma_platform_data - Controller configuration parameters |
| 19 | * @nr_channels: Number of channels supported by hardware (max 8) |
Jamie Iles | 95ea759 | 2011-01-21 14:11:54 +0000 | [diff] [blame] | 20 | * @is_private: The device channels should be marked as private and not for |
| 21 | * by the general purpose DMA channel allocator. |
Viresh Kumar | 177d2bf | 2012-10-16 09:49:16 +0530 | [diff] [blame^] | 22 | * @chan_allocation_order: Allocate channels starting from 0 or 7 |
| 23 | * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 24 | * @block_size: Maximum block size supported by the controller |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 25 | * @nr_masters: Number of AHB masters supported by the controller |
| 26 | * @data_width: Maximum data width supported by hardware per AHB master |
| 27 | * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 28 | */ |
| 29 | struct dw_dma_platform_data { |
| 30 | unsigned int nr_channels; |
Jamie Iles | 95ea759 | 2011-01-21 14:11:54 +0000 | [diff] [blame] | 31 | bool is_private; |
Viresh Kumar | b0c3130 | 2011-03-03 15:47:21 +0530 | [diff] [blame] | 32 | #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ |
| 33 | #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ |
| 34 | unsigned char chan_allocation_order; |
Viresh Kumar | 93317e8 | 2011-03-03 15:47:22 +0530 | [diff] [blame] | 35 | #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ |
| 36 | #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ |
| 37 | unsigned char chan_priority; |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 38 | unsigned short block_size; |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 39 | unsigned char nr_masters; |
| 40 | unsigned char data_width[4]; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 41 | }; |
| 42 | |
Viresh KUMAR | ee66509 | 2011-03-04 15:42:51 +0530 | [diff] [blame] | 43 | /* bursts size */ |
| 44 | enum dw_dma_msize { |
| 45 | DW_DMA_MSIZE_1, |
| 46 | DW_DMA_MSIZE_4, |
| 47 | DW_DMA_MSIZE_8, |
| 48 | DW_DMA_MSIZE_16, |
| 49 | DW_DMA_MSIZE_32, |
| 50 | DW_DMA_MSIZE_64, |
| 51 | DW_DMA_MSIZE_128, |
| 52 | DW_DMA_MSIZE_256, |
| 53 | }; |
| 54 | |
Dan Williams | 74465b4 | 2009-01-06 11:38:16 -0700 | [diff] [blame] | 55 | /** |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 56 | * struct dw_dma_slave - Controller-specific information about a slave |
Dan Williams | 74465b4 | 2009-01-06 11:38:16 -0700 | [diff] [blame] | 57 | * |
| 58 | * @dma_dev: required DMA master device |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 59 | * @cfg_hi: Platform-specific initializer for the CFG_HI register |
| 60 | * @cfg_lo: Platform-specific initializer for the CFG_LO register |
Viresh Kumar | 59c22fc | 2011-03-03 15:47:23 +0530 | [diff] [blame] | 61 | * @src_master: src master for transfers on allocated channel. |
| 62 | * @dst_master: dest master for transfers on allocated channel. |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 63 | */ |
| 64 | struct dw_dma_slave { |
Dan Williams | 74465b4 | 2009-01-06 11:38:16 -0700 | [diff] [blame] | 65 | struct device *dma_dev; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 66 | u32 cfg_hi; |
| 67 | u32 cfg_lo; |
Viresh Kumar | 59c22fc | 2011-03-03 15:47:23 +0530 | [diff] [blame] | 68 | u8 src_master; |
| 69 | u8 dst_master; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | /* Platform-configurable bits in CFG_HI */ |
| 73 | #define DWC_CFGH_FCMODE (1 << 0) |
| 74 | #define DWC_CFGH_FIFO_MODE (1 << 1) |
| 75 | #define DWC_CFGH_PROTCTL(x) ((x) << 2) |
| 76 | #define DWC_CFGH_SRC_PER(x) ((x) << 7) |
| 77 | #define DWC_CFGH_DST_PER(x) ((x) << 11) |
| 78 | |
| 79 | /* Platform-configurable bits in CFG_LO */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 80 | #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ |
| 81 | #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) |
| 82 | #define DWC_CFGL_LOCK_CH_XACT (2 << 12) |
| 83 | #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ |
| 84 | #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) |
| 85 | #define DWC_CFGL_LOCK_BUS_XACT (2 << 14) |
| 86 | #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ |
| 87 | #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ |
| 88 | #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ |
| 89 | #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ |
| 90 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 91 | /* DMA API extensions */ |
| 92 | struct dw_cyclic_desc { |
| 93 | struct dw_desc **desc; |
| 94 | unsigned long periods; |
| 95 | void (*period_callback)(void *param); |
| 96 | void *period_callback_param; |
| 97 | }; |
| 98 | |
| 99 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, |
| 100 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 101 | enum dma_transfer_direction direction); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 102 | void dw_dma_cyclic_free(struct dma_chan *chan); |
| 103 | int dw_dma_cyclic_start(struct dma_chan *chan); |
| 104 | void dw_dma_cyclic_stop(struct dma_chan *chan); |
| 105 | |
| 106 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan); |
| 107 | |
| 108 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan); |
| 109 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 110 | #endif /* DW_DMAC_H */ |