Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 10 Gigabit PCI Express Linux driver |
| 4 | Copyright(c) 1999 - 2007 Intel Corporation. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | Linux NICS <linux.nics@intel.com> |
| 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | |
| 27 | *******************************************************************************/ |
| 28 | |
| 29 | #ifndef _IXGBE_H_ |
| 30 | #define _IXGBE_H_ |
| 31 | |
| 32 | #include <linux/types.h> |
| 33 | #include <linux/pci.h> |
| 34 | #include <linux/netdevice.h> |
Mallikarjuna R Chilakala | 177db6f | 2008-06-18 15:32:19 -0700 | [diff] [blame^] | 35 | #include <linux/inet_lro.h> |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 36 | |
| 37 | #include "ixgbe_type.h" |
| 38 | #include "ixgbe_common.h" |
| 39 | |
Jeb Cramer | bd0362d | 2008-03-03 15:04:02 -0800 | [diff] [blame] | 40 | #ifdef CONFIG_DCA |
| 41 | #include <linux/dca.h> |
| 42 | #endif |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 43 | |
| 44 | #define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args) |
| 45 | |
| 46 | #define PFX "ixgbe: " |
| 47 | #define DPRINTK(nlevel, klevel, fmt, args...) \ |
| 48 | ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \ |
| 49 | printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \ |
| 50 | __FUNCTION__ , ## args))) |
| 51 | |
| 52 | /* TX/RX descriptor defines */ |
| 53 | #define IXGBE_DEFAULT_TXD 1024 |
| 54 | #define IXGBE_MAX_TXD 4096 |
| 55 | #define IXGBE_MIN_TXD 64 |
| 56 | |
| 57 | #define IXGBE_DEFAULT_RXD 1024 |
| 58 | #define IXGBE_MAX_RXD 4096 |
| 59 | #define IXGBE_MIN_RXD 64 |
| 60 | |
| 61 | #define IXGBE_DEFAULT_RXQ 1 |
| 62 | #define IXGBE_MAX_RXQ 1 |
| 63 | #define IXGBE_MIN_RXQ 1 |
| 64 | |
| 65 | #define IXGBE_DEFAULT_ITR_RX_USECS 125 /* 8k irqs/sec */ |
| 66 | #define IXGBE_DEFAULT_ITR_TX_USECS 250 /* 4k irqs/sec */ |
| 67 | #define IXGBE_MIN_ITR_USECS 100 /* 500k irqs/sec */ |
| 68 | #define IXGBE_MAX_ITR_USECS 10000 /* 100 irqs/sec */ |
| 69 | |
| 70 | /* flow control */ |
| 71 | #define IXGBE_DEFAULT_FCRTL 0x10000 |
| 72 | #define IXGBE_MIN_FCRTL 0 |
| 73 | #define IXGBE_MAX_FCRTL 0x7FF80 |
| 74 | #define IXGBE_DEFAULT_FCRTH 0x20000 |
| 75 | #define IXGBE_MIN_FCRTH 0 |
| 76 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
| 77 | #define IXGBE_DEFAULT_FCPAUSE 0x6800 /* may be too long */ |
| 78 | #define IXGBE_MIN_FCPAUSE 0 |
| 79 | #define IXGBE_MAX_FCPAUSE 0xFFFF |
| 80 | |
| 81 | /* Supported Rx Buffer Sizes */ |
| 82 | #define IXGBE_RXBUFFER_64 64 /* Used for packet split */ |
| 83 | #define IXGBE_RXBUFFER_128 128 /* Used for packet split */ |
| 84 | #define IXGBE_RXBUFFER_256 256 /* Used for packet split */ |
| 85 | #define IXGBE_RXBUFFER_2048 2048 |
| 86 | |
| 87 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 |
| 88 | |
| 89 | #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) |
| 90 | |
| 91 | /* How many Tx Descriptors do we need to call netif_wake_queue? */ |
| 92 | #define IXGBE_TX_QUEUE_WAKE 16 |
| 93 | |
| 94 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
| 95 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
| 96 | |
| 97 | #define IXGBE_TX_FLAGS_CSUM (u32)(1) |
| 98 | #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1) |
| 99 | #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2) |
| 100 | #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3) |
| 101 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
| 102 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
| 103 | |
Mallikarjuna R Chilakala | 177db6f | 2008-06-18 15:32:19 -0700 | [diff] [blame^] | 104 | #define IXGBE_MAX_LRO_DESCRIPTORS 8 |
| 105 | #define IXGBE_MAX_LRO_AGGREGATE 32 |
| 106 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 107 | /* wrapper around a pointer to a socket buffer, |
| 108 | * so a DMA handle can be stored along with the buffer */ |
| 109 | struct ixgbe_tx_buffer { |
| 110 | struct sk_buff *skb; |
| 111 | dma_addr_t dma; |
| 112 | unsigned long time_stamp; |
| 113 | u16 length; |
| 114 | u16 next_to_watch; |
| 115 | }; |
| 116 | |
| 117 | struct ixgbe_rx_buffer { |
| 118 | struct sk_buff *skb; |
| 119 | dma_addr_t dma; |
| 120 | struct page *page; |
| 121 | dma_addr_t page_dma; |
| 122 | }; |
| 123 | |
| 124 | struct ixgbe_queue_stats { |
| 125 | u64 packets; |
| 126 | u64 bytes; |
| 127 | }; |
| 128 | |
| 129 | struct ixgbe_ring { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 130 | void *desc; /* descriptor ring memory */ |
| 131 | dma_addr_t dma; /* phys. address of descriptor ring */ |
| 132 | unsigned int size; /* length in bytes */ |
| 133 | unsigned int count; /* amount of descriptors */ |
| 134 | unsigned int next_to_use; |
| 135 | unsigned int next_to_clean; |
| 136 | |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 137 | int queue_index; /* needed for multiqueue queue management */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 138 | union { |
| 139 | struct ixgbe_tx_buffer *tx_buffer_info; |
| 140 | struct ixgbe_rx_buffer *rx_buffer_info; |
| 141 | }; |
| 142 | |
| 143 | u16 head; |
| 144 | u16 tail; |
| 145 | |
Ayyappan Veeraiyan | f494e8f | 2008-03-03 15:03:57 -0800 | [diff] [blame] | 146 | unsigned int total_bytes; |
| 147 | unsigned int total_packets; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 148 | |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 149 | u16 reg_idx; /* holds the special value that gets the hardware register |
| 150 | * offset associated with this ring, which is different |
| 151 | * for DCE and RSS modes */ |
Jeb Cramer | bd0362d | 2008-03-03 15:04:02 -0800 | [diff] [blame] | 152 | |
| 153 | #ifdef CONFIG_DCA |
| 154 | /* cpu for tx queue */ |
| 155 | int cpu; |
| 156 | #endif |
Mallikarjuna R Chilakala | 177db6f | 2008-06-18 15:32:19 -0700 | [diff] [blame^] | 157 | struct net_lro_mgr lro_mgr; |
| 158 | bool lro_used; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 159 | struct ixgbe_queue_stats stats; |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 160 | u8 v_idx; /* maps directly to the index for this ring in the hardware |
| 161 | * vector array, can also be used for finding the bit in EICR |
| 162 | * and friends that represents the vector for this ring */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 163 | |
| 164 | u32 eims_value; |
| 165 | u16 itr_register; |
| 166 | |
| 167 | char name[IFNAMSIZ + 5]; |
| 168 | u16 work_limit; /* max work per interrupt */ |
| 169 | }; |
| 170 | |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 171 | #define RING_F_VMDQ 1 |
| 172 | #define RING_F_RSS 2 |
| 173 | #define IXGBE_MAX_RSS_INDICES 16 |
| 174 | #define IXGBE_MAX_VMDQ_INDICES 16 |
| 175 | struct ixgbe_ring_feature { |
| 176 | int indices; |
| 177 | int mask; |
| 178 | }; |
| 179 | |
| 180 | #define MAX_RX_QUEUES 64 |
| 181 | #define MAX_TX_QUEUES 32 |
| 182 | |
| 183 | /* MAX_MSIX_Q_VECTORS of these are allocated, |
| 184 | * but we only use one per queue-specific vector. |
| 185 | */ |
| 186 | struct ixgbe_q_vector { |
| 187 | struct ixgbe_adapter *adapter; |
| 188 | struct napi_struct napi; |
| 189 | DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */ |
| 190 | DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */ |
| 191 | u8 rxr_count; /* Rx ring count assigned to this vector */ |
| 192 | u8 txr_count; /* Tx ring count assigned to this vector */ |
Ayyappan Veeraiyan | f494e8f | 2008-03-03 15:03:57 -0800 | [diff] [blame] | 193 | u8 tx_eitr; |
| 194 | u8 rx_eitr; |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 195 | u32 eitr; |
| 196 | }; |
| 197 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 198 | /* Helper macros to switch between ints/sec and what the register uses. |
| 199 | * And yes, it's the same math going both ways. |
| 200 | */ |
| 201 | #define EITR_INTS_PER_SEC_TO_REG(_eitr) \ |
| 202 | ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0) |
| 203 | #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG |
| 204 | |
| 205 | #define IXGBE_DESC_UNUSED(R) \ |
| 206 | ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ |
| 207 | (R)->next_to_clean - (R)->next_to_use - 1) |
| 208 | |
| 209 | #define IXGBE_RX_DESC_ADV(R, i) \ |
| 210 | (&(((union ixgbe_adv_rx_desc *)((R).desc))[i])) |
| 211 | #define IXGBE_TX_DESC_ADV(R, i) \ |
| 212 | (&(((union ixgbe_adv_tx_desc *)((R).desc))[i])) |
| 213 | #define IXGBE_TX_CTXTDESC_ADV(R, i) \ |
| 214 | (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i])) |
| 215 | |
| 216 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128 |
| 217 | |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 218 | #define OTHER_VECTOR 1 |
| 219 | #define NON_Q_VECTORS (OTHER_VECTOR) |
| 220 | |
| 221 | #define MAX_MSIX_Q_VECTORS 16 |
| 222 | #define MIN_MSIX_Q_VECTORS 2 |
| 223 | #define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS) |
| 224 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
| 225 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 226 | /* board specific private data structure */ |
| 227 | struct ixgbe_adapter { |
| 228 | struct timer_list watchdog_timer; |
| 229 | struct vlan_group *vlgrp; |
| 230 | u16 bd_number; |
| 231 | u16 rx_buf_len; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 232 | struct work_struct reset_task; |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 233 | struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS]; |
| 234 | char name[MAX_MSIX_COUNT][IFNAMSIZ + 5]; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 235 | |
Ayyappan Veeraiyan | f494e8f | 2008-03-03 15:03:57 -0800 | [diff] [blame] | 236 | /* Interrupt Throttle Rate */ |
| 237 | u32 itr_setting; |
| 238 | u16 eitr_low; |
| 239 | u16 eitr_high; |
| 240 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 241 | /* TX */ |
| 242 | struct ixgbe_ring *tx_ring; /* One per active queue */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 243 | u64 restart_queue; |
| 244 | u64 lsc_int; |
| 245 | u64 hw_tso_ctxt; |
| 246 | u64 hw_tso6_ctxt; |
| 247 | u32 tx_timeout_count; |
| 248 | bool detect_tx_hung; |
| 249 | |
| 250 | /* RX */ |
| 251 | struct ixgbe_ring *rx_ring; /* One per active queue */ |
| 252 | u64 hw_csum_tx_good; |
| 253 | u64 hw_csum_rx_error; |
| 254 | u64 hw_csum_rx_good; |
| 255 | u64 non_eop_descs; |
| 256 | int num_tx_queues; |
| 257 | int num_rx_queues; |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 258 | int num_msix_vectors; |
| 259 | struct ixgbe_ring_feature ring_feature[3]; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 260 | struct msix_entry *msix_entries; |
| 261 | |
| 262 | u64 rx_hdr_split; |
| 263 | u32 alloc_rx_page_failed; |
| 264 | u32 alloc_rx_buff_failed; |
| 265 | |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 266 | /* Some features need tri-state capability, |
| 267 | * thus the additional *_CAPABLE flags. |
| 268 | */ |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 269 | u32 flags; |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 270 | #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1 << 0) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 271 | #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 272 | #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 2) |
| 273 | #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 3) |
| 274 | #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 4) |
| 275 | #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 5) |
| 276 | #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 6) |
| 277 | #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) |
Jeb Cramer | bd0362d | 2008-03-03 15:04:02 -0800 | [diff] [blame] | 278 | #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 279 | |
| 280 | /* OS defined structs */ |
| 281 | struct net_device *netdev; |
| 282 | struct pci_dev *pdev; |
| 283 | struct net_device_stats net_stats; |
| 284 | |
| 285 | /* structs defined in ixgbe_hw.h */ |
| 286 | struct ixgbe_hw hw; |
| 287 | u16 msg_enable; |
| 288 | struct ixgbe_hw_stats stats; |
Ayyappan Veeraiyan | 021230d | 2008-03-03 15:03:45 -0800 | [diff] [blame] | 289 | |
| 290 | /* Interrupt Throttle Rate */ |
| 291 | u32 rx_eitr; |
| 292 | u32 tx_eitr; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 293 | |
| 294 | unsigned long state; |
| 295 | u64 tx_busy; |
Mallikarjuna R Chilakala | 177db6f | 2008-06-18 15:32:19 -0700 | [diff] [blame^] | 296 | u64 lro_aggregated; |
| 297 | u64 lro_flushed; |
| 298 | u64 lro_no_desc; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 299 | }; |
| 300 | |
| 301 | enum ixbge_state_t { |
| 302 | __IXGBE_TESTING, |
| 303 | __IXGBE_RESETTING, |
| 304 | __IXGBE_DOWN |
| 305 | }; |
| 306 | |
| 307 | enum ixgbe_boards { |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 308 | board_82598, |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 309 | }; |
| 310 | |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 311 | extern struct ixgbe_info ixgbe_82598_info; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 312 | |
| 313 | extern char ixgbe_driver_name[]; |
Stephen Hemminger | 9c8eb72 | 2007-10-29 10:46:24 -0700 | [diff] [blame] | 314 | extern const char ixgbe_driver_version[]; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 315 | |
| 316 | extern int ixgbe_up(struct ixgbe_adapter *adapter); |
| 317 | extern void ixgbe_down(struct ixgbe_adapter *adapter); |
Ayyappan Veeraiyan | d4f8088 | 2008-02-01 15:58:41 -0800 | [diff] [blame] | 318 | extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 319 | extern void ixgbe_reset(struct ixgbe_adapter *adapter); |
| 320 | extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); |
| 321 | extern void ixgbe_set_ethtool_ops(struct net_device *netdev); |
| 322 | extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, |
| 323 | struct ixgbe_ring *rxdr); |
| 324 | extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, |
| 325 | struct ixgbe_ring *txdr); |
| 326 | |
| 327 | #endif /* _IXGBE_H_ */ |