H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_PGTABLE_3LEVEL_H |
| 2 | #define _ASM_X86_PGTABLE_3LEVEL_H |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | /* |
| 5 | * Intel Physical Address Extension (PAE) Mode - three-level page |
| 6 | * tables on PPro+ CPUs. |
| 7 | * |
| 8 | * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> |
| 9 | */ |
| 10 | |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 11 | #define pte_ERROR(e) \ |
| 12 | printk("%s:%d: bad pte %p(%08lx%08lx).\n", \ |
| 13 | __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low) |
| 14 | #define pmd_ERROR(e) \ |
| 15 | printk("%s:%d: bad pmd %p(%016Lx).\n", \ |
| 16 | __FILE__, __LINE__, &(e), pmd_val(e)) |
| 17 | #define pgd_ERROR(e) \ |
| 18 | printk("%s:%d: bad pgd %p(%016Lx).\n", \ |
| 19 | __FILE__, __LINE__, &(e), pgd_val(e)) |
Jeremy Fitzhardinge | 6194ba6 | 2008-01-30 13:34:11 +0100 | [diff] [blame] | 20 | |
| 21 | static inline int pud_none(pud_t pud) |
| 22 | { |
| 23 | return pud_val(pud) == 0; |
| 24 | } |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 25 | |
Jeremy Fitzhardinge | 6194ba6 | 2008-01-30 13:34:11 +0100 | [diff] [blame] | 26 | static inline int pud_bad(pud_t pud) |
| 27 | { |
Jeremy Fitzhardinge | 59438c9 | 2008-07-21 22:59:42 -0700 | [diff] [blame] | 28 | return (pud_val(pud) & ~(PTE_PFN_MASK | _KERNPG_TABLE | _PAGE_USER)) != 0; |
Jeremy Fitzhardinge | 6194ba6 | 2008-01-30 13:34:11 +0100 | [diff] [blame] | 29 | } |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 30 | |
Jeremy Fitzhardinge | 6194ba6 | 2008-01-30 13:34:11 +0100 | [diff] [blame] | 31 | static inline int pud_present(pud_t pud) |
| 32 | { |
| 33 | return pud_val(pud) & _PAGE_PRESENT; |
| 34 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | /* Rules for using set_pte: the pte being assigned *must* be |
| 37 | * either not present or in a state where the hardware will |
| 38 | * not attempt to update the pte. In places where this is |
| 39 | * not possible, use pte_get_and_clear to obtain the old pte |
| 40 | * value and then use set_pte to update it. -ben |
| 41 | */ |
Jeremy Fitzhardinge | 3dc494e | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 42 | static inline void native_set_pte(pte_t *ptep, pte_t pte) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | { |
| 44 | ptep->pte_high = pte.pte_high; |
| 45 | smp_wmb(); |
| 46 | ptep->pte_low = pte.pte_low; |
| 47 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | |
Zachary Amsden | d6d861e | 2006-09-30 23:29:36 -0700 | [diff] [blame] | 49 | /* |
| 50 | * Since this is only called on user PTEs, and the page fault handler |
| 51 | * must handle the already racy situation of simultaneous page faults, |
| 52 | * we are justified in merely clearing the PTE present bit, followed |
| 53 | * by a set. The ordering here is important. |
| 54 | */ |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 55 | static inline void native_set_pte_present(struct mm_struct *mm, |
| 56 | unsigned long addr, |
Jeremy Fitzhardinge | 3dc494e | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 57 | pte_t *ptep, pte_t pte) |
Zachary Amsden | d6d861e | 2006-09-30 23:29:36 -0700 | [diff] [blame] | 58 | { |
| 59 | ptep->pte_low = 0; |
| 60 | smp_wmb(); |
| 61 | ptep->pte_high = pte.pte_high; |
| 62 | smp_wmb(); |
| 63 | ptep->pte_low = pte.pte_low; |
| 64 | } |
| 65 | |
Jeremy Fitzhardinge | 3dc494e | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 66 | static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte) |
| 67 | { |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 68 | set_64bit((unsigned long long *)(ptep), native_pte_val(pte)); |
Jeremy Fitzhardinge | 3dc494e | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 69 | } |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 70 | |
Jeremy Fitzhardinge | 3dc494e | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 71 | static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd) |
| 72 | { |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 73 | set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd)); |
Jeremy Fitzhardinge | 3dc494e | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 74 | } |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 75 | |
Jeremy Fitzhardinge | 3dc494e | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 76 | static inline void native_set_pud(pud_t *pudp, pud_t pud) |
| 77 | { |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 78 | set_64bit((unsigned long long *)(pudp), native_pud_val(pud)); |
Jeremy Fitzhardinge | 3dc494e | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 79 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 80 | |
| 81 | /* |
Zachary Amsden | 6e5882c | 2006-04-27 11:32:29 -0700 | [diff] [blame] | 82 | * For PTEs and PDEs, we must clear the P-bit first when clearing a page table |
| 83 | * entry, so clear the bottom half first and enforce ordering with a compiler |
| 84 | * barrier. |
| 85 | */ |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 86 | static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, |
| 87 | pte_t *ptep) |
Zachary Amsden | 6e5882c | 2006-04-27 11:32:29 -0700 | [diff] [blame] | 88 | { |
| 89 | ptep->pte_low = 0; |
| 90 | smp_wmb(); |
| 91 | ptep->pte_high = 0; |
| 92 | } |
| 93 | |
Jeremy Fitzhardinge | 3dc494e | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 94 | static inline void native_pmd_clear(pmd_t *pmd) |
Zachary Amsden | 6e5882c | 2006-04-27 11:32:29 -0700 | [diff] [blame] | 95 | { |
| 96 | u32 *tmp = (u32 *)pmd; |
| 97 | *tmp = 0; |
| 98 | smp_wmb(); |
| 99 | *(tmp + 1) = 0; |
| 100 | } |
Jeremy Fitzhardinge | 3dc494e | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 101 | |
Jeremy Fitzhardinge | 6194ba6 | 2008-01-30 13:34:11 +0100 | [diff] [blame] | 102 | static inline void pud_clear(pud_t *pudp) |
| 103 | { |
Jeremy Fitzhardinge | edd6bcd | 2008-02-04 16:48:02 +0100 | [diff] [blame] | 104 | unsigned long pgd; |
| 105 | |
Jeremy Fitzhardinge | 6194ba6 | 2008-01-30 13:34:11 +0100 | [diff] [blame] | 106 | set_pud(pudp, __pud(0)); |
| 107 | |
| 108 | /* |
Jeremy Fitzhardinge | f5430f9 | 2008-02-04 16:48:02 +0100 | [diff] [blame] | 109 | * According to Intel App note "TLBs, Paging-Structure Caches, |
| 110 | * and Their Invalidation", April 2007, document 317080-001, |
| 111 | * section 8.1: in PAE mode we explicitly have to flush the |
| 112 | * TLB via cr3 if the top-level pgd is changed... |
Jeremy Fitzhardinge | 6194ba6 | 2008-01-30 13:34:11 +0100 | [diff] [blame] | 113 | * |
Jeremy Fitzhardinge | edd6bcd | 2008-02-04 16:48:02 +0100 | [diff] [blame] | 114 | * Make sure the pud entry we're updating is within the |
| 115 | * current pgd to avoid unnecessary TLB flushes. |
Jeremy Fitzhardinge | 6194ba6 | 2008-01-30 13:34:11 +0100 | [diff] [blame] | 116 | */ |
Jeremy Fitzhardinge | edd6bcd | 2008-02-04 16:48:02 +0100 | [diff] [blame] | 117 | pgd = read_cr3(); |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 118 | if (__pa(pudp) >= pgd && __pa(pudp) < |
| 119 | (pgd + sizeof(pgd_t)*PTRS_PER_PGD)) |
Jeremy Fitzhardinge | edd6bcd | 2008-02-04 16:48:02 +0100 | [diff] [blame] | 120 | write_cr3(pgd); |
Jeremy Fitzhardinge | 6194ba6 | 2008-01-30 13:34:11 +0100 | [diff] [blame] | 121 | } |
Rusty Russell | da181a8 | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 122 | |
Jan Beulich | ab00fee | 2008-10-30 10:37:21 +0000 | [diff] [blame] | 123 | #define pud_page(pud) pfn_to_page(pud_val(pud) >> PAGE_SHIFT) |
Rusty Russell | da181a8 | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 124 | |
Jeremy Fitzhardinge | 59438c9 | 2008-07-21 22:59:42 -0700 | [diff] [blame] | 125 | #define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PTE_PFN_MASK)) |
Rusty Russell | da181a8 | 2006-12-07 02:14:08 +0100 | [diff] [blame] | 126 | |
| 127 | |
| 128 | /* Find an entry in the second-level page table.. */ |
Jan Beulich | ab00fee | 2008-10-30 10:37:21 +0000 | [diff] [blame] | 129 | #define pmd_offset(pud, address) ((pmd_t *)pud_page_vaddr(*(pud)) + \ |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 130 | pmd_index(address)) |
Zachary Amsden | 6e5882c | 2006-04-27 11:32:29 -0700 | [diff] [blame] | 131 | |
Zachary Amsden | 142dd97 | 2007-05-02 19:27:19 +0200 | [diff] [blame] | 132 | #ifdef CONFIG_SMP |
Jeremy Fitzhardinge | 3dc494e | 2007-05-02 19:27:13 +0200 | [diff] [blame] | 133 | static inline pte_t native_ptep_get_and_clear(pte_t *ptep) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 134 | { |
| 135 | pte_t res; |
| 136 | |
| 137 | /* xchg acts as a barrier before the setting of the high bits */ |
| 138 | res.pte_low = xchg(&ptep->pte_low, 0); |
| 139 | res.pte_high = ptep->pte_high; |
| 140 | ptep->pte_high = 0; |
| 141 | |
| 142 | return res; |
| 143 | } |
Zachary Amsden | 142dd97 | 2007-05-02 19:27:19 +0200 | [diff] [blame] | 144 | #else |
| 145 | #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp) |
| 146 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | |
Rusty Russell | 6049742 | 2006-09-25 23:32:30 -0700 | [diff] [blame] | 148 | #define __HAVE_ARCH_PTE_SAME |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | static inline int pte_same(pte_t a, pte_t b) |
| 150 | { |
| 151 | return a.pte_low == b.pte_low && a.pte_high == b.pte_high; |
| 152 | } |
| 153 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | static inline int pte_none(pte_t pte) |
| 155 | { |
| 156 | return !pte.pte_low && !pte.pte_high; |
| 157 | } |
| 158 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | /* |
| 160 | * Bits 0, 6 and 7 are taken in the low part of the pte, |
| 161 | * put the 32 bits of offset into the high part. |
| 162 | */ |
| 163 | #define pte_to_pgoff(pte) ((pte).pte_high) |
Joe Perches | 4b01fef | 2008-03-23 01:03:10 -0700 | [diff] [blame] | 164 | #define pgoff_to_pte(off) \ |
| 165 | ((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } }) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | #define PTE_FILE_MAX_BITS 32 |
| 167 | |
| 168 | /* Encode and de-code a swap entry */ |
Jan Beulich | 1796316 | 2008-12-16 11:35:24 +0000 | [diff] [blame^] | 169 | #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | #define __swp_type(x) (((x).val) & 0x1f) |
| 171 | #define __swp_offset(x) ((x).val >> 5) |
| 172 | #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5}) |
| 173 | #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high }) |
Jeremy Fitzhardinge | c8e5393 | 2008-01-30 13:32:57 +0100 | [diff] [blame] | 174 | #define __swp_entry_to_pte(x) ((pte_t){ { .pte_high = (x).val } }) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 176 | #endif /* _ASM_X86_PGTABLE_3LEVEL_H */ |