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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef __TRID4DWAVE_H
2#define __TRID4DWAVE_H
3
4/*
5 * audio@tridentmicro.com
6 * Fri Feb 19 15:55:28 MST 1999
7 * Definitions for Trident 4DWave DX/NX chips
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 */
25
26/* PCI vendor and device ID */
27#ifndef PCI_VENDOR_ID_TRIDENT
28#define PCI_VENDOR_ID_TRIDENT 0x1023
29#endif
30
31#ifndef PCI_VENDOR_ID_SI
32#define PCI_VENDOR_ID_SI 0x1039
33#endif
34
35#ifndef PCI_VENDOR_ID_ALI
36#define PCI_VENDOR_ID_ALI 0x10b9
37#endif
38
39#ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_DX
40#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
41#endif
42
43#ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_NX
44#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
45#endif
46
47#ifndef PCI_DEVICE_ID_SI_7018
48#define PCI_DEVICE_ID_SI_7018 0x7018
49#endif
50
51#ifndef PCI_DEVICE_ID_ALI_5451
52#define PCI_DEVICE_ID_ALI_5451 0x5451
53#endif
54
55#ifndef PCI_DEVICE_ID_ALI_1533
56#define PCI_DEVICE_ID_ALI_1533 0x1533
57#endif
58
59#define CHANNEL_REGS 5
60#define CHANNEL_START 0xe0 // The first bytes of the contiguous register space.
61
62#define BANK_A 0
63#define BANK_B 1
64#define NR_BANKS 2
65
66#define TRIDENT_FMT_STEREO 0x01
67#define TRIDENT_FMT_16BIT 0x02
68#define TRIDENT_FMT_MASK 0x03
69
70#define DAC_RUNNING 0x01
71#define ADC_RUNNING 0x02
72
73/* Register Addresses */
74
75/* operational registers common to DX, NX, 7018 */
76enum trident_op_registers {
77 T4D_GAME_CR = 0x30, T4D_GAME_LEG = 0x31,
78 T4D_GAME_AXD = 0x34,
79 T4D_REC_CH = 0x70,
80 T4D_START_A = 0x80, T4D_STOP_A = 0x84,
81 T4D_DLY_A = 0x88, T4D_SIGN_CSO_A = 0x8c,
82 T4D_CSPF_A = 0x90, T4D_CEBC_A = 0x94,
83 T4D_AINT_A = 0x98, T4D_EINT_A = 0x9c,
84 T4D_LFO_GC_CIR = 0xa0, T4D_AINTEN_A = 0xa4,
85 T4D_MUSICVOL_WAVEVOL = 0xa8, T4D_SBDELTA_DELTA_R = 0xac,
86 T4D_MISCINT = 0xb0, T4D_START_B = 0xb4,
87 T4D_STOP_B = 0xb8, T4D_CSPF_B = 0xbc,
88 T4D_SBBL_SBCL = 0xc0, T4D_SBCTRL_SBE2R_SBDD = 0xc4,
89 T4D_STIMER = 0xc8, T4D_LFO_B_I2S_DELTA = 0xcc,
90 T4D_AINT_B = 0xd8, T4D_AINTEN_B = 0xdc,
91 ALI_MPUR2 = 0x22, ALI_GPIO = 0x7c,
92 ALI_EBUF1 = 0xf4,
93 ALI_EBUF2 = 0xf8
94};
95
96enum ali_op_registers {
97 ALI_SCTRL = 0x48,
98 ALI_GLOBAL_CONTROL = 0xd4,
99 ALI_STIMER = 0xc8,
100 ALI_SPDIF_CS = 0x70,
101 ALI_SPDIF_CTRL = 0x74
102};
103
104enum ali_registers_number {
105 ALI_GLOBAL_REGS = 56,
106 ALI_CHANNEL_REGS = 8,
107 ALI_MIXER_REGS = 20
108};
109
110enum ali_sctrl_control_bit {
111 ALI_SPDIF_OUT_ENABLE = 0x20
112};
113
114enum ali_global_control_bit {
115 ALI_SPDIF_OUT_SEL_PCM = 0x00000400,
116 ALI_SPDIF_IN_SUPPORT = 0x00000800,
117 ALI_SPDIF_OUT_CH_ENABLE = 0x00008000,
118 ALI_SPDIF_IN_CH_ENABLE = 0x00080000,
119 ALI_PCM_IN_DISABLE = 0x7fffffff,
120 ALI_PCM_IN_ENABLE = 0x80000000,
121 ALI_SPDIF_IN_CH_DISABLE = 0xfff7ffff,
122 ALI_SPDIF_OUT_CH_DISABLE = 0xffff7fff,
123 ALI_SPDIF_OUT_SEL_SPDIF = 0xfffffbff
124
125};
126
127enum ali_spdif_control_bit {
128 ALI_SPDIF_IN_FUNC_ENABLE = 0x02,
129 ALI_SPDIF_IN_CH_STATUS = 0x40,
130 ALI_SPDIF_OUT_CH_STATUS = 0xbf
131
132};
133
134enum ali_control_all {
135 ALI_DISABLE_ALL_IRQ = 0,
136 ALI_CHANNELS = 32,
137 ALI_STOP_ALL_CHANNELS = 0xffffffff,
138 ALI_MULTI_CHANNELS_START_STOP = 0x07800000
139};
140
141enum ali_EMOD_control_bit {
142 ALI_EMOD_DEC = 0x00000000,
143 ALI_EMOD_INC = 0x10000000,
144 ALI_EMOD_Delay = 0x20000000,
145 ALI_EMOD_Still = 0x30000000
146};
147
148enum ali_pcm_in_channel_num {
149 ALI_NORMAL_CHANNEL = 0,
150 ALI_SPDIF_OUT_CHANNEL = 15,
151 ALI_SPDIF_IN_CHANNEL = 19,
152 ALI_LEF_CHANNEL = 23,
153 ALI_CENTER_CHANNEL = 24,
154 ALI_SURR_RIGHT_CHANNEL = 25,
155 ALI_SURR_LEFT_CHANNEL = 26,
156 ALI_PCM_IN_CHANNEL = 31
157};
158
159enum ali_pcm_out_channel_num {
160 ALI_PCM_OUT_CHANNEL_FIRST = 0,
161 ALI_PCM_OUT_CHANNEL_LAST = 31
162};
163
164enum ali_ac97_power_control_bit {
165 ALI_EAPD_POWER_DOWN = 0x8000
166};
167
168enum ali_update_ptr_flags {
169 ALI_ADDRESS_INT_UPDATE = 0x01
170};
171
172enum ali_revision {
173 ALI_5451_V02 = 0x02
174};
175
176enum ali_spdif_out_control {
177 ALI_PCM_TO_SPDIF_OUT = 0,
178 ALI_SPDIF_OUT_TO_SPDIF_OUT = 1,
179 ALI_SPDIF_OUT_PCM = 0,
180 ALI_SPDIF_OUT_NON_PCM = 2
181};
182
183/* S/PDIF Operational Registers for 4D-NX */
184enum nx_spdif_registers {
185 NX_SPCTRL_SPCSO = 0x24, NX_SPLBA = 0x28,
186 NX_SPESO = 0x2c, NX_SPCSTATUS = 0x64
187};
188
189/* OP registers to access each hardware channel */
190enum channel_registers {
191 CH_DX_CSO_ALPHA_FMS = 0xe0, CH_DX_ESO_DELTA = 0xe8,
192 CH_DX_FMC_RVOL_CVOL = 0xec,
193 CH_NX_DELTA_CSO = 0xe0, CH_NX_DELTA_ESO = 0xe8,
194 CH_NX_ALPHA_FMS_FMC_RVOL_CVOL = 0xec,
195 CH_LBA = 0xe4,
196 CH_GVSEL_PAN_VOL_CTRL_EC = 0xf0
197};
198
199/* registers to read/write/control AC97 codec */
200enum dx_ac97_registers {
201 DX_ACR0_AC97_W = 0x40, DX_ACR1_AC97_R = 0x44,
202 DX_ACR2_AC97_COM_STAT = 0x48
203};
204
205enum nx_ac97_registers {
206 NX_ACR0_AC97_COM_STAT = 0x40, NX_ACR1_AC97_W = 0x44,
207 NX_ACR2_AC97_R_PRIMARY = 0x48, NX_ACR3_AC97_R_SECONDARY = 0x4c
208};
209
210enum si_ac97_registers {
211 SI_AC97_WRITE = 0x40, SI_AC97_READ = 0x44,
212 SI_SERIAL_INTF_CTRL = 0x48, SI_AC97_GPIO = 0x4c
213};
214
215enum ali_ac97_registers {
216 ALI_AC97_WRITE = 0x40, ALI_AC97_READ = 0x44
217};
218
219/* Bit mask for operational registers */
220#define AC97_REG_ADDR 0x000000ff
221
222enum ali_ac97_bits {
223 ALI_AC97_BUSY_WRITE = 0x8000, ALI_AC97_BUSY_READ = 0x8000,
224 ALI_AC97_WRITE_ACTION = 0x8000, ALI_AC97_READ_ACTION = 0x8000,
225 ALI_AC97_AUDIO_BUSY = 0x4000, ALI_AC97_SECONDARY = 0x0080,
226 ALI_AC97_READ_MIXER_REGISTER = 0xfeff,
227 ALI_AC97_WRITE_MIXER_REGISTER = 0x0100
228};
229
230enum sis7018_ac97_bits {
231 SI_AC97_BUSY_WRITE = 0x8000, SI_AC97_BUSY_READ = 0x8000,
232 SI_AC97_AUDIO_BUSY = 0x4000, SI_AC97_MODEM_BUSY = 0x2000,
233 SI_AC97_SECONDARY = 0x0080
234};
235
236enum trident_dx_ac97_bits {
237 DX_AC97_BUSY_WRITE = 0x8000, DX_AC97_BUSY_READ = 0x8000,
238 DX_AC97_READY = 0x0010, DX_AC97_RECORD = 0x0008,
239 DX_AC97_PLAYBACK = 0x0002
240};
241
242enum trident_nx_ac97_bits {
243 /* ACR1-3 */
244 NX_AC97_BUSY_WRITE = 0x0800, NX_AC97_BUSY_READ = 0x0800,
245 NX_AC97_BUSY_DATA = 0x0400, NX_AC97_WRITE_SECONDARY = 0x0100,
246 /* ACR0 */
247 NX_AC97_SECONDARY_READY = 0x0040, NX_AC97_SECONDARY_RECORD = 0x0020,
248 NX_AC97_SURROUND_OUTPUT = 0x0010,
249 NX_AC97_PRIMARY_READY = 0x0008, NX_AC97_PRIMARY_RECORD = 0x0004,
250 NX_AC97_PCM_OUTPUT = 0x0002,
251 NX_AC97_WARM_RESET = 0x0001
252};
253
254enum serial_intf_ctrl_bits {
255 WARM_REST = 0x00000001, COLD_RESET = 0x00000002,
256 I2S_CLOCK = 0x00000004, PCM_SEC_AC97= 0x00000008,
257 AC97_DBL_RATE = 0x00000010, SPDIF_EN = 0x00000020,
258 I2S_OUTPUT_EN = 0x00000040, I2S_INPUT_EN = 0x00000080,
259 PCMIN = 0x00000100, LINE1IN = 0x00000200,
260 MICIN = 0x00000400, LINE2IN = 0x00000800,
261 HEAD_SET_IN = 0x00001000, GPIOIN = 0x00002000,
262 /* 7018 spec says id = 01 but the demo board routed to 10
263 SECONDARY_ID= 0x00004000, */
264 SECONDARY_ID= 0x00004000,
265 PCMOUT = 0x00010000, SURROUT = 0x00020000,
266 CENTEROUT = 0x00040000, LFEOUT = 0x00080000,
267 LINE1OUT = 0x00100000, LINE2OUT = 0x00200000,
268 GPIOOUT = 0x00400000,
269 SI_AC97_PRIMARY_READY = 0x01000000,
270 SI_AC97_SECONDARY_READY = 0x02000000,
271};
272
273enum global_control_bits {
274 CHANNLE_IDX = 0x0000003f, PB_RESET = 0x00000100,
275 PAUSE_ENG = 0x00000200,
276 OVERRUN_IE = 0x00000400, UNDERRUN_IE = 0x00000800,
277 ENDLP_IE = 0x00001000, MIDLP_IE = 0x00002000,
278 ETOG_IE = 0x00004000,
279 EDROP_IE = 0x00008000, BANK_B_EN = 0x00010000
280};
281
282enum channel_control_bits {
283 CHANNEL_LOOP = 0x00001000, CHANNEL_SIGNED = 0x00002000,
284 CHANNEL_STEREO = 0x00004000, CHANNEL_16BITS = 0x00008000,
285};
286
287enum channel_attribute {
288 /* playback/record select */
289 CHANNEL_PB = 0x0000, CHANNEL_SPC_PB = 0x4000,
290 CHANNEL_REC = 0x8000, CHANNEL_REC_PB = 0xc000,
291 /* playback destination/record source select */
292 MODEM_LINE1 = 0x0000, MODEM_LINE2 = 0x0400,
293 PCM_LR = 0x0800, HSET = 0x0c00,
294 I2S_LR = 0x1000, CENTER_LFE = 0x1400,
295 SURR_LR = 0x1800, SPDIF_LR = 0x1c00,
296 MIC = 0x1400,
297 /* mist stuff */
298 MONO_LEFT = 0x0000, MONO_RIGHT = 0x0100,
299 MONO_MIX = 0x0200, SRC_ENABLE = 0x0080,
300};
301
302enum miscint_bits {
303 PB_UNDERRUN_IRO = 0x00000001, REC_OVERRUN_IRQ = 0x00000002,
304 SB_IRQ = 0x00000004, MPU401_IRQ = 0x00000008,
305 OPL3_IRQ = 0x00000010, ADDRESS_IRQ = 0x00000020,
306 ENVELOPE_IRQ = 0x00000040, ST_IRQ = 0x00000080,
307 PB_UNDERRUN = 0x00000100, REC_OVERRUN = 0x00000200,
308 MIXER_UNDERFLOW = 0x00000400, MIXER_OVERFLOW = 0x00000800,
309 ST_TARGET_REACHED = 0x00008000, PB_24K_MODE = 0x00010000,
310 ST_IRQ_EN = 0x00800000, ACGPIO_IRQ = 0x01000000
311};
312
313#define TRID_REG( trident, x ) ( (trident) -> iobase + (x) )
314
315#define CYBER_PORT_AUDIO 0x3CE
316#define CYBER_IDX_AUDIO_ENABLE 0x7B
317#define CYBER_BMSK_AUDIO_INT_ENABLE 0x09
318#define CYBER_BMSK_AUENZ 0x01
319#define CYBER_BMSK_AUENZ_ENABLE 0x00
320#define CYBER_IDX_IRQ_ENABLE 0x12
321
322#define VALIDATE_MAGIC(FOO,MAG) \
323({ \
324 if (!(FOO) || (FOO)->magic != MAG) { \
325 printk(invalid_magic,__FUNCTION__); \
326 return -ENXIO; \
327 } \
328})
329
330#define VALIDATE_STATE(a) VALIDATE_MAGIC(a,TRIDENT_STATE_MAGIC)
331#define VALIDATE_CARD(a) VALIDATE_MAGIC(a,TRIDENT_CARD_MAGIC)
332
333static inline unsigned ld2(unsigned int x)
334{
335 unsigned r = 0;
336
337 if (x >= 0x10000) {
338 x >>= 16;
339 r += 16;
340 }
341 if (x >= 0x100) {
342 x >>= 8;
343 r += 8;
344 }
345 if (x >= 0x10) {
346 x >>= 4;
347 r += 4;
348 }
349 if (x >= 4) {
350 x >>= 2;
351 r += 2;
352 }
353 if (x >= 2)
354 r++;
355 return r;
356}
357
358#endif /* __TRID4DWAVE_H */