Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Driver for Intel I82092AA PCI-PCMCIA bridge. |
| 3 | * |
| 4 | * (C) 2001 Red Hat, Inc. |
| 5 | * |
| 6 | * Author: Arjan Van De Ven <arjanv@redhat.com> |
| 7 | * Loosly based on i82365.c from the pcmcia-cs package |
| 8 | * |
| 9 | * $Id: i82092aa.c,v 1.2 2001/10/23 14:43:34 arjanv Exp $ |
| 10 | */ |
| 11 | |
| 12 | #include <linux/kernel.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <linux/module.h> |
| 14 | #include <linux/pci.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/workqueue.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/device.h> |
| 19 | |
| 20 | #include <pcmcia/cs_types.h> |
| 21 | #include <pcmcia/ss.h> |
| 22 | #include <pcmcia/cs.h> |
| 23 | |
| 24 | #include <asm/system.h> |
| 25 | #include <asm/io.h> |
| 26 | |
| 27 | #include "i82092aa.h" |
| 28 | #include "i82365.h" |
| 29 | |
| 30 | MODULE_LICENSE("GPL"); |
| 31 | |
| 32 | /* PCI core routines */ |
| 33 | static struct pci_device_id i82092aa_pci_ids[] = { |
| 34 | { |
| 35 | .vendor = PCI_VENDOR_ID_INTEL, |
| 36 | .device = PCI_DEVICE_ID_INTEL_82092AA_0, |
| 37 | .subvendor = PCI_ANY_ID, |
| 38 | .subdevice = PCI_ANY_ID, |
| 39 | }, |
| 40 | {} |
| 41 | }; |
| 42 | MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids); |
| 43 | |
| 44 | static int i82092aa_socket_suspend (struct pci_dev *dev, pm_message_t state) |
| 45 | { |
| 46 | return pcmcia_socket_dev_suspend(&dev->dev, state); |
| 47 | } |
| 48 | |
| 49 | static int i82092aa_socket_resume (struct pci_dev *dev) |
| 50 | { |
| 51 | return pcmcia_socket_dev_resume(&dev->dev); |
| 52 | } |
| 53 | |
| 54 | static struct pci_driver i82092aa_pci_drv = { |
| 55 | .name = "i82092aa", |
| 56 | .id_table = i82092aa_pci_ids, |
| 57 | .probe = i82092aa_pci_probe, |
| 58 | .remove = __devexit_p(i82092aa_pci_remove), |
| 59 | .suspend = i82092aa_socket_suspend, |
| 60 | .resume = i82092aa_socket_resume, |
| 61 | }; |
| 62 | |
| 63 | |
| 64 | /* the pccard structure and its functions */ |
| 65 | static struct pccard_operations i82092aa_operations = { |
| 66 | .init = i82092aa_init, |
| 67 | .get_status = i82092aa_get_status, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | .set_socket = i82092aa_set_socket, |
| 69 | .set_io_map = i82092aa_set_io_map, |
| 70 | .set_mem_map = i82092aa_set_mem_map, |
| 71 | }; |
| 72 | |
| 73 | /* The card can do upto 4 sockets, allocate a structure for each of them */ |
| 74 | |
| 75 | struct socket_info { |
| 76 | int number; |
| 77 | int card_state; /* 0 = no socket, |
| 78 | 1 = empty socket, |
| 79 | 2 = card but not initialized, |
| 80 | 3 = operational card */ |
| 81 | kio_addr_t io_base; /* base io address of the socket */ |
| 82 | |
| 83 | struct pcmcia_socket socket; |
| 84 | struct pci_dev *dev; /* The PCI device for the socket */ |
| 85 | }; |
| 86 | |
| 87 | #define MAX_SOCKETS 4 |
| 88 | static struct socket_info sockets[MAX_SOCKETS]; |
| 89 | static int socket_count; /* shortcut */ |
| 90 | |
| 91 | |
| 92 | static int __devinit i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) |
| 93 | { |
| 94 | unsigned char configbyte; |
| 95 | int i, ret; |
| 96 | |
| 97 | enter("i82092aa_pci_probe"); |
| 98 | |
| 99 | if ((ret = pci_enable_device(dev))) |
| 100 | return ret; |
| 101 | |
| 102 | pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */ |
| 103 | switch(configbyte&6) { |
| 104 | case 0: |
| 105 | socket_count = 2; |
| 106 | break; |
| 107 | case 2: |
| 108 | socket_count = 1; |
| 109 | break; |
| 110 | case 4: |
| 111 | case 6: |
| 112 | socket_count = 4; |
| 113 | break; |
| 114 | |
| 115 | default: |
| 116 | printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n"); |
| 117 | ret = -EIO; |
| 118 | goto err_out_disable; |
| 119 | } |
| 120 | printk(KERN_INFO "i82092aa: configured as a %d socket device.\n", socket_count); |
| 121 | |
| 122 | if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) { |
| 123 | ret = -EBUSY; |
| 124 | goto err_out_disable; |
| 125 | } |
| 126 | |
| 127 | for (i = 0;i<socket_count;i++) { |
| 128 | sockets[i].card_state = 1; /* 1 = present but empty */ |
| 129 | sockets[i].io_base = pci_resource_start(dev, 0); |
| 130 | sockets[i].socket.features |= SS_CAP_PCCARD; |
| 131 | sockets[i].socket.map_size = 0x1000; |
| 132 | sockets[i].socket.irq_mask = 0; |
| 133 | sockets[i].socket.pci_irq = dev->irq; |
| 134 | sockets[i].socket.owner = THIS_MODULE; |
| 135 | |
| 136 | sockets[i].number = i; |
| 137 | |
| 138 | if (card_present(i)) { |
| 139 | sockets[i].card_state = 3; |
| 140 | dprintk(KERN_DEBUG "i82092aa: slot %i is occupied\n",i); |
| 141 | } else { |
| 142 | dprintk(KERN_DEBUG "i82092aa: slot %i is vacant\n",i); |
| 143 | } |
| 144 | } |
| 145 | |
| 146 | /* Now, specifiy that all interrupts are to be done as PCI interrupts */ |
| 147 | configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */ |
| 148 | pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */ |
| 149 | |
| 150 | /* Register the interrupt handler */ |
| 151 | dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq); |
Thomas Gleixner | dace145 | 2006-07-01 19:29:38 -0700 | [diff] [blame] | 152 | if ((ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, "i82092aa", i82092aa_interrupt))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq); |
| 154 | goto err_out_free_res; |
| 155 | } |
| 156 | |
| 157 | pci_set_drvdata(dev, &sockets[i].socket); |
| 158 | |
| 159 | for (i = 0; i<socket_count; i++) { |
| 160 | sockets[i].socket.dev.dev = &dev->dev; |
| 161 | sockets[i].socket.ops = &i82092aa_operations; |
| 162 | sockets[i].socket.resource_ops = &pccard_nonstatic_ops; |
| 163 | ret = pcmcia_register_socket(&sockets[i].socket); |
| 164 | if (ret) { |
| 165 | goto err_out_free_sockets; |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | leave("i82092aa_pci_probe"); |
| 170 | return 0; |
| 171 | |
| 172 | err_out_free_sockets: |
| 173 | if (i) { |
| 174 | for (i--;i>=0;i--) { |
| 175 | pcmcia_unregister_socket(&sockets[i].socket); |
| 176 | } |
| 177 | } |
| 178 | free_irq(dev->irq, i82092aa_interrupt); |
| 179 | err_out_free_res: |
| 180 | release_region(pci_resource_start(dev, 0), 2); |
| 181 | err_out_disable: |
| 182 | pci_disable_device(dev); |
| 183 | return ret; |
| 184 | } |
| 185 | |
| 186 | static void __devexit i82092aa_pci_remove(struct pci_dev *dev) |
| 187 | { |
| 188 | struct pcmcia_socket *socket = pci_get_drvdata(dev); |
| 189 | |
| 190 | enter("i82092aa_pci_remove"); |
| 191 | |
| 192 | free_irq(dev->irq, i82092aa_interrupt); |
| 193 | |
| 194 | if (socket) |
| 195 | pcmcia_unregister_socket(socket); |
| 196 | |
| 197 | leave("i82092aa_pci_remove"); |
| 198 | } |
| 199 | |
| 200 | static DEFINE_SPINLOCK(port_lock); |
| 201 | |
| 202 | /* basic value read/write functions */ |
| 203 | |
| 204 | static unsigned char indirect_read(int socket, unsigned short reg) |
| 205 | { |
| 206 | unsigned short int port; |
| 207 | unsigned char val; |
| 208 | unsigned long flags; |
| 209 | spin_lock_irqsave(&port_lock,flags); |
| 210 | reg += socket * 0x40; |
| 211 | port = sockets[socket].io_base; |
| 212 | outb(reg,port); |
| 213 | val = inb(port+1); |
| 214 | spin_unlock_irqrestore(&port_lock,flags); |
| 215 | return val; |
| 216 | } |
| 217 | |
| 218 | #if 0 |
| 219 | static unsigned short indirect_read16(int socket, unsigned short reg) |
| 220 | { |
| 221 | unsigned short int port; |
| 222 | unsigned short tmp; |
| 223 | unsigned long flags; |
| 224 | spin_lock_irqsave(&port_lock,flags); |
| 225 | reg = reg + socket * 0x40; |
| 226 | port = sockets[socket].io_base; |
| 227 | outb(reg,port); |
| 228 | tmp = inb(port+1); |
| 229 | reg++; |
| 230 | outb(reg,port); |
| 231 | tmp = tmp | (inb(port+1)<<8); |
| 232 | spin_unlock_irqrestore(&port_lock,flags); |
| 233 | return tmp; |
| 234 | } |
| 235 | #endif |
| 236 | |
| 237 | static void indirect_write(int socket, unsigned short reg, unsigned char value) |
| 238 | { |
| 239 | unsigned short int port; |
| 240 | unsigned long flags; |
| 241 | spin_lock_irqsave(&port_lock,flags); |
| 242 | reg = reg + socket * 0x40; |
| 243 | port = sockets[socket].io_base; |
| 244 | outb(reg,port); |
| 245 | outb(value,port+1); |
| 246 | spin_unlock_irqrestore(&port_lock,flags); |
| 247 | } |
| 248 | |
| 249 | static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) |
| 250 | { |
| 251 | unsigned short int port; |
| 252 | unsigned char val; |
| 253 | unsigned long flags; |
| 254 | spin_lock_irqsave(&port_lock,flags); |
| 255 | reg = reg + socket * 0x40; |
| 256 | port = sockets[socket].io_base; |
| 257 | outb(reg,port); |
| 258 | val = inb(port+1); |
| 259 | val |= mask; |
| 260 | outb(reg,port); |
| 261 | outb(val,port+1); |
| 262 | spin_unlock_irqrestore(&port_lock,flags); |
| 263 | } |
| 264 | |
| 265 | |
| 266 | static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask) |
| 267 | { |
| 268 | unsigned short int port; |
| 269 | unsigned char val; |
| 270 | unsigned long flags; |
| 271 | spin_lock_irqsave(&port_lock,flags); |
| 272 | reg = reg + socket * 0x40; |
| 273 | port = sockets[socket].io_base; |
| 274 | outb(reg,port); |
| 275 | val = inb(port+1); |
| 276 | val &= ~mask; |
| 277 | outb(reg,port); |
| 278 | outb(val,port+1); |
| 279 | spin_unlock_irqrestore(&port_lock,flags); |
| 280 | } |
| 281 | |
| 282 | static void indirect_write16(int socket, unsigned short reg, unsigned short value) |
| 283 | { |
| 284 | unsigned short int port; |
| 285 | unsigned char val; |
| 286 | unsigned long flags; |
| 287 | spin_lock_irqsave(&port_lock,flags); |
| 288 | reg = reg + socket * 0x40; |
| 289 | port = sockets[socket].io_base; |
| 290 | |
| 291 | outb(reg,port); |
| 292 | val = value & 255; |
| 293 | outb(val,port+1); |
| 294 | |
| 295 | reg++; |
| 296 | |
| 297 | outb(reg,port); |
| 298 | val = value>>8; |
| 299 | outb(val,port+1); |
| 300 | spin_unlock_irqrestore(&port_lock,flags); |
| 301 | } |
| 302 | |
| 303 | /* simple helper functions */ |
| 304 | /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ |
| 305 | static int cycle_time = 120; |
| 306 | |
| 307 | static int to_cycles(int ns) |
| 308 | { |
| 309 | if (cycle_time!=0) |
| 310 | return ns/cycle_time; |
| 311 | else |
| 312 | return 0; |
| 313 | } |
| 314 | |
| 315 | |
| 316 | /* Interrupt handler functionality */ |
| 317 | |
| 318 | static irqreturn_t i82092aa_interrupt(int irq, void *dev, struct pt_regs *regs) |
| 319 | { |
| 320 | int i; |
| 321 | int loopcount = 0; |
| 322 | int handled = 0; |
| 323 | |
| 324 | unsigned int events, active=0; |
| 325 | |
| 326 | /* enter("i82092aa_interrupt");*/ |
| 327 | |
| 328 | while (1) { |
| 329 | loopcount++; |
| 330 | if (loopcount>20) { |
| 331 | printk(KERN_ERR "i82092aa: infinite eventloop in interrupt \n"); |
| 332 | break; |
| 333 | } |
| 334 | |
| 335 | active = 0; |
| 336 | |
| 337 | for (i=0;i<socket_count;i++) { |
| 338 | int csc; |
| 339 | if (sockets[i].card_state==0) /* Inactive socket, should not happen */ |
| 340 | continue; |
| 341 | |
| 342 | csc = indirect_read(i,I365_CSC); /* card status change register */ |
| 343 | |
| 344 | if (csc==0) /* no events on this socket */ |
| 345 | continue; |
| 346 | handled = 1; |
| 347 | events = 0; |
| 348 | |
| 349 | if (csc & I365_CSC_DETECT) { |
| 350 | events |= SS_DETECT; |
| 351 | printk("Card detected in socket %i!\n",i); |
| 352 | } |
| 353 | |
| 354 | if (indirect_read(i,I365_INTCTL) & I365_PC_IOCARD) { |
| 355 | /* For IO/CARDS, bit 0 means "read the card" */ |
| 356 | events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; |
| 357 | } else { |
| 358 | /* Check for battery/ready events */ |
| 359 | events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; |
| 360 | events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; |
| 361 | events |= (csc & I365_CSC_READY) ? SS_READY : 0; |
| 362 | } |
| 363 | |
| 364 | if (events) { |
| 365 | pcmcia_parse_events(&sockets[i].socket, events); |
| 366 | } |
| 367 | active |= events; |
| 368 | } |
| 369 | |
| 370 | if (active==0) /* no more events to handle */ |
| 371 | break; |
| 372 | |
| 373 | } |
| 374 | return IRQ_RETVAL(handled); |
| 375 | /* leave("i82092aa_interrupt");*/ |
| 376 | } |
| 377 | |
| 378 | |
| 379 | |
| 380 | /* socket functions */ |
| 381 | |
| 382 | static int card_present(int socketno) |
| 383 | { |
| 384 | unsigned int val; |
| 385 | enter("card_present"); |
| 386 | |
| 387 | if ((socketno<0) || (socketno >= MAX_SOCKETS)) |
| 388 | return 0; |
| 389 | if (sockets[socketno].io_base == 0) |
| 390 | return 0; |
| 391 | |
| 392 | |
| 393 | val = indirect_read(socketno, 1); /* Interface status register */ |
| 394 | if ((val&12)==12) { |
| 395 | leave("card_present 1"); |
| 396 | return 1; |
| 397 | } |
| 398 | |
| 399 | leave("card_present 0"); |
| 400 | return 0; |
| 401 | } |
| 402 | |
| 403 | static void set_bridge_state(int sock) |
| 404 | { |
| 405 | enter("set_bridge_state"); |
| 406 | indirect_write(sock, I365_GBLCTL,0x00); |
| 407 | indirect_write(sock, I365_GENCTL,0x00); |
| 408 | |
| 409 | indirect_setbit(sock, I365_INTCTL,0x08); |
| 410 | leave("set_bridge_state"); |
| 411 | } |
| 412 | |
| 413 | |
| 414 | |
| 415 | |
| 416 | |
| 417 | |
| 418 | static int i82092aa_init(struct pcmcia_socket *sock) |
| 419 | { |
| 420 | int i; |
| 421 | struct resource res = { .start = 0, .end = 0x0fff }; |
| 422 | pccard_io_map io = { 0, 0, 0, 0, 1 }; |
| 423 | pccard_mem_map mem = { .res = &res, }; |
| 424 | |
| 425 | enter("i82092aa_init"); |
| 426 | |
| 427 | for (i = 0; i < 2; i++) { |
| 428 | io.map = i; |
| 429 | i82092aa_set_io_map(sock, &io); |
| 430 | } |
| 431 | for (i = 0; i < 5; i++) { |
| 432 | mem.map = i; |
| 433 | i82092aa_set_mem_map(sock, &mem); |
| 434 | } |
| 435 | |
| 436 | leave("i82092aa_init"); |
| 437 | return 0; |
| 438 | } |
| 439 | |
| 440 | static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value) |
| 441 | { |
| 442 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; |
| 443 | unsigned int status; |
| 444 | |
| 445 | enter("i82092aa_get_status"); |
| 446 | |
| 447 | status = indirect_read(sock,I365_STATUS); /* Interface Status Register */ |
| 448 | *value = 0; |
| 449 | |
| 450 | if ((status & I365_CS_DETECT) == I365_CS_DETECT) { |
| 451 | *value |= SS_DETECT; |
| 452 | } |
| 453 | |
| 454 | /* IO cards have a different meaning of bits 0,1 */ |
| 455 | /* Also notice the inverse-logic on the bits */ |
| 456 | if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) { |
| 457 | /* IO card */ |
| 458 | if (!(status & I365_CS_STSCHG)) |
| 459 | *value |= SS_STSCHG; |
| 460 | } else { /* non I/O card */ |
| 461 | if (!(status & I365_CS_BVD1)) |
| 462 | *value |= SS_BATDEAD; |
| 463 | if (!(status & I365_CS_BVD2)) |
| 464 | *value |= SS_BATWARN; |
| 465 | |
| 466 | } |
| 467 | |
| 468 | if (status & I365_CS_WRPROT) |
| 469 | (*value) |= SS_WRPROT; /* card is write protected */ |
| 470 | |
| 471 | if (status & I365_CS_READY) |
| 472 | (*value) |= SS_READY; /* card is not busy */ |
| 473 | |
| 474 | if (status & I365_CS_POWERON) |
| 475 | (*value) |= SS_POWERON; /* power is applied to the card */ |
| 476 | |
| 477 | |
| 478 | leave("i82092aa_get_status"); |
| 479 | return 0; |
| 480 | } |
| 481 | |
| 482 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state) |
| 484 | { |
| 485 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; |
| 486 | unsigned char reg; |
| 487 | |
| 488 | enter("i82092aa_set_socket"); |
| 489 | |
| 490 | /* First, set the global controller options */ |
| 491 | |
| 492 | set_bridge_state(sock); |
| 493 | |
| 494 | /* Values for the IGENC register */ |
| 495 | |
| 496 | reg = 0; |
| 497 | if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */ |
| 498 | reg = reg | I365_PC_RESET; |
| 499 | if (state->flags & SS_IOCARD) |
| 500 | reg = reg | I365_PC_IOCARD; |
| 501 | |
| 502 | indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */ |
| 503 | |
| 504 | /* Power registers */ |
| 505 | |
| 506 | reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ |
| 507 | |
| 508 | if (state->flags & SS_PWR_AUTO) { |
| 509 | printk("Auto power\n"); |
| 510 | reg |= I365_PWR_AUTO; /* automatic power mngmnt */ |
| 511 | } |
| 512 | if (state->flags & SS_OUTPUT_ENA) { |
| 513 | printk("Power Enabled \n"); |
| 514 | reg |= I365_PWR_OUT; /* enable power */ |
| 515 | } |
| 516 | |
| 517 | switch (state->Vcc) { |
| 518 | case 0: |
| 519 | break; |
| 520 | case 50: |
| 521 | printk("setting voltage to Vcc to 5V on socket %i\n",sock); |
| 522 | reg |= I365_VCC_5V; |
| 523 | break; |
| 524 | default: |
| 525 | printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc); |
| 526 | leave("i82092aa_set_socket"); |
| 527 | return -EINVAL; |
| 528 | } |
| 529 | |
| 530 | |
| 531 | switch (state->Vpp) { |
| 532 | case 0: |
| 533 | printk("not setting Vpp on socket %i\n",sock); |
| 534 | break; |
| 535 | case 50: |
| 536 | printk("setting Vpp to 5.0 for socket %i\n",sock); |
| 537 | reg |= I365_VPP1_5V | I365_VPP2_5V; |
| 538 | break; |
| 539 | case 120: |
| 540 | printk("setting Vpp to 12.0\n"); |
| 541 | reg |= I365_VPP1_12V | I365_VPP2_12V; |
| 542 | break; |
| 543 | default: |
| 544 | printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc); |
| 545 | leave("i82092aa_set_socket"); |
| 546 | return -EINVAL; |
| 547 | } |
| 548 | |
| 549 | if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */ |
| 550 | indirect_write(sock,I365_POWER,reg); |
| 551 | |
| 552 | /* Enable specific interrupt events */ |
| 553 | |
| 554 | reg = 0x00; |
| 555 | if (state->csc_mask & SS_DETECT) { |
| 556 | reg |= I365_CSC_DETECT; |
| 557 | } |
| 558 | if (state->flags & SS_IOCARD) { |
| 559 | if (state->csc_mask & SS_STSCHG) |
| 560 | reg |= I365_CSC_STSCHG; |
| 561 | } else { |
| 562 | if (state->csc_mask & SS_BATDEAD) |
| 563 | reg |= I365_CSC_BVD1; |
| 564 | if (state->csc_mask & SS_BATWARN) |
| 565 | reg |= I365_CSC_BVD2; |
| 566 | if (state->csc_mask & SS_READY) |
| 567 | reg |= I365_CSC_READY; |
| 568 | |
| 569 | } |
| 570 | |
| 571 | /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/ |
| 572 | |
| 573 | indirect_write(sock,I365_CSCINT,reg); |
| 574 | (void)indirect_read(sock,I365_CSC); |
| 575 | |
| 576 | leave("i82092aa_set_socket"); |
| 577 | return 0; |
| 578 | } |
| 579 | |
| 580 | static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io) |
| 581 | { |
| 582 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; |
| 583 | unsigned char map, ioctl; |
| 584 | |
| 585 | enter("i82092aa_set_io_map"); |
| 586 | |
| 587 | map = io->map; |
| 588 | |
| 589 | /* Check error conditions */ |
| 590 | if (map > 1) { |
| 591 | leave("i82092aa_set_io_map with invalid map"); |
| 592 | return -EINVAL; |
| 593 | } |
| 594 | if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){ |
| 595 | leave("i82092aa_set_io_map with invalid io"); |
| 596 | return -EINVAL; |
| 597 | } |
| 598 | |
| 599 | /* Turn off the window before changing anything */ |
| 600 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map)) |
| 601 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); |
| 602 | |
| 603 | /* printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop); */ |
| 604 | |
| 605 | /* write the new values */ |
| 606 | indirect_write16(sock,I365_IO(map)+I365_W_START,io->start); |
| 607 | indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop); |
| 608 | |
| 609 | ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map); |
| 610 | |
| 611 | if (io->flags & (MAP_16BIT|MAP_AUTOSZ)) |
| 612 | ioctl |= I365_IOCTL_16BIT(map); |
| 613 | |
| 614 | indirect_write(sock,I365_IOCTL,ioctl); |
| 615 | |
| 616 | /* Turn the window back on if needed */ |
| 617 | if (io->flags & MAP_ACTIVE) |
| 618 | indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map)); |
| 619 | |
| 620 | leave("i82092aa_set_io_map"); |
| 621 | return 0; |
| 622 | } |
| 623 | |
| 624 | static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem) |
| 625 | { |
| 626 | struct socket_info *sock_info = container_of(socket, struct socket_info, socket); |
| 627 | unsigned int sock = sock_info->number; |
| 628 | struct pci_bus_region region; |
| 629 | unsigned short base, i; |
| 630 | unsigned char map; |
| 631 | |
| 632 | enter("i82092aa_set_mem_map"); |
| 633 | |
| 634 | pcibios_resource_to_bus(sock_info->dev, ®ion, mem->res); |
| 635 | |
| 636 | map = mem->map; |
| 637 | if (map > 4) { |
| 638 | leave("i82092aa_set_mem_map: invalid map"); |
| 639 | return -EINVAL; |
| 640 | } |
| 641 | |
| 642 | |
| 643 | if ( (mem->card_start > 0x3ffffff) || (region.start > region.end) || |
| 644 | (mem->speed > 1000) ) { |
| 645 | leave("i82092aa_set_mem_map: invalid address / speed"); |
| 646 | printk("invalid mem map for socket %i : %lx to %lx with a start of %x \n",sock,region.start, region.end, mem->card_start); |
| 647 | return -EINVAL; |
| 648 | } |
| 649 | |
| 650 | /* Turn off the window before changing anything */ |
| 651 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map)) |
| 652 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); |
| 653 | |
| 654 | |
| 655 | /* printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, region.start,region.end,sock,mem->speed,mem->flags & MAP_ACTIVE); */ |
| 656 | |
| 657 | /* write the start address */ |
| 658 | base = I365_MEM(map); |
| 659 | i = (region.start >> 12) & 0x0fff; |
| 660 | if (mem->flags & MAP_16BIT) |
| 661 | i |= I365_MEM_16BIT; |
| 662 | if (mem->flags & MAP_0WS) |
| 663 | i |= I365_MEM_0WS; |
| 664 | indirect_write16(sock,base+I365_W_START,i); |
| 665 | |
| 666 | /* write the stop address */ |
| 667 | |
| 668 | i= (region.end >> 12) & 0x0fff; |
| 669 | switch (to_cycles(mem->speed)) { |
| 670 | case 0: |
| 671 | break; |
| 672 | case 1: |
| 673 | i |= I365_MEM_WS0; |
| 674 | break; |
| 675 | case 2: |
| 676 | i |= I365_MEM_WS1; |
| 677 | break; |
| 678 | default: |
| 679 | i |= I365_MEM_WS1 | I365_MEM_WS0; |
| 680 | break; |
| 681 | } |
| 682 | |
| 683 | indirect_write16(sock,base+I365_W_STOP,i); |
| 684 | |
| 685 | /* card start */ |
| 686 | |
| 687 | i = ((mem->card_start - region.start) >> 12) & 0x3fff; |
| 688 | if (mem->flags & MAP_WRPROT) |
| 689 | i |= I365_MEM_WRPROT; |
| 690 | if (mem->flags & MAP_ATTRIB) { |
| 691 | /* printk("requesting attribute memory for socket %i\n",sock);*/ |
| 692 | i |= I365_MEM_REG; |
| 693 | } else { |
| 694 | /* printk("requesting normal memory for socket %i\n",sock);*/ |
| 695 | } |
| 696 | indirect_write16(sock,base+I365_W_OFF,i); |
| 697 | |
| 698 | /* Enable the window if necessary */ |
| 699 | if (mem->flags & MAP_ACTIVE) |
| 700 | indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); |
| 701 | |
| 702 | leave("i82092aa_set_mem_map"); |
| 703 | return 0; |
| 704 | } |
| 705 | |
| 706 | static int i82092aa_module_init(void) |
| 707 | { |
| 708 | enter("i82092aa_module_init"); |
| 709 | pci_register_driver(&i82092aa_pci_drv); |
| 710 | leave("i82092aa_module_init"); |
| 711 | return 0; |
| 712 | } |
| 713 | |
| 714 | static void i82092aa_module_exit(void) |
| 715 | { |
| 716 | enter("i82092aa_module_exit"); |
| 717 | pci_unregister_driver(&i82092aa_pci_drv); |
| 718 | if (sockets[0].io_base>0) |
| 719 | release_region(sockets[0].io_base, 2); |
| 720 | leave("i82092aa_module_exit"); |
| 721 | } |
| 722 | |
| 723 | module_init(i82092aa_module_init); |
| 724 | module_exit(i82092aa_module_exit); |
| 725 | |