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Luis R. Rodriguezd15dd3e2009-08-12 09:56:59 -07001/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH_H
18#define ATH_H
19
20#include <linux/skbuff.h>
Luis R. Rodriguezbcd8f542009-09-09 22:43:17 -070021#include <linux/if_ether.h>
Felix Fietkaub5bfc562010-10-08 22:13:53 +020022#include <linux/spinlock.h>
Luis R. Rodriguezb002a4a2009-09-13 00:03:27 -070023#include <net/mac80211.h>
Luis R. Rodriguezd15dd3e2009-08-12 09:56:59 -070024
Luis R. Rodriguez7e86c102009-11-04 17:21:01 -080025/*
26 * The key cache is used for h/w cipher state and also for
27 * tracking station state such as the current tx antenna.
28 * We also setup a mapping table between key cache slot indices
29 * and station state to short-circuit node lookups on rx.
30 * Different parts have different size key caches. We handle
31 * up to ATH_KEYMAX entries (could dynamically allocate state).
32 */
33#define ATH_KEYMAX 128 /* max key cache size we handle */
34
Luis R. Rodriguez17753742009-09-09 22:19:26 -070035static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
36
Luis R. Rodriguez3d536ac2009-11-03 17:07:04 -080037struct ath_ani {
38 bool caldone;
Luis R. Rodriguez3d536ac2009-11-03 17:07:04 -080039 unsigned int longcal_timer;
40 unsigned int shortcal_timer;
41 unsigned int resetcal_timer;
42 unsigned int checkani_timer;
43 struct timer_list timer;
44};
45
Felix Fietkaub5bfc562010-10-08 22:13:53 +020046struct ath_cycle_counters {
47 u32 cycles;
48 u32 rx_busy;
49 u32 rx_frame;
50 u32 tx_frame;
51};
52
Luis R. Rodriguez211f5852009-10-06 21:19:07 -040053enum ath_device_state {
54 ATH_HW_UNAVAILABLE,
55 ATH_HW_INITIALIZED,
56};
57
Sujith497ad9a2010-04-01 10:28:20 +053058enum ath_bus_type {
59 ATH_PCI,
60 ATH_AHB,
61 ATH_USB,
62};
63
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -070064struct reg_dmn_pair_mapping {
65 u16 regDmnEnum;
66 u16 reg_5ghz_ctl;
67 u16 reg_2ghz_ctl;
68};
69
70struct ath_regulatory {
71 char alpha2[2];
72 u16 country_code;
73 u16 max_power_level;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -070074 u16 current_rd;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -070075 int16_t power_limit;
76 struct reg_dmn_pair_mapping *regpair;
77};
78
Bruno Randolf34a13052010-09-08 16:04:33 +090079enum ath_crypt_caps {
Bruno Randolfce2220d2010-09-17 11:36:25 +090080 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
81 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
Bruno Randolf34a13052010-09-08 16:04:33 +090082};
83
Bruno Randolf1bba5b72010-09-08 16:04:38 +090084struct ath_keyval {
85 u8 kv_type;
86 u8 kv_pad;
87 u16 kv_len;
88 u8 kv_val[16]; /* TK */
89 u8 kv_mic[8]; /* Michael MIC key */
90 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
91 * supports both MIC keys in the same key cache entry;
92 * in that case, kv_mic is the RX key) */
93};
94
95enum ath_cipher {
96 ATH_CIPHER_WEP = 0,
97 ATH_CIPHER_AES_OCB = 1,
98 ATH_CIPHER_AES_CCM = 2,
99 ATH_CIPHER_CKIP = 3,
100 ATH_CIPHER_TKIP = 4,
101 ATH_CIPHER_CLR = 5,
102 ATH_CIPHER_MIC = 127
103};
104
Sujith50f56312010-04-16 11:53:50 +0530105/**
106 * struct ath_ops - Register read/write operations
107 *
108 * @read: Register read
Sujith Manoharan09a525d2011-01-04 13:17:18 +0530109 * @multi_read: Multiple register read
Sujith50f56312010-04-16 11:53:50 +0530110 * @write: Register write
111 * @enable_write_buffer: Enable multiple register writes
Felix Fietkau435c1612010-10-05 12:03:42 +0200112 * @write_flush: flush buffered register writes and disable buffering
Sujith50f56312010-04-16 11:53:50 +0530113 */
Luis R. Rodriguez9e4bffd2009-09-10 16:11:21 -0700114struct ath_ops {
115 unsigned int (*read)(void *, u32 reg_offset);
Sujith Manoharan09a525d2011-01-04 13:17:18 +0530116 void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
Sujith50f56312010-04-16 11:53:50 +0530117 void (*write)(void *, u32 val, u32 reg_offset);
118 void (*enable_write_buffer)(void *);
Sujith50f56312010-04-16 11:53:50 +0530119 void (*write_flush) (void *);
Felix Fietkau845e03c2011-03-23 20:57:25 +0100120 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
Luis R. Rodriguez9e4bffd2009-09-10 16:11:21 -0700121};
122
Luis R. Rodriguez5bb12792009-09-14 00:55:09 -0700123struct ath_common;
Felix Fietkau0cb9e062011-04-13 21:56:43 +0200124struct ath_bus_ops;
Luis R. Rodriguez5bb12792009-09-14 00:55:09 -0700125
Luis R. Rodriguezd15dd3e2009-08-12 09:56:59 -0700126struct ath_common {
Luis R. Rodriguez13b81552009-09-10 17:52:45 -0700127 void *ah;
Luis R. Rodriguezbc974f42009-09-28 02:54:40 -0400128 void *priv;
Luis R. Rodriguezb002a4a2009-09-13 00:03:27 -0700129 struct ieee80211_hw *hw;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700130 int debug_mask;
Luis R. Rodriguez211f5852009-10-06 21:19:07 -0400131 enum ath_device_state state;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700132
Luis R. Rodriguez3d536ac2009-11-03 17:07:04 -0800133 struct ath_ani ani;
134
Luis R. Rodriguezd15dd3e2009-08-12 09:56:59 -0700135 u16 cachelsz;
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700136 u16 curaid;
137 u8 macaddr[ETH_ALEN];
138 u8 curbssid[ETH_ALEN];
139 u8 bssidmask[ETH_ALEN];
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700140
Luis R. Rodriguezcc861f72009-11-04 09:11:34 -0800141 u32 rx_bufsize;
142
Luis R. Rodriguez7e86c102009-11-04 17:21:01 -0800143 u32 keymax;
144 DECLARE_BITMAP(keymap, ATH_KEYMAX);
Felix Fietkau56363dd2010-08-28 18:21:21 +0200145 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
Bruno Randolf34a13052010-09-08 16:04:33 +0900146 enum ath_crypt_caps crypt_caps;
Luis R. Rodriguez7e86c102009-11-04 17:21:01 -0800147
Felix Fietkaudfdac8a2010-10-08 22:13:51 +0200148 unsigned int clockrate;
149
Felix Fietkaub5bfc562010-10-08 22:13:53 +0200150 spinlock_t cc_lock;
151 struct ath_cycle_counters cc_ani;
152 struct ath_cycle_counters cc_survey;
153
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700154 struct ath_regulatory regulatory;
Luis R. Rodriguezde1c7322011-12-08 23:59:24 +0530155 struct ath_regulatory reg_world_copy;
Luis R. Rodriguez9adca122009-09-10 18:04:47 -0700156 const struct ath_ops *ops;
Luis R. Rodriguez5bb12792009-09-14 00:55:09 -0700157 const struct ath_bus_ops *bus_ops;
Vasanthakumar Thiagarajan8f5dcb12010-11-26 06:10:06 -0800158
159 bool btcoex_enabled;
Mohammed Shafi Shajakhan05c0be22011-05-26 10:56:15 +0530160 bool disable_ani;
Luis R. Rodriguezd15dd3e2009-08-12 09:56:59 -0700161};
162
163struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
164 u32 len,
165 gfp_t gfp_mask);
166
Luis R. Rodriguez13b81552009-09-10 17:52:45 -0700167void ath_hw_setbssidmask(struct ath_common *common);
Bruno Randolf1bba5b72010-09-08 16:04:38 +0900168void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
169int ath_key_config(struct ath_common *common,
170 struct ieee80211_vif *vif,
171 struct ieee80211_sta *sta,
172 struct ieee80211_key_conf *key);
173bool ath_hw_keyreset(struct ath_common *common, u16 entry);
Felix Fietkaub5bfc562010-10-08 22:13:53 +0200174void ath_hw_cycle_counters_update(struct ath_common *common);
175int32_t ath_hw_get_listen_time(struct ath_common *common);
Luis R. Rodriguez13b81552009-09-10 17:52:45 -0700176
Ben Greear98b36a02012-03-08 10:20:55 -0800177__printf(3, 4)
178void ath_printk(const char *level, const struct ath_common *common,
179 const char *fmt, ...);
Joe Perches21a99f92010-12-02 19:12:35 -0800180
181#define ath_emerg(common, fmt, ...) \
Ben Greear98b36a02012-03-08 10:20:55 -0800182 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
Joe Perches21a99f92010-12-02 19:12:35 -0800183#define ath_alert(common, fmt, ...) \
Ben Greear98b36a02012-03-08 10:20:55 -0800184 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
Joe Perches21a99f92010-12-02 19:12:35 -0800185#define ath_crit(common, fmt, ...) \
Ben Greear98b36a02012-03-08 10:20:55 -0800186 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
Joe Perches21a99f92010-12-02 19:12:35 -0800187#define ath_err(common, fmt, ...) \
Ben Greear98b36a02012-03-08 10:20:55 -0800188 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
Joe Perches21a99f92010-12-02 19:12:35 -0800189#define ath_warn(common, fmt, ...) \
Ben Greear98b36a02012-03-08 10:20:55 -0800190 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
Joe Perches21a99f92010-12-02 19:12:35 -0800191#define ath_notice(common, fmt, ...) \
Ben Greear98b36a02012-03-08 10:20:55 -0800192 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
Joe Perches21a99f92010-12-02 19:12:35 -0800193#define ath_info(common, fmt, ...) \
Ben Greear98b36a02012-03-08 10:20:55 -0800194 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
Joe Perches21a99f92010-12-02 19:12:35 -0800195
196/**
197 * enum ath_debug_level - atheros wireless debug level
198 *
199 * @ATH_DBG_RESET: reset processing
200 * @ATH_DBG_QUEUE: hardware queue management
201 * @ATH_DBG_EEPROM: eeprom processing
202 * @ATH_DBG_CALIBRATE: periodic calibration
203 * @ATH_DBG_INTERRUPT: interrupt processing
204 * @ATH_DBG_REGULATORY: regulatory processing
205 * @ATH_DBG_ANI: adaptive noise immunitive processing
206 * @ATH_DBG_XMIT: basic xmit operation
207 * @ATH_DBG_BEACON: beacon handling
208 * @ATH_DBG_CONFIG: configuration of the hardware
209 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
210 * @ATH_DBG_PS: power save processing
211 * @ATH_DBG_HWTIMER: hardware timer handling
212 * @ATH_DBG_BTCOEX: bluetooth coexistance
213 * @ATH_DBG_BSTUCK: stuck beacons
Luis R. Rodriguez55e435d2011-12-14 13:56:36 -0800214 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
215 * used exclusively for WLAN-BT coexistence starting from
216 * AR9462.
Zefir Kurtisi9b203c82011-12-14 20:16:32 -0800217 * @ATH_DBG_DFS: radar datection
Joe Perches21a99f92010-12-02 19:12:35 -0800218 * @ATH_DBG_ANY: enable all debugging
219 *
220 * The debug level is used to control the amount and type of debugging output
221 * we want to see. Each driver has its own method for enabling debugging and
222 * modifying debug level states -- but this is typically done through a
223 * module parameter 'debug' along with a respective 'debug' debugfs file
224 * entry.
225 */
226enum ATH_DEBUG {
227 ATH_DBG_RESET = 0x00000001,
228 ATH_DBG_QUEUE = 0x00000002,
229 ATH_DBG_EEPROM = 0x00000004,
230 ATH_DBG_CALIBRATE = 0x00000008,
231 ATH_DBG_INTERRUPT = 0x00000010,
232 ATH_DBG_REGULATORY = 0x00000020,
233 ATH_DBG_ANI = 0x00000040,
234 ATH_DBG_XMIT = 0x00000080,
235 ATH_DBG_BEACON = 0x00000100,
236 ATH_DBG_CONFIG = 0x00000200,
237 ATH_DBG_FATAL = 0x00000400,
238 ATH_DBG_PS = 0x00000800,
239 ATH_DBG_HWTIMER = 0x00001000,
240 ATH_DBG_BTCOEX = 0x00002000,
241 ATH_DBG_WMI = 0x00004000,
242 ATH_DBG_BSTUCK = 0x00008000,
Rajkumar Manoharan7dc181c2011-10-24 18:19:49 +0530243 ATH_DBG_MCI = 0x00010000,
Zefir Kurtisi9b203c82011-12-14 20:16:32 -0800244 ATH_DBG_DFS = 0x00020000,
Joe Perches21a99f92010-12-02 19:12:35 -0800245 ATH_DBG_ANY = 0xffffffff
246};
247
248#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
249
250#ifdef CONFIG_ATH_DEBUG
251
Joe Perches7b8112d2011-08-26 01:56:38 -0700252#define ath_dbg(common, dbg_mask, fmt, ...) \
253do { \
Joe Perchesd2182b62011-12-15 14:55:53 -0800254 if ((common)->debug_mask & ATH_DBG_##dbg_mask) \
Ben Greear98b36a02012-03-08 10:20:55 -0800255 ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \
Joe Perches7b8112d2011-08-26 01:56:38 -0700256} while (0)
257
Joe Perches21a99f92010-12-02 19:12:35 -0800258#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
Ben Greeard7fd1b502010-12-06 13:13:07 -0800259#define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
Joe Perches21a99f92010-12-02 19:12:35 -0800260
261#else
262
Joe Perchesb9075fa2011-10-31 17:11:33 -0700263static inline __attribute__ ((format (printf, 3, 4)))
Joe Perchesd2182b62011-12-15 14:55:53 -0800264void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
Joe Perches7b8112d2011-08-26 01:56:38 -0700265 const char *fmt, ...)
Joe Perches21a99f92010-12-02 19:12:35 -0800266{
Joe Perches21a99f92010-12-02 19:12:35 -0800267}
Joe Perchesd2182b62011-12-15 14:55:53 -0800268#define ath_dbg(common, dbg_mask, fmt, ...) \
269 _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)
270
Joe Perches21a99f92010-12-02 19:12:35 -0800271#define ATH_DBG_WARN(foo, arg...) do {} while (0)
John W. Linvilleb7613372010-12-09 09:08:47 -0500272#define ATH_DBG_WARN_ON_ONCE(foo) ({ \
273 int __ret_warn_once = !!(foo); \
274 unlikely(__ret_warn_once); \
275})
Joe Perches21a99f92010-12-02 19:12:35 -0800276
277#endif /* CONFIG_ATH_DEBUG */
278
279/** Returns string describing opmode, or NULL if unknown mode. */
280#ifdef CONFIG_ATH_DEBUG
281const char *ath_opmode_to_string(enum nl80211_iftype opmode);
282#else
283static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
284{
285 return "UNKNOWN";
286}
287#endif
288
Luis R. Rodriguezd15dd3e2009-08-12 09:56:59 -0700289#endif /* ATH_H */