Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _CORESIGHT_CORESIGHT_ETM_H |
| 14 | #define _CORESIGHT_CORESIGHT_ETM_H |
| 15 | |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 16 | #include <asm/local.h> |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 17 | #include <linux/spinlock.h> |
| 18 | #include "coresight-priv.h" |
| 19 | |
| 20 | /* |
| 21 | * Device registers: |
| 22 | * 0x000 - 0x2FC: Trace registers |
| 23 | * 0x300 - 0x314: Management registers |
| 24 | * 0x318 - 0xEFC: Trace registers |
| 25 | * |
| 26 | * Coresight registers |
| 27 | * 0xF00 - 0xF9C: Management registers |
| 28 | * 0xFA0 - 0xFA4: Management registers in PFTv1.0 |
| 29 | * Trace registers in PFTv1.1 |
| 30 | * 0xFA8 - 0xFFC: Management registers |
| 31 | */ |
| 32 | |
| 33 | /* Trace registers (0x000-0x2FC) */ |
| 34 | #define ETMCR 0x000 |
| 35 | #define ETMCCR 0x004 |
| 36 | #define ETMTRIGGER 0x008 |
| 37 | #define ETMSR 0x010 |
| 38 | #define ETMSCR 0x014 |
| 39 | #define ETMTSSCR 0x018 |
| 40 | #define ETMTECR2 0x01c |
| 41 | #define ETMTEEVR 0x020 |
| 42 | #define ETMTECR1 0x024 |
| 43 | #define ETMFFLR 0x02c |
| 44 | #define ETMACVRn(n) (0x040 + (n * 4)) |
| 45 | #define ETMACTRn(n) (0x080 + (n * 4)) |
| 46 | #define ETMCNTRLDVRn(n) (0x140 + (n * 4)) |
| 47 | #define ETMCNTENRn(n) (0x150 + (n * 4)) |
| 48 | #define ETMCNTRLDEVRn(n) (0x160 + (n * 4)) |
| 49 | #define ETMCNTVRn(n) (0x170 + (n * 4)) |
| 50 | #define ETMSQ12EVR 0x180 |
| 51 | #define ETMSQ21EVR 0x184 |
| 52 | #define ETMSQ23EVR 0x188 |
| 53 | #define ETMSQ31EVR 0x18c |
| 54 | #define ETMSQ32EVR 0x190 |
| 55 | #define ETMSQ13EVR 0x194 |
| 56 | #define ETMSQR 0x19c |
| 57 | #define ETMEXTOUTEVRn(n) (0x1a0 + (n * 4)) |
| 58 | #define ETMCIDCVRn(n) (0x1b0 + (n * 4)) |
| 59 | #define ETMCIDCMR 0x1bc |
| 60 | #define ETMIMPSPEC0 0x1c0 |
| 61 | #define ETMIMPSPEC1 0x1c4 |
| 62 | #define ETMIMPSPEC2 0x1c8 |
| 63 | #define ETMIMPSPEC3 0x1cc |
| 64 | #define ETMIMPSPEC4 0x1d0 |
| 65 | #define ETMIMPSPEC5 0x1d4 |
| 66 | #define ETMIMPSPEC6 0x1d8 |
| 67 | #define ETMIMPSPEC7 0x1dc |
| 68 | #define ETMSYNCFR 0x1e0 |
| 69 | #define ETMIDR 0x1e4 |
| 70 | #define ETMCCER 0x1e8 |
| 71 | #define ETMEXTINSELR 0x1ec |
| 72 | #define ETMTESSEICR 0x1f0 |
| 73 | #define ETMEIBCR 0x1f4 |
| 74 | #define ETMTSEVR 0x1f8 |
| 75 | #define ETMAUXCR 0x1fc |
| 76 | #define ETMTRACEIDR 0x200 |
| 77 | #define ETMVMIDCVR 0x240 |
| 78 | /* Management registers (0x300-0x314) */ |
| 79 | #define ETMOSLAR 0x300 |
| 80 | #define ETMOSLSR 0x304 |
| 81 | #define ETMOSSRR 0x308 |
| 82 | #define ETMPDCR 0x310 |
| 83 | #define ETMPDSR 0x314 |
| 84 | #define ETM_MAX_ADDR_CMP 16 |
| 85 | #define ETM_MAX_CNTR 4 |
| 86 | #define ETM_MAX_CTXID_CMP 3 |
| 87 | |
| 88 | /* Register definition */ |
| 89 | /* ETMCR - 0x00 */ |
| 90 | #define ETMCR_PWD_DWN BIT(0) |
| 91 | #define ETMCR_STALL_MODE BIT(7) |
| 92 | #define ETMCR_ETM_PRG BIT(10) |
| 93 | #define ETMCR_ETM_EN BIT(11) |
| 94 | #define ETMCR_CYC_ACC BIT(12) |
| 95 | #define ETMCR_CTXID_SIZE (BIT(14)|BIT(15)) |
| 96 | #define ETMCR_TIMESTAMP_EN BIT(28) |
| 97 | /* ETMCCR - 0x04 */ |
| 98 | #define ETMCCR_FIFOFULL BIT(23) |
| 99 | /* ETMPDCR - 0x310 */ |
| 100 | #define ETMPDCR_PWD_UP BIT(3) |
| 101 | /* ETMTECR1 - 0x024 */ |
| 102 | #define ETMTECR1_ADDR_COMP_1 BIT(0) |
| 103 | #define ETMTECR1_INC_EXC BIT(24) |
| 104 | #define ETMTECR1_START_STOP BIT(25) |
| 105 | /* ETMCCER - 0x1E8 */ |
| 106 | #define ETMCCER_TIMESTAMP BIT(22) |
| 107 | |
| 108 | #define ETM_MODE_EXCLUDE BIT(0) |
| 109 | #define ETM_MODE_CYCACC BIT(1) |
| 110 | #define ETM_MODE_STALL BIT(2) |
| 111 | #define ETM_MODE_TIMESTAMP BIT(3) |
| 112 | #define ETM_MODE_CTXID BIT(4) |
Mathieu Poirier | 2127154 | 2016-02-17 17:51:56 -0700 | [diff] [blame] | 113 | #define ETM_MODE_ALL (ETM_MODE_EXCLUDE | ETM_MODE_CYCACC | \ |
| 114 | ETM_MODE_STALL | ETM_MODE_TIMESTAMP | \ |
| 115 | ETM_MODE_CTXID | ETM_MODE_EXCL_KERN | \ |
| 116 | ETM_MODE_EXCL_USER) |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 117 | |
| 118 | #define ETM_SQR_MASK 0x3 |
| 119 | #define ETM_TRACEID_MASK 0x3f |
| 120 | #define ETM_EVENT_MASK 0x1ffff |
| 121 | #define ETM_SYNC_MASK 0xfff |
| 122 | #define ETM_ALL_MASK 0xffffffff |
| 123 | |
| 124 | #define ETMSR_PROG_BIT 1 |
| 125 | #define ETM_SEQ_STATE_MAX_VAL (0x2) |
| 126 | #define PORT_SIZE_MASK (GENMASK(21, 21) | GENMASK(6, 4)) |
| 127 | |
| 128 | #define ETM_HARD_WIRE_RES_A /* Hard wired, always true */ \ |
| 129 | ((0x0f << 0) | \ |
| 130 | /* Resource index A */ \ |
| 131 | (0x06 << 4)) |
| 132 | |
| 133 | #define ETM_ADD_COMP_0 /* Single addr comparator 1 */ \ |
| 134 | ((0x00 << 7) | \ |
| 135 | /* Resource index B */ \ |
| 136 | (0x00 << 11)) |
| 137 | |
| 138 | #define ETM_EVENT_NOT_A BIT(14) /* NOT(A) */ |
| 139 | |
| 140 | #define ETM_DEFAULT_EVENT_VAL (ETM_HARD_WIRE_RES_A | \ |
| 141 | ETM_ADD_COMP_0 | \ |
| 142 | ETM_EVENT_NOT_A) |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 143 | |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 144 | /** |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 145 | * struct etm_config - configuration information related to an ETM |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 146 | * @mode: controls various modes supported by this ETM/PTM. |
| 147 | * @ctrl: used in conjunction with @mode. |
| 148 | * @trigger_event: setting for register ETMTRIGGER. |
| 149 | * @startstop_ctrl: setting for register ETMTSSCR. |
| 150 | * @enable_event: setting for register ETMTEEVR. |
| 151 | * @enable_ctrl1: setting for register ETMTECR1. |
Mathieu Poirier | e192172 | 2016-02-17 17:51:54 -0700 | [diff] [blame] | 152 | * @enable_ctrl2: setting for register ETMTECR2. |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 153 | * @fifofull_level: setting for register ETMFFLR. |
| 154 | * @addr_idx: index for the address comparator selection. |
| 155 | * @addr_val: value for address comparator register. |
| 156 | * @addr_acctype: access type for address comparator register. |
| 157 | * @addr_type: current status of the comparator register. |
| 158 | * @cntr_idx: index for the counter register selection. |
| 159 | * @cntr_rld_val: reload value of a counter register. |
| 160 | * @cntr_event: control for counter enable register. |
| 161 | * @cntr_rld_event: value for counter reload event register. |
| 162 | * @cntr_val: counter value register. |
| 163 | * @seq_12_event: event causing the transition from 1 to 2. |
| 164 | * @seq_21_event: event causing the transition from 2 to 1. |
| 165 | * @seq_23_event: event causing the transition from 2 to 3. |
| 166 | * @seq_31_event: event causing the transition from 3 to 1. |
| 167 | * @seq_32_event: event causing the transition from 3 to 2. |
| 168 | * @seq_13_event: event causing the transition from 1 to 3. |
| 169 | * @seq_curr_state: current value of the sequencer register. |
| 170 | * @ctxid_idx: index for the context ID registers. |
Chunyan Zhang | 414a141 | 2015-07-31 09:37:24 -0600 | [diff] [blame] | 171 | * @ctxid_pid: value for the context ID to trigger on. |
Chunyan Zhang | a440617 | 2015-07-31 09:37:27 -0600 | [diff] [blame] | 172 | * @ctxid_vpid: Virtual PID seen by users if PID namespace is enabled, otherwise |
| 173 | * the same value of ctxid_pid. |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 174 | * @ctxid_mask: mask applicable to all the context IDs. |
| 175 | * @sync_freq: Synchronisation frequency. |
| 176 | * @timestamp_event: Defines an event that requests the insertion |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 177 | * of a timestamp into the trace stream. |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 178 | */ |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 179 | struct etm_config { |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 180 | u32 mode; |
| 181 | u32 ctrl; |
| 182 | u32 trigger_event; |
| 183 | u32 startstop_ctrl; |
| 184 | u32 enable_event; |
| 185 | u32 enable_ctrl1; |
Mathieu Poirier | e192172 | 2016-02-17 17:51:54 -0700 | [diff] [blame] | 186 | u32 enable_ctrl2; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 187 | u32 fifofull_level; |
| 188 | u8 addr_idx; |
| 189 | u32 addr_val[ETM_MAX_ADDR_CMP]; |
| 190 | u32 addr_acctype[ETM_MAX_ADDR_CMP]; |
| 191 | u32 addr_type[ETM_MAX_ADDR_CMP]; |
| 192 | u8 cntr_idx; |
| 193 | u32 cntr_rld_val[ETM_MAX_CNTR]; |
| 194 | u32 cntr_event[ETM_MAX_CNTR]; |
| 195 | u32 cntr_rld_event[ETM_MAX_CNTR]; |
| 196 | u32 cntr_val[ETM_MAX_CNTR]; |
| 197 | u32 seq_12_event; |
| 198 | u32 seq_21_event; |
| 199 | u32 seq_23_event; |
| 200 | u32 seq_31_event; |
| 201 | u32 seq_32_event; |
| 202 | u32 seq_13_event; |
| 203 | u32 seq_curr_state; |
| 204 | u8 ctxid_idx; |
Chunyan Zhang | 414a141 | 2015-07-31 09:37:24 -0600 | [diff] [blame] | 205 | u32 ctxid_pid[ETM_MAX_CTXID_CMP]; |
Chunyan Zhang | a440617 | 2015-07-31 09:37:27 -0600 | [diff] [blame] | 206 | u32 ctxid_vpid[ETM_MAX_CTXID_CMP]; |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 207 | u32 ctxid_mask; |
| 208 | u32 sync_freq; |
| 209 | u32 timestamp_event; |
| 210 | }; |
| 211 | |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 212 | /** |
| 213 | * struct etm_drvdata - specifics associated to an ETM component |
| 214 | * @base: memory mapped base address for this component. |
| 215 | * @dev: the device entity associated to this component. |
| 216 | * @atclk: optional clock for the core parts of the ETM. |
| 217 | * @csdev: component vitals needed by the framework. |
| 218 | * @spinlock: only one at a time pls. |
| 219 | * @cpu: the cpu this component is affined to. |
| 220 | * @port_size: port size as reported by ETMCR bit 4-6 and 21. |
| 221 | * @arch: ETM/PTM version number. |
| 222 | * @use_cpu14: true if management registers need to be accessed via CP14. |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 223 | * @mode: this tracer's mode, i.e sysFS, Perf or disabled. |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 224 | * @sticky_enable: true if ETM base configuration has been done. |
| 225 | * @boot_enable:true if we should start tracing at boot time. |
| 226 | * @os_unlock: true if access to management registers is allowed. |
| 227 | * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR. |
| 228 | * @nr_cntr: Number of counters as found in ETMCCR bit 13-15. |
| 229 | * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19. |
| 230 | * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22. |
| 231 | * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25. |
| 232 | * @etmccr: value of register ETMCCR. |
| 233 | * @etmccer: value of register ETMCCER. |
| 234 | * @traceid: value of the current ID for this component. |
| 235 | * @config: structure holding configuration parameters. |
| 236 | */ |
| 237 | struct etm_drvdata { |
| 238 | void __iomem *base; |
| 239 | struct device *dev; |
| 240 | struct clk *atclk; |
| 241 | struct coresight_device *csdev; |
| 242 | spinlock_t spinlock; |
| 243 | int cpu; |
| 244 | int port_size; |
| 245 | u8 arch; |
| 246 | bool use_cp14; |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 247 | local_t mode; |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 248 | bool sticky_enable; |
| 249 | bool boot_enable; |
| 250 | bool os_unlock; |
| 251 | u8 nr_addr_cmp; |
| 252 | u8 nr_cntr; |
| 253 | u8 nr_ext_inp; |
| 254 | u8 nr_ext_out; |
| 255 | u8 nr_ctxid_cmp; |
| 256 | u32 etmccr; |
| 257 | u32 etmccer; |
| 258 | u32 traceid; |
| 259 | struct etm_config config; |
| 260 | }; |
| 261 | |
Mathieu Poirier | c1f8e57 | 2016-02-17 17:51:48 -0700 | [diff] [blame] | 262 | static inline void etm_writel(struct etm_drvdata *drvdata, |
| 263 | u32 val, u32 off) |
| 264 | { |
| 265 | if (drvdata->use_cp14) { |
| 266 | if (etm_writel_cp14(off, val)) { |
| 267 | dev_err(drvdata->dev, |
| 268 | "invalid CP14 access to ETM reg: %#x", off); |
| 269 | } |
| 270 | } else { |
| 271 | writel_relaxed(val, drvdata->base + off); |
| 272 | } |
| 273 | } |
| 274 | |
| 275 | static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off) |
| 276 | { |
| 277 | u32 val; |
| 278 | |
| 279 | if (drvdata->use_cp14) { |
| 280 | if (etm_readl_cp14(off, &val)) { |
| 281 | dev_err(drvdata->dev, |
| 282 | "invalid CP14 access to ETM reg: %#x", off); |
| 283 | } |
| 284 | } else { |
| 285 | val = readl_relaxed(drvdata->base + off); |
| 286 | } |
| 287 | |
| 288 | return val; |
| 289 | } |
Mathieu Poirier | c04148e | 2016-02-17 17:51:49 -0700 | [diff] [blame] | 290 | |
| 291 | extern const struct attribute_group *coresight_etm_groups[]; |
| 292 | int etm_get_trace_id(struct etm_drvdata *drvdata); |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 293 | void etm_set_default(struct etm_config *config); |
Mathieu Poirier | 2127154 | 2016-02-17 17:51:56 -0700 | [diff] [blame] | 294 | void etm_config_trace_mode(struct etm_config *config); |
Mathieu Poirier | 1925a47 | 2016-02-17 17:51:51 -0700 | [diff] [blame] | 295 | struct etm_config *get_etm_config(struct etm_drvdata *drvdata); |
Pratik Patel | a939fc5 | 2014-11-03 11:07:41 -0700 | [diff] [blame] | 296 | #endif |