Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mm/proc-v7.S |
| 3 | * |
| 4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This is the "shell" of the ARMv7 processor support. |
| 11 | */ |
Tim Abbott | 991da17 | 2009-04-27 14:02:22 -0400 | [diff] [blame] | 12 | #include <linux/init.h> |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 13 | #include <linux/linkage.h> |
| 14 | #include <asm/assembler.h> |
| 15 | #include <asm/asm-offsets.h> |
Russell King | 5ec9407 | 2008-09-07 19:15:31 +0100 | [diff] [blame] | 16 | #include <asm/hwcap.h> |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 17 | #include <asm/pgtable-hwdef.h> |
| 18 | #include <asm/pgtable.h> |
| 19 | |
| 20 | #include "proc-macros.S" |
| 21 | |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 22 | #define TTB_S (1 << 1) |
Jon Callan | 73b63ef | 2008-11-06 13:23:09 +0000 | [diff] [blame] | 23 | #define TTB_RGN_NC (0 << 3) |
| 24 | #define TTB_RGN_OC_WBWA (1 << 3) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 25 | #define TTB_RGN_OC_WT (2 << 3) |
| 26 | #define TTB_RGN_OC_WB (3 << 3) |
Tony Thompson | ba3c026 | 2009-05-30 14:00:15 +0100 | [diff] [blame] | 27 | #define TTB_NOS (1 << 5) |
| 28 | #define TTB_IRGN_NC ((0 << 0) | (0 << 6)) |
| 29 | #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) |
| 30 | #define TTB_IRGN_WT ((1 << 0) | (0 << 6)) |
| 31 | #define TTB_IRGN_WB ((1 << 0) | (1 << 6)) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 32 | |
Tony Thompson | ba3c026 | 2009-05-30 14:00:15 +0100 | [diff] [blame] | 33 | /* PTWs cacheable, inner WB not shareable, outer WB not shareable */ |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 34 | #define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB |
| 35 | #define PMD_FLAGS_UP PMD_SECT_WB |
| 36 | |
Tony Thompson | ba3c026 | 2009-05-30 14:00:15 +0100 | [diff] [blame] | 37 | /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 38 | #define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA |
| 39 | #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S |
Jon Callan | 73b63ef | 2008-11-06 13:23:09 +0000 | [diff] [blame] | 40 | |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 41 | ENTRY(cpu_v7_proc_init) |
| 42 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 43 | ENDPROC(cpu_v7_proc_init) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 44 | |
| 45 | ENTRY(cpu_v7_proc_fin) |
Tony Lindgren | 1f667c6 | 2010-01-19 17:01:33 +0100 | [diff] [blame] | 46 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
| 47 | bic r0, r0, #0x1000 @ ...i............ |
| 48 | bic r0, r0, #0x0006 @ .............ca. |
| 49 | mcr p15, 0, r0, c1, c0, 0 @ disable caches |
Russell King | 9ca03a2 | 2010-07-26 12:22:12 +0100 | [diff] [blame] | 50 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 51 | ENDPROC(cpu_v7_proc_fin) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 52 | |
| 53 | /* |
| 54 | * cpu_v7_reset(loc) |
| 55 | * |
| 56 | * Perform a soft reset of the system. Put the CPU into the |
| 57 | * same state as it would be if it had been reset, and branch |
| 58 | * to what would be the reset vector. |
| 59 | * |
| 60 | * - loc - location to jump to for soft reset |
Will Deacon | f4daf06 | 2011-06-06 12:27:34 +0100 | [diff] [blame] | 61 | * |
| 62 | * This code must be executed using a flat identity mapping with |
| 63 | * caches disabled. |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 64 | */ |
| 65 | .align 5 |
Will Deacon | 1a4baaf | 2011-11-15 13:25:04 +0000 | [diff] [blame^] | 66 | .pushsection .idmap.text, "ax" |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 67 | ENTRY(cpu_v7_reset) |
Will Deacon | f4daf06 | 2011-06-06 12:27:34 +0100 | [diff] [blame] | 68 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register |
| 69 | bic r1, r1, #0x1 @ ...............m |
Will Deacon | 0f81bb6 | 2011-08-26 16:34:51 +0100 | [diff] [blame] | 70 | THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) |
Will Deacon | f4daf06 | 2011-06-06 12:27:34 +0100 | [diff] [blame] | 71 | mcr p15, 0, r1, c1, c0, 0 @ disable MMU |
| 72 | isb |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 73 | mov pc, r0 |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 74 | ENDPROC(cpu_v7_reset) |
Will Deacon | 1a4baaf | 2011-11-15 13:25:04 +0000 | [diff] [blame^] | 75 | .popsection |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * cpu_v7_do_idle() |
| 79 | * |
| 80 | * Idle the processor (eg, wait for interrupt). |
| 81 | * |
| 82 | * IRQs are already disabled. |
| 83 | */ |
| 84 | ENTRY(cpu_v7_do_idle) |
Catalin Marinas | 8553cb6 | 2008-11-10 14:14:11 +0000 | [diff] [blame] | 85 | dsb @ WFI may enter a low-power mode |
Catalin Marinas | 000b502 | 2008-10-03 11:09:10 +0100 | [diff] [blame] | 86 | wfi |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 87 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 88 | ENDPROC(cpu_v7_do_idle) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 89 | |
| 90 | ENTRY(cpu_v7_dcache_clean_area) |
| 91 | #ifndef TLB_CAN_READ_FROM_L1_CACHE |
| 92 | dcache_line_size r2, r3 |
| 93 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
| 94 | add r0, r0, r2 |
| 95 | subs r1, r1, r2 |
| 96 | bhi 1b |
| 97 | dsb |
| 98 | #endif |
| 99 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 100 | ENDPROC(cpu_v7_dcache_clean_area) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 101 | |
| 102 | /* |
| 103 | * cpu_v7_switch_mm(pgd_phys, tsk) |
| 104 | * |
| 105 | * Set the translation table base pointer to be pgd_phys |
| 106 | * |
| 107 | * - pgd_phys - physical address of new TTB |
| 108 | * |
| 109 | * It is assumed that: |
| 110 | * - we are not using split page tables |
| 111 | */ |
| 112 | ENTRY(cpu_v7_switch_mm) |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 113 | #ifdef CONFIG_MMU |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 114 | mov r2, #0 |
| 115 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 116 | ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) |
| 117 | ALT_UP(orr r0, r0, #TTB_FLAGS_UP) |
Catalin Marinas | 7ce236f | 2009-04-30 17:06:09 +0100 | [diff] [blame] | 118 | #ifdef CONFIG_ARM_ERRATA_430973 |
| 119 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
| 120 | #endif |
Russell King | 07989b7 | 2011-06-09 10:10:27 +0100 | [diff] [blame] | 121 | #ifdef CONFIG_ARM_ERRATA_754322 |
| 122 | dsb |
| 123 | #endif |
| 124 | mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID |
| 125 | isb |
| 126 | 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 127 | isb |
Will Deacon | fcbdc5fe | 2011-02-28 18:15:16 +0100 | [diff] [blame] | 128 | #ifdef CONFIG_ARM_ERRATA_754322 |
| 129 | dsb |
| 130 | #endif |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 131 | mcr p15, 0, r1, c13, c0, 1 @ set context ID |
| 132 | isb |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 133 | #endif |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 134 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 135 | ENDPROC(cpu_v7_switch_mm) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 136 | |
| 137 | /* |
| 138 | * cpu_v7_set_pte_ext(ptep, pte) |
| 139 | * |
| 140 | * Set a level 2 translation table entry. |
| 141 | * |
| 142 | * - ptep - pointer to level 2 translation table entry |
Russell King | d30e45e | 2010-11-16 00:16:01 +0000 | [diff] [blame] | 143 | * (hardware version is stored at +2048 bytes) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 144 | * - pte - PTE value to store |
| 145 | * - ext - value for extended PTE bits |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 146 | */ |
| 147 | ENTRY(cpu_v7_set_pte_ext) |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 148 | #ifdef CONFIG_MMU |
Russell King | d30e45e | 2010-11-16 00:16:01 +0000 | [diff] [blame] | 149 | str r1, [r0] @ linux version |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 150 | |
| 151 | bic r3, r1, #0x000003f0 |
Russell King | 3f69c0c | 2008-09-15 17:23:10 +0100 | [diff] [blame] | 152 | bic r3, r3, #PTE_TYPE_MASK |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 153 | orr r3, r3, r2 |
| 154 | orr r3, r3, #PTE_EXT_AP0 | 2 |
| 155 | |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 156 | tst r1, #1 << 4 |
Russell King | 3f69c0c | 2008-09-15 17:23:10 +0100 | [diff] [blame] | 157 | orrne r3, r3, #PTE_EXT_TEX(1) |
| 158 | |
Russell King | 36bb94b | 2010-11-16 08:40:36 +0000 | [diff] [blame] | 159 | eor r1, r1, #L_PTE_DIRTY |
| 160 | tst r1, #L_PTE_RDONLY | L_PTE_DIRTY |
| 161 | orrne r3, r3, #PTE_EXT_APX |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 162 | |
| 163 | tst r1, #L_PTE_USER |
| 164 | orrne r3, r3, #PTE_EXT_AP1 |
Catalin Marinas | 247055a | 2010-09-13 16:03:21 +0100 | [diff] [blame] | 165 | #ifdef CONFIG_CPU_USE_DOMAINS |
| 166 | @ allow kernel read/write access to read-only user pages |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 167 | tstne r3, #PTE_EXT_APX |
| 168 | bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 |
Catalin Marinas | 247055a | 2010-09-13 16:03:21 +0100 | [diff] [blame] | 169 | #endif |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 170 | |
Russell King | 9522d7e | 2010-11-16 00:23:31 +0000 | [diff] [blame] | 171 | tst r1, #L_PTE_XN |
| 172 | orrne r3, r3, #PTE_EXT_XN |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 173 | |
Russell King | 3f69c0c | 2008-09-15 17:23:10 +0100 | [diff] [blame] | 174 | tst r1, #L_PTE_YOUNG |
| 175 | tstne r1, #L_PTE_PRESENT |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 176 | moveq r3, #0 |
| 177 | |
Dave Martin | 874d5d3 | 2011-01-14 00:43:01 +0100 | [diff] [blame] | 178 | ARM( str r3, [r0, #2048]! ) |
| 179 | THUMB( add r0, r0, #2048 ) |
| 180 | THUMB( str r3, [r0] ) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 181 | mcr p15, 0, r0, c7, c10, 1 @ flush_pte |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 182 | #endif |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 183 | mov pc, lr |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 184 | ENDPROC(cpu_v7_set_pte_ext) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 185 | |
Dave Martin | 78a8f3c | 2011-06-23 17:26:19 +0100 | [diff] [blame] | 186 | string cpu_v7_name, "ARMv7 Processor" |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 187 | .align |
| 188 | |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 189 | /* |
| 190 | * Memory region attributes with SCTLR.TRE=1 |
| 191 | * |
| 192 | * n = TEX[0],C,B |
| 193 | * TR = PRRR[2n+1:2n] - memory type |
| 194 | * IR = NMRR[2n+1:2n] - inner cacheable property |
| 195 | * OR = NMRR[2n+17:2n+16] - outer cacheable property |
| 196 | * |
| 197 | * n TR IR OR |
| 198 | * UNCACHED 000 00 |
| 199 | * BUFFERABLE 001 10 00 00 |
| 200 | * WRITETHROUGH 010 10 10 10 |
| 201 | * WRITEBACK 011 10 11 11 |
| 202 | * reserved 110 |
| 203 | * WRITEALLOC 111 10 01 01 |
| 204 | * DEV_SHARED 100 01 |
| 205 | * DEV_NONSHARED 100 01 |
| 206 | * DEV_WC 001 10 |
| 207 | * DEV_CACHED 011 10 |
| 208 | * |
| 209 | * Other attributes: |
| 210 | * |
| 211 | * DS0 = PRRR[16] = 0 - device shareable property |
| 212 | * DS1 = PRRR[17] = 1 - device shareable property |
| 213 | * NS0 = PRRR[18] = 0 - normal shareable property |
| 214 | * NS1 = PRRR[19] = 1 - normal shareable property |
| 215 | * NOS = PRRR[24+n] = 1 - not outer shareable |
| 216 | */ |
| 217 | .equ PRRR, 0xff0a81a8 |
| 218 | .equ NMRR, 0x40e040e0 |
| 219 | |
| 220 | /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ |
| 221 | .globl cpu_v7_suspend_size |
Russell King | 1aede68 | 2011-08-28 10:30:34 +0100 | [diff] [blame] | 222 | .equ cpu_v7_suspend_size, 4 * 7 |
Arnd Bergmann | 15e0d9e | 2011-10-01 21:09:39 +0200 | [diff] [blame] | 223 | #ifdef CONFIG_ARM_CPU_SUSPEND |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 224 | ENTRY(cpu_v7_do_suspend) |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 225 | stmfd sp!, {r4 - r10, lr} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 226 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID |
Russell King | 1aede68 | 2011-08-28 10:30:34 +0100 | [diff] [blame] | 227 | mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID |
| 228 | stmia r0!, {r4 - r5} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 229 | mrc p15, 0, r6, c3, c0, 0 @ Domain ID |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 230 | mrc p15, 0, r7, c2, c0, 1 @ TTB 1 |
| 231 | mrc p15, 0, r8, c1, c0, 0 @ Control register |
| 232 | mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register |
| 233 | mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control |
| 234 | stmia r0, {r6 - r10} |
| 235 | ldmfd sp!, {r4 - r10, pc} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 236 | ENDPROC(cpu_v7_do_suspend) |
| 237 | |
| 238 | ENTRY(cpu_v7_do_resume) |
| 239 | mov ip, #0 |
| 240 | mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs |
| 241 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache |
Russell King | 1aede68 | 2011-08-28 10:30:34 +0100 | [diff] [blame] | 242 | mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID |
| 243 | ldmia r0!, {r4 - r5} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 244 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID |
Russell King | 1aede68 | 2011-08-28 10:30:34 +0100 | [diff] [blame] | 245 | mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 246 | ldmia r0, {r6 - r10} |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 247 | mcr p15, 0, r6, c3, c0, 0 @ Domain ID |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 248 | ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) |
| 249 | ALT_UP(orr r1, r1, #TTB_FLAGS_UP) |
| 250 | mcr p15, 0, r1, c2, c0, 0 @ TTB 0 |
| 251 | mcr p15, 0, r7, c2, c0, 1 @ TTB 1 |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 252 | mcr p15, 0, ip, c2, c0, 2 @ TTB control register |
Russell King | 2590415 | 2011-08-26 22:44:59 +0100 | [diff] [blame] | 253 | mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 254 | teq r4, r9 @ Is it already set? |
| 255 | mcrne p15, 0, r9, c1, c0, 1 @ No, so write it |
| 256 | mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 257 | ldr r4, =PRRR @ PRRR |
| 258 | ldr r5, =NMRR @ NMRR |
| 259 | mcr p15, 0, r4, c10, c2, 0 @ write PRRR |
| 260 | mcr p15, 0, r5, c10, c2, 1 @ write NMRR |
| 261 | isb |
Russell King | f35235a | 2011-08-27 00:37:38 +0100 | [diff] [blame] | 262 | dsb |
Russell King | de8e71c | 2011-08-27 22:39:09 +0100 | [diff] [blame] | 263 | mov r0, r8 @ control register |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 264 | b cpu_resume_mmu |
| 265 | ENDPROC(cpu_v7_do_resume) |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 266 | #endif |
| 267 | |
Russell King | 5085f3f | 2010-10-01 15:37:05 +0100 | [diff] [blame] | 268 | __CPUINIT |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 269 | |
| 270 | /* |
| 271 | * __v7_setup |
| 272 | * |
| 273 | * Initialise TLB, Caches, and MMU state ready to switch the MMU |
| 274 | * on. Return in r0 the new CP15 C1 control register setting. |
| 275 | * |
| 276 | * We automatically detect if we have a Harvard cache, and use the |
| 277 | * Harvard cache control instructions insead of the unified cache |
| 278 | * control instructions. |
| 279 | * |
| 280 | * This should be able to cover all ARMv7 cores. |
| 281 | * |
| 282 | * It is assumed that: |
| 283 | * - cache type register is implemented |
| 284 | */ |
Pawel Moll | 15eb169 | 2011-05-20 14:39:29 +0100 | [diff] [blame] | 285 | __v7_ca5mp_setup: |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 286 | __v7_ca9mp_setup: |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 287 | mov r10, #(1 << 0) @ TLB ops broadcasting |
| 288 | b 1f |
| 289 | __v7_ca15mp_setup: |
| 290 | mov r10, #0 |
| 291 | 1: |
Jon Callan | 73b63ef | 2008-11-06 13:23:09 +0000 | [diff] [blame] | 292 | #ifdef CONFIG_SMP |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 293 | ALT_SMP(mrc p15, 0, r0, c1, c0, 1) |
| 294 | ALT_UP(mov r0, #(1 << 6)) @ fake it for UP |
Tony Thompson | 1b3a02eb | 2009-11-04 12:16:38 +0000 | [diff] [blame] | 295 | tst r0, #(1 << 6) @ SMP/nAMP mode enabled? |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 296 | orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode |
| 297 | orreq r0, r0, r10 @ Enable CPU-specific SMP bits |
| 298 | mcreq p15, 0, r0, c1, c0, 1 |
Jon Callan | 73b63ef | 2008-11-06 13:23:09 +0000 | [diff] [blame] | 299 | #endif |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 300 | __v7_setup: |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 301 | adr r12, __v7_setup_stack @ the local stack |
| 302 | stmia r12, {r0-r5, r7, r9, r11, lr} |
| 303 | bl v7_flush_dcache_all |
| 304 | ldmia r12, {r0-r5, r7, r9, r11, lr} |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 305 | |
| 306 | mrc p15, 0, r0, c0, c0, 0 @ read main ID register |
| 307 | and r10, r0, #0xff000000 @ ARM? |
| 308 | teq r10, #0x41000000 |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 309 | bne 3f |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 310 | and r5, r0, #0x00f00000 @ variant |
| 311 | and r6, r0, #0x0000000f @ revision |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 312 | orr r6, r6, r5, lsr #20-4 @ combine variant and revision |
| 313 | ubfx r0, r0, #4, #12 @ primary part number |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 314 | |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 315 | /* Cortex-A8 Errata */ |
| 316 | ldr r10, =0x00000c08 @ Cortex-A8 primary part number |
| 317 | teq r0, r10 |
| 318 | bne 2f |
Catalin Marinas | 7ce236f | 2009-04-30 17:06:09 +0100 | [diff] [blame] | 319 | #ifdef CONFIG_ARM_ERRATA_430973 |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 320 | teq r5, #0x00100000 @ only present in r1p* |
| 321 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register |
| 322 | orreq r10, r10, #(1 << 6) @ set IBE to 1 |
| 323 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register |
Catalin Marinas | 7ce236f | 2009-04-30 17:06:09 +0100 | [diff] [blame] | 324 | #endif |
Catalin Marinas | 855c551 | 2009-04-30 17:06:15 +0100 | [diff] [blame] | 325 | #ifdef CONFIG_ARM_ERRATA_458693 |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 326 | teq r6, #0x20 @ only present in r2p0 |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 327 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register |
| 328 | orreq r10, r10, #(1 << 5) @ set L1NEON to 1 |
| 329 | orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 |
| 330 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register |
Catalin Marinas | 855c551 | 2009-04-30 17:06:15 +0100 | [diff] [blame] | 331 | #endif |
Catalin Marinas | 0516e46 | 2009-04-30 17:06:20 +0100 | [diff] [blame] | 332 | #ifdef CONFIG_ARM_ERRATA_460075 |
Will Deacon | 6491848 | 2010-09-14 09:50:03 +0100 | [diff] [blame] | 333 | teq r6, #0x20 @ only present in r2p0 |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 334 | mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register |
| 335 | tsteq r10, #1 << 22 |
| 336 | orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit |
| 337 | mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register |
Catalin Marinas | 0516e46 | 2009-04-30 17:06:20 +0100 | [diff] [blame] | 338 | #endif |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 339 | b 3f |
Russell King | 1946d6e | 2009-06-01 12:50:33 +0100 | [diff] [blame] | 340 | |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 341 | /* Cortex-A9 Errata */ |
| 342 | 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number |
| 343 | teq r0, r10 |
| 344 | bne 3f |
| 345 | #ifdef CONFIG_ARM_ERRATA_742230 |
| 346 | cmp r6, #0x22 @ only present up to r2p2 |
| 347 | mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 348 | orrle r10, r10, #1 << 4 @ set bit #4 |
| 349 | mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register |
| 350 | #endif |
Will Deacon | a672e99 | 2010-09-14 09:53:02 +0100 | [diff] [blame] | 351 | #ifdef CONFIG_ARM_ERRATA_742231 |
| 352 | teq r6, #0x20 @ present in r2p0 |
| 353 | teqne r6, #0x21 @ present in r2p1 |
| 354 | teqne r6, #0x22 @ present in r2p2 |
| 355 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 356 | orreq r10, r10, #1 << 12 @ set bit #12 |
| 357 | orreq r10, r10, #1 << 22 @ set bit #22 |
| 358 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register |
| 359 | #endif |
Will Deacon | 475d92f | 2010-09-28 14:02:02 +0100 | [diff] [blame] | 360 | #ifdef CONFIG_ARM_ERRATA_743622 |
| 361 | teq r6, #0x20 @ present in r2p0 |
| 362 | teqne r6, #0x21 @ present in r2p1 |
| 363 | teqne r6, #0x22 @ present in r2p2 |
| 364 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 365 | orreq r10, r10, #1 << 6 @ set bit #6 |
| 366 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register |
| 367 | #endif |
Will Deacon | 9a27c27 | 2011-02-18 16:36:35 +0100 | [diff] [blame] | 368 | #ifdef CONFIG_ARM_ERRATA_751472 |
| 369 | cmp r6, #0x30 @ present prior to r3p0 |
| 370 | mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register |
| 371 | orrlt r10, r10, #1 << 11 @ set bit #11 |
| 372 | mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register |
| 373 | #endif |
Will Deacon | 9f05027 | 2010-09-14 09:51:43 +0100 | [diff] [blame] | 374 | |
| 375 | 3: mov r10, #0 |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 376 | #ifdef HARVARD_CACHE |
| 377 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |
| 378 | #endif |
| 379 | dsb |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 380 | #ifdef CONFIG_MMU |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 381 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
| 382 | mcr p15, 0, r10, c2, c0, 2 @ TTB control register |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 383 | ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) |
| 384 | ALT_UP(orr r4, r4, #TTB_FLAGS_UP) |
Catalin Marinas | d427958 | 2011-05-26 11:22:44 +0100 | [diff] [blame] | 385 | ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) |
| 386 | ALT_UP(orr r8, r8, #TTB_FLAGS_UP) |
| 387 | mcr p15, 0, r8, c2, c0, 1 @ load TTB1 |
Russell King | f6b0fa0 | 2011-02-06 15:48:39 +0000 | [diff] [blame] | 388 | ldr r5, =PRRR @ PRRR |
| 389 | ldr r6, =NMRR @ NMRR |
Russell King | 3f69c0c | 2008-09-15 17:23:10 +0100 | [diff] [blame] | 390 | mcr p15, 0, r5, c10, c2, 0 @ write PRRR |
| 391 | mcr p15, 0, r6, c10, c2, 1 @ write NMRR |
Catalin Marinas | bdaaaec | 2009-07-24 12:35:06 +0100 | [diff] [blame] | 392 | #endif |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 393 | adr r5, v7_crval |
| 394 | ldmia r5, {r5, r6} |
Catalin Marinas | 2658485 | 2009-05-30 14:00:18 +0100 | [diff] [blame] | 395 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
| 396 | orr r6, r6, #1 << 25 @ big-endian page tables |
| 397 | #endif |
Leif Lindholm | 64d2dc3 | 2010-09-16 18:00:47 +0100 | [diff] [blame] | 398 | #ifdef CONFIG_SWP_EMULATE |
| 399 | orr r5, r5, #(1 << 10) @ set SW bit in "clear" |
| 400 | bic r6, r6, #(1 << 10) @ clear it in "mmuset" |
| 401 | #endif |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 402 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
| 403 | bic r0, r0, r5 @ clear bits them |
| 404 | orr r0, r0, r6 @ set them |
Catalin Marinas | 347c8b7 | 2009-07-24 12:32:56 +0100 | [diff] [blame] | 405 | THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 406 | mov pc, lr @ return to head.S:__ret |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 407 | ENDPROC(__v7_setup) |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 408 | |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 409 | /* AT |
Catalin Marinas | 213fb2a | 2009-05-30 14:00:16 +0100 | [diff] [blame] | 410 | * TFR EV X F I D LR S |
| 411 | * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM |
Russell King | b1cce6b | 2008-11-04 10:52:28 +0000 | [diff] [blame] | 412 | * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced |
Catalin Marinas | 213fb2a | 2009-05-30 14:00:16 +0100 | [diff] [blame] | 413 | * 1 0 110 0011 1100 .111 1101 < we want |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 414 | */ |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 415 | .type v7_crval, #object |
| 416 | v7_crval: |
Catalin Marinas | 213fb2a | 2009-05-30 14:00:16 +0100 | [diff] [blame] | 417 | crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 418 | |
| 419 | __v7_setup_stack: |
| 420 | .space 4 * 11 @ 11 registers |
| 421 | |
Russell King | 5085f3f | 2010-10-01 15:37:05 +0100 | [diff] [blame] | 422 | __INITDATA |
| 423 | |
Dave Martin | 78a8f3c | 2011-06-23 17:26:19 +0100 | [diff] [blame] | 424 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
| 425 | define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 426 | |
Russell King | 5085f3f | 2010-10-01 15:37:05 +0100 | [diff] [blame] | 427 | .section ".rodata" |
| 428 | |
Dave Martin | 78a8f3c | 2011-06-23 17:26:19 +0100 | [diff] [blame] | 429 | string cpu_arch_name, "armv7" |
| 430 | string cpu_elf_name, "v7" |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 431 | .align |
| 432 | |
| 433 | .section ".proc.info.init", #alloc, #execinstr |
| 434 | |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 435 | /* |
| 436 | * Standard v7 proc info content |
| 437 | */ |
| 438 | .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 |
| 439 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ |
| 440 | PMD_FLAGS_SMP | \mm_mmuflags) |
| 441 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ |
| 442 | PMD_FLAGS_UP | \mm_mmuflags) |
| 443 | .long PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \ |
| 444 | PMD_SECT_AP_READ | \io_mmuflags |
| 445 | W(b) \initfunc |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 446 | .long cpu_arch_name |
| 447 | .long cpu_elf_name |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 448 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ |
| 449 | HWCAP_EDSP | HWCAP_TLS | \hwcaps |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 450 | .long cpu_v7_name |
| 451 | .long v7_processor_functions |
| 452 | .long v7wbi_tlb_fns |
| 453 | .long v6_user_fns |
| 454 | .long v7_cache_fns |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 455 | .endm |
| 456 | |
| 457 | /* |
Pawel Moll | 15eb169 | 2011-05-20 14:39:29 +0100 | [diff] [blame] | 458 | * ARM Ltd. Cortex A5 processor. |
| 459 | */ |
| 460 | .type __v7_ca5mp_proc_info, #object |
| 461 | __v7_ca5mp_proc_info: |
| 462 | .long 0x410fc050 |
| 463 | .long 0xff0ffff0 |
| 464 | __v7_proc __v7_ca5mp_setup |
| 465 | .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info |
| 466 | |
| 467 | /* |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 468 | * ARM Ltd. Cortex A9 processor. |
| 469 | */ |
| 470 | .type __v7_ca9mp_proc_info, #object |
| 471 | __v7_ca9mp_proc_info: |
| 472 | .long 0x410fc090 |
| 473 | .long 0xff0ffff0 |
| 474 | __v7_proc __v7_ca9mp_setup |
Daniel Walker | 14eff18 | 2010-09-17 16:42:10 +0100 | [diff] [blame] | 475 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info |
| 476 | |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 477 | /* |
Will Deacon | 7665d9d | 2011-01-12 17:10:45 +0000 | [diff] [blame] | 478 | * ARM Ltd. Cortex A15 processor. |
| 479 | */ |
| 480 | .type __v7_ca15mp_proc_info, #object |
| 481 | __v7_ca15mp_proc_info: |
| 482 | .long 0x410fc0f0 |
| 483 | .long 0xff0ffff0 |
| 484 | __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV |
| 485 | .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info |
| 486 | |
| 487 | /* |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 488 | * Match any ARMv7 processor core. |
| 489 | */ |
| 490 | .type __v7_proc_info, #object |
| 491 | __v7_proc_info: |
| 492 | .long 0x000f0000 @ Required ID value |
| 493 | .long 0x000f0000 @ Mask for ID |
Pawel Moll | dc939cd | 2011-05-20 14:39:28 +0100 | [diff] [blame] | 494 | __v7_proc __v7_setup |
Catalin Marinas | bbe8888 | 2007-05-08 22:27:46 +0100 | [diff] [blame] | 495 | .size __v7_proc_info, . - __v7_proc_info |