Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
Boris BREZILLON | 2edb90a | 2013-10-11 09:37:45 +0200 | [diff] [blame] | 2 | * include/linux/clk/at91_pmc.h |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People |
| 6 | * |
| 7 | * Power Management Controller (PMC) - System peripherals registers. |
| 8 | * Based on AT91RM9200 datasheet revision E. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | */ |
| 15 | |
| 16 | #ifndef AT91_PMC_H |
| 17 | #define AT91_PMC_H |
| 18 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 19 | #ifndef __ASSEMBLY__ |
| 20 | extern void __iomem *at91_pmc_base; |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 21 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 22 | #define at91_pmc_read(field) \ |
| 23 | __raw_readl(at91_pmc_base + field) |
| 24 | |
| 25 | #define at91_pmc_write(field, value) \ |
| 26 | __raw_writel(value, at91_pmc_base + field) |
| 27 | #else |
Nicolas Ferre | 67f3af4 | 2012-04-10 14:30:24 +0200 | [diff] [blame] | 28 | .extern at91_pmc_base |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 29 | #endif |
| 30 | |
| 31 | #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ |
| 32 | #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ |
| 33 | |
| 34 | #define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 35 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ |
| 36 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ |
| 37 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ |
| 38 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ |
| 39 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 40 | #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ |
| 41 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ |
| 42 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ |
| 43 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ |
| 44 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ |
Andrew Victor | 5e38efa | 2009-12-15 21:57:27 +0100 | [diff] [blame] | 45 | #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 46 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ |
| 47 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ |
| 48 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 49 | #define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ |
| 50 | #define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ |
| 51 | #define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 52 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 53 | #define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 54 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ |
| 55 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ |
| 56 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 57 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 58 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 59 | #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ |
Nicolas Ferre | cbd5c78 | 2011-03-10 19:08:53 +0100 | [diff] [blame] | 60 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
| 61 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ |
| 62 | #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ |
| 63 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ |
| 64 | #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ |
| 65 | #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ |
| 66 | #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 67 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 68 | #define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 69 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ |
| 70 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ |
| 71 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 72 | #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ |
| 73 | #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 74 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ |
| 75 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ |
| 76 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ |
| 77 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ |
Ludovic Desroches | 8f4b479 | 2013-03-22 13:24:12 +0000 | [diff] [blame] | 78 | #define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) |
| 79 | #define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ |
| 80 | #define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 81 | #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ |
| 82 | #define AT91_PMC_USBDIV_1 (0 << 28) |
| 83 | #define AT91_PMC_USBDIV_2 (1 << 28) |
| 84 | #define AT91_PMC_USBDIV_4 (2 << 28) |
| 85 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ |
| 86 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 87 | #define AT91_PMC_MCKR 0x30 /* Master Clock Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 88 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ |
| 89 | #define AT91_PMC_CSS_SLOW (0 << 0) |
| 90 | #define AT91_PMC_CSS_MAIN (1 << 0) |
| 91 | #define AT91_PMC_CSS_PLLA (2 << 0) |
| 92 | #define AT91_PMC_CSS_PLLB (3 << 0) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 93 | #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ |
Nicolas Ferre | cbd5c78 | 2011-03-10 19:08:53 +0100 | [diff] [blame] | 94 | #define PMC_PRES_OFFSET 2 |
| 95 | #define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ |
| 96 | #define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) |
| 97 | #define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) |
| 98 | #define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) |
| 99 | #define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) |
| 100 | #define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) |
| 101 | #define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) |
| 102 | #define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) |
| 103 | #define PMC_ALT_PRES_OFFSET 4 |
| 104 | #define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ |
| 105 | #define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) |
| 106 | #define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) |
| 107 | #define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) |
| 108 | #define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) |
| 109 | #define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) |
| 110 | #define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) |
| 111 | #define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 112 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ |
| 113 | #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ |
| 114 | #define AT91RM9200_PMC_MDIV_2 (1 << 8) |
| 115 | #define AT91RM9200_PMC_MDIV_3 (2 << 8) |
| 116 | #define AT91RM9200_PMC_MDIV_4 (3 << 8) |
Jean-Christophe PLAGNIOL-VILLARD | 9918cea | 2012-01-26 14:07:09 +0100 | [diff] [blame] | 117 | #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 118 | #define AT91SAM9_PMC_MDIV_2 (1 << 8) |
| 119 | #define AT91SAM9_PMC_MDIV_4 (2 << 8) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 120 | #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ |
| 121 | #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 122 | #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ |
| 123 | #define AT91_PMC_PDIV_1 (0 << 12) |
| 124 | #define AT91_PMC_PDIV_2 (1 << 12) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 125 | #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ |
| 126 | #define AT91_PMC_PLLADIV2_OFF (0 << 12) |
| 127 | #define AT91_PMC_PLLADIV2_ON (1 << 12) |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 128 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 129 | #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 130 | #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ |
| 131 | #define AT91_PMC_USBS_PLLA (0 << 0) |
| 132 | #define AT91_PMC_USBS_UPLL (1 << 0) |
Nicolas Ferre | d04e5b6 | 2013-06-24 18:07:34 +0200 | [diff] [blame] | 133 | #define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 134 | #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ |
Nicolas Ferre | d04e5b6 | 2013-06-24 18:07:34 +0200 | [diff] [blame] | 135 | #define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8) |
| 136 | #define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8) |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 137 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 138 | #define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ |
Nicolas Ferre | cbd5c78 | 2011-03-10 19:08:53 +0100 | [diff] [blame] | 139 | #define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ |
| 140 | #define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ |
| 141 | #define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) |
| 142 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 143 | #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ |
Nicolas Ferre | cbd5c78 | 2011-03-10 19:08:53 +0100 | [diff] [blame] | 144 | #define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ |
| 145 | #define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 146 | #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ |
| 147 | #define AT91_PMC_CSSMCK_CSS (0 << 8) |
| 148 | #define AT91_PMC_CSSMCK_MCK (1 << 8) |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 149 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 150 | #define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ |
| 151 | #define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ |
| 152 | #define AT91_PMC_SR 0x68 /* Status Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 153 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ |
| 154 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ |
| 155 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ |
| 156 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ |
Jean-Christophe PLAGNIOL-VILLARD | 9918cea | 2012-01-26 14:07:09 +0100 | [diff] [blame] | 157 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 158 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ |
| 159 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ |
| 160 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ |
| 161 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ |
Nicolas Ferre | cbd5c78 | 2011-03-10 19:08:53 +0100 | [diff] [blame] | 162 | #define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ |
| 163 | #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ |
| 164 | #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 165 | #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 166 | |
Boris BREZILLON | 1a748d2 | 2013-10-11 10:48:26 +0200 | [diff] [blame^] | 167 | #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ |
| 168 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 169 | #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ |
Nicolas Ferre | cbd5c78 | 2011-03-10 19:08:53 +0100 | [diff] [blame] | 170 | #define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ |
| 171 | #define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ |
| 172 | #define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ |
Stelian Pop | 7be90a6 | 2008-10-22 13:52:08 +0100 | [diff] [blame] | 173 | |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 174 | #define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ |
Nicolas Ferre | cbd5c78 | 2011-03-10 19:08:53 +0100 | [diff] [blame] | 175 | #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ |
| 176 | #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ |
| 177 | |
Ludovic Desroches | 8f4b479 | 2013-03-22 13:24:12 +0000 | [diff] [blame] | 178 | #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ |
| 179 | #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ |
| 180 | #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ |
| 181 | |
| 182 | #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ |
Nicolas Ferre | cbd5c78 | 2011-03-10 19:08:53 +0100 | [diff] [blame] | 183 | #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ |
Ludovic Desroches | 8f4b479 | 2013-03-22 13:24:12 +0000 | [diff] [blame] | 184 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ |
| 185 | #define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ |
| 186 | #define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ |
Josh Wu | 144ea15 | 2013-05-23 10:18:48 +0000 | [diff] [blame] | 187 | #define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ |
| 188 | #define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ |
| 189 | #define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ |
Nicolas Ferre | cbd5c78 | 2011-03-10 19:08:53 +0100 | [diff] [blame] | 190 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ |
Stelian Pop | 7be90a6 | 2008-10-22 13:52:08 +0100 | [diff] [blame] | 191 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 192 | #endif |