blob: cc7eb8767b82b869a5f8862b20a222b819378e86 [file] [log] [blame]
Robert Jarzmikdc944362009-01-06 14:42:14 -08001/*
2 * Real Time Clock interface for XScale PXA27x and PXA3xx
3 *
4 * Copyright (C) 2008 Robert Jarzmik
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
Alessandro Zummo0417ce22009-01-06 14:42:15 -080022#include <linux/init.h>
Robert Jarzmikdc944362009-01-06 14:42:14 -080023#include <linux/platform_device.h>
24#include <linux/module.h>
25#include <linux/rtc.h>
26#include <linux/seq_file.h>
27#include <linux/interrupt.h>
Alessandro Zummo0417ce22009-01-06 14:42:15 -080028#include <linux/io.h>
Robert Jarzmikdc944362009-01-06 14:42:14 -080029
30#define TIMER_FREQ CLOCK_TICK_RATE
31#define RTC_DEF_DIVIDER (32768 - 1)
32#define RTC_DEF_TRIM 0
33#define MAXFREQ_PERIODIC 1000
34
35/*
36 * PXA Registers and bits definitions
37 */
38#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
39#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
40#define RTSR_PIAL (1 << 13) /* Periodic interrupt detected */
41#define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */
42#define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */
43#define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */
44#define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */
45#define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */
46#define RTSR_RDAL2 (1 << 6) /* RTC alarm2 detected */
47#define RTSR_RDALE1 (1 << 5) /* RTC alarm1 enable */
48#define RTSR_RDAL1 (1 << 4) /* RTC alarm1 detected */
49#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
50#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
51#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
52#define RTSR_AL (1 << 0) /* RTC alarm detected */
53#define RTSR_TRIG_MASK (RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
54 | RTSR_SWAL1 | RTSR_SWAL2)
55#define RYxR_YEAR_S 9
56#define RYxR_YEAR_MASK (0xfff << RYxR_YEAR_S)
57#define RYxR_MONTH_S 5
58#define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S)
59#define RYxR_DAY_MASK 0x1f
60#define RDxR_HOUR_S 12
61#define RDxR_HOUR_MASK (0x1f << RDxR_HOUR_S)
62#define RDxR_MIN_S 6
63#define RDxR_MIN_MASK (0x3f << RDxR_MIN_S)
64#define RDxR_SEC_MASK 0x3f
65
66#define RTSR 0x08
67#define RTTR 0x0c
68#define RDCR 0x10
69#define RYCR 0x14
70#define RDAR1 0x18
71#define RYAR1 0x1c
72#define RTCPICR 0x34
73#define PIAR 0x38
74
75#define rtc_readl(pxa_rtc, reg) \
76 __raw_readl((pxa_rtc)->base + (reg))
77#define rtc_writel(pxa_rtc, reg, value) \
78 __raw_writel((value), (pxa_rtc)->base + (reg))
79
80struct pxa_rtc {
81 struct resource *ress;
82 void __iomem *base;
83 int irq_1Hz;
84 int irq_Alrm;
85 struct rtc_device *rtc;
86 spinlock_t lock; /* Protects this structure */
87 struct rtc_time rtc_alarm;
88};
89
90static u32 ryxr_calc(struct rtc_time *tm)
91{
92 return ((tm->tm_year + 1900) << RYxR_YEAR_S)
93 | ((tm->tm_mon + 1) << RYxR_MONTH_S)
94 | tm->tm_mday;
95}
96
97static u32 rdxr_calc(struct rtc_time *tm)
98{
99 return (tm->tm_hour << RDxR_HOUR_S) | (tm->tm_min << RDxR_MIN_S)
100 | tm->tm_sec;
101}
102
103static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
104{
105 tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
106 tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
107 tm->tm_mday = (rycr & RYxR_DAY_MASK);
108 tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
109 tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
110 tm->tm_sec = rdcr & RDxR_SEC_MASK;
111}
112
113static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
114{
115 u32 rtsr;
116
117 rtsr = rtc_readl(pxa_rtc, RTSR);
118 rtsr &= ~RTSR_TRIG_MASK;
119 rtsr &= ~mask;
120 rtc_writel(pxa_rtc, RTSR, rtsr);
121}
122
123static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
124{
125 u32 rtsr;
126
127 rtsr = rtc_readl(pxa_rtc, RTSR);
128 rtsr &= ~RTSR_TRIG_MASK;
129 rtsr |= mask;
130 rtc_writel(pxa_rtc, RTSR, rtsr);
131}
132
133static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
134{
135 struct platform_device *pdev = to_platform_device(dev_id);
136 struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
137 u32 rtsr;
138 unsigned long events = 0;
139
140 spin_lock(&pxa_rtc->lock);
141
142 /* clear interrupt sources */
143 rtsr = rtc_readl(pxa_rtc, RTSR);
144 rtc_writel(pxa_rtc, RTSR, rtsr);
145
146 /* temporary disable rtc interrupts */
147 rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);
148
149 /* clear alarm interrupt if it has occurred */
150 if (rtsr & RTSR_RDAL1)
151 rtsr &= ~RTSR_RDALE1;
152
153 /* update irq data & counter */
154 if (rtsr & RTSR_RDAL1)
155 events |= RTC_AF | RTC_IRQF;
156 if (rtsr & RTSR_HZ)
157 events |= RTC_UF | RTC_IRQF;
158 if (rtsr & RTSR_PIAL)
159 events |= RTC_PF | RTC_IRQF;
160
161 rtc_update_irq(pxa_rtc->rtc, 1, events);
162
163 /* enable back rtc interrupts */
164 rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
165
166 spin_unlock(&pxa_rtc->lock);
167 return IRQ_HANDLED;
168}
169
170static int pxa_rtc_open(struct device *dev)
171{
172 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
173 int ret;
174
175 ret = request_irq(pxa_rtc->irq_1Hz, pxa_rtc_irq, IRQF_DISABLED,
176 "rtc 1Hz", dev);
177 if (ret < 0) {
178 dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_1Hz,
179 ret);
180 goto err_irq_1Hz;
181 }
182 ret = request_irq(pxa_rtc->irq_Alrm, pxa_rtc_irq, IRQF_DISABLED,
183 "rtc Alrm", dev);
184 if (ret < 0) {
185 dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_Alrm,
186 ret);
187 goto err_irq_Alrm;
188 }
189
190 return 0;
191
192err_irq_Alrm:
193 free_irq(pxa_rtc->irq_1Hz, dev);
194err_irq_1Hz:
195 return ret;
196}
197
198static void pxa_rtc_release(struct device *dev)
199{
200 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
201
202 spin_lock_irq(&pxa_rtc->lock);
203 rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
204 spin_unlock_irq(&pxa_rtc->lock);
205
206 free_irq(pxa_rtc->irq_Alrm, dev);
207 free_irq(pxa_rtc->irq_1Hz, dev);
208}
209
210static int pxa_periodic_irq_set_freq(struct device *dev, int freq)
211{
212 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
213 int period_ms;
214
215 if (freq < 1 || freq > MAXFREQ_PERIODIC)
216 return -EINVAL;
217
218 period_ms = 1000 / freq;
219 rtc_writel(pxa_rtc, PIAR, period_ms);
220
221 return 0;
222}
223
224static int pxa_periodic_irq_set_state(struct device *dev, int enabled)
225{
226 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
227
228 if (enabled)
229 rtsr_set_bits(pxa_rtc, RTSR_PIALE | RTSR_PICE);
230 else
231 rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_PICE);
232
233 return 0;
234}
235
236static int pxa_rtc_ioctl(struct device *dev, unsigned int cmd,
237 unsigned long arg)
238{
239 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
240 int ret = 0;
241
242 spin_lock_irq(&pxa_rtc->lock);
243 switch (cmd) {
244 case RTC_AIE_OFF:
245 rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
246 break;
247 case RTC_AIE_ON:
248 rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
249 break;
250 case RTC_UIE_OFF:
251 rtsr_clear_bits(pxa_rtc, RTSR_HZE);
252 break;
253 case RTC_UIE_ON:
254 rtsr_set_bits(pxa_rtc, RTSR_HZE);
255 break;
256 default:
257 ret = -ENOIOCTLCMD;
258 }
259
260 spin_unlock_irq(&pxa_rtc->lock);
261 return ret;
262}
263
264static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
265{
266 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
267 u32 rycr, rdcr;
268
269 rycr = rtc_readl(pxa_rtc, RYCR);
270 rdcr = rtc_readl(pxa_rtc, RDCR);
271
272 tm_calc(rycr, rdcr, tm);
273 return 0;
274}
275
276static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
277{
278 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
279
280 rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
281 rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
282
283 return 0;
284}
285
286static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
287{
288 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
289 u32 rtsr, ryar, rdar;
290
291 ryar = rtc_readl(pxa_rtc, RYAR1);
292 rdar = rtc_readl(pxa_rtc, RDAR1);
293 tm_calc(ryar, rdar, &alrm->time);
294
295 rtsr = rtc_readl(pxa_rtc, RTSR);
296 alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
297 alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
298 return 0;
299}
300
301static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
302{
303 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
304 u32 rtsr;
305
306 spin_lock_irq(&pxa_rtc->lock);
307
308 rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
309 rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
310
311 rtsr = rtc_readl(pxa_rtc, RTSR);
312 if (alrm->enabled)
313 rtsr |= RTSR_RDALE1;
314 else
315 rtsr &= ~RTSR_RDALE1;
316 rtc_writel(pxa_rtc, RTSR, rtsr);
317
318 spin_unlock_irq(&pxa_rtc->lock);
319
320 return 0;
321}
322
323static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
324{
325 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
326
327 seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
328 seq_printf(seq, "update_IRQ\t: %s\n",
329 (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
330 seq_printf(seq, "periodic_IRQ\t: %s\n",
331 (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
332 seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
333
334 return 0;
335}
336
337static const struct rtc_class_ops pxa_rtc_ops = {
338 .open = pxa_rtc_open,
339 .release = pxa_rtc_release,
340 .ioctl = pxa_rtc_ioctl,
341 .read_time = pxa_rtc_read_time,
342 .set_time = pxa_rtc_set_time,
343 .read_alarm = pxa_rtc_read_alarm,
344 .set_alarm = pxa_rtc_set_alarm,
345 .proc = pxa_rtc_proc,
346 .irq_set_state = pxa_periodic_irq_set_state,
347 .irq_set_freq = pxa_periodic_irq_set_freq,
348};
349
Alessandro Zummo0417ce22009-01-06 14:42:15 -0800350static int __init pxa_rtc_probe(struct platform_device *pdev)
Robert Jarzmikdc944362009-01-06 14:42:14 -0800351{
352 struct device *dev = &pdev->dev;
353 struct pxa_rtc *pxa_rtc;
354 int ret;
355 u32 rttr;
356
Robert Jarzmikdc944362009-01-06 14:42:14 -0800357 pxa_rtc = kzalloc(sizeof(struct pxa_rtc), GFP_KERNEL);
358 if (!pxa_rtc)
Alessandro Zummo0417ce22009-01-06 14:42:15 -0800359 return -ENOMEM;
360
361 spin_lock_init(&pxa_rtc->lock);
362 platform_set_drvdata(pdev, pxa_rtc);
Robert Jarzmikdc944362009-01-06 14:42:14 -0800363
364 ret = -ENXIO;
365 pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
366 if (!pxa_rtc->ress) {
367 dev_err(dev, "No I/O memory resource defined\n");
368 goto err_ress;
369 }
370
371 pxa_rtc->irq_1Hz = platform_get_irq(pdev, 0);
372 if (pxa_rtc->irq_1Hz < 0) {
373 dev_err(dev, "No 1Hz IRQ resource defined\n");
374 goto err_ress;
375 }
376 pxa_rtc->irq_Alrm = platform_get_irq(pdev, 1);
377 if (pxa_rtc->irq_Alrm < 0) {
378 dev_err(dev, "No alarm IRQ resource defined\n");
379 goto err_ress;
380 }
381
Robert Jarzmikdc944362009-01-06 14:42:14 -0800382 ret = -ENOMEM;
383 pxa_rtc->base = ioremap(pxa_rtc->ress->start,
Alessandro Zummo0417ce22009-01-06 14:42:15 -0800384 resource_size(pxa_rtc->ress));
Robert Jarzmikdc944362009-01-06 14:42:14 -0800385 if (!pxa_rtc->base) {
386 dev_err(&pdev->dev, "Unable to map pxa RTC I/O memory\n");
387 goto err_map;
388 }
389
390 /*
391 * If the clock divider is uninitialized then reset it to the
392 * default value to get the 1Hz clock.
393 */
394 if (rtc_readl(pxa_rtc, RTTR) == 0) {
395 rttr = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
396 rtc_writel(pxa_rtc, RTTR, rttr);
397 dev_warn(dev, "warning: initializing default clock"
398 " divider/trim value\n");
399 }
400
401 rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
Alessandro Zummo0417ce22009-01-06 14:42:15 -0800402
403 pxa_rtc->rtc = rtc_device_register("pxa-rtc", &pdev->dev, &pxa_rtc_ops,
404 THIS_MODULE);
405 ret = PTR_ERR(pxa_rtc->rtc);
406 if (IS_ERR(pxa_rtc->rtc)) {
407 dev_err(dev, "Failed to register RTC device -> %d\n", ret);
408 goto err_rtc_reg;
409 }
410
Robert Jarzmikdc944362009-01-06 14:42:14 -0800411 device_init_wakeup(dev, 1);
412
413 return 0;
414
Robert Jarzmikdc944362009-01-06 14:42:14 -0800415err_rtc_reg:
Alessandro Zummo0417ce22009-01-06 14:42:15 -0800416 iounmap(pxa_rtc->base);
Robert Jarzmikdc944362009-01-06 14:42:14 -0800417err_ress:
Alessandro Zummo0417ce22009-01-06 14:42:15 -0800418err_map:
Robert Jarzmikdc944362009-01-06 14:42:14 -0800419 kfree(pxa_rtc);
Robert Jarzmikdc944362009-01-06 14:42:14 -0800420 return ret;
421}
422
Alessandro Zummo0417ce22009-01-06 14:42:15 -0800423static int __exit pxa_rtc_remove(struct platform_device *pdev)
Robert Jarzmikdc944362009-01-06 14:42:14 -0800424{
425 struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
426
Alessandro Zummo0417ce22009-01-06 14:42:15 -0800427 rtc_device_unregister(pxa_rtc->rtc);
428
Robert Jarzmikdc944362009-01-06 14:42:14 -0800429 spin_lock_irq(&pxa_rtc->lock);
430 iounmap(pxa_rtc->base);
Robert Jarzmikdc944362009-01-06 14:42:14 -0800431 spin_unlock_irq(&pxa_rtc->lock);
432
Robert Jarzmikdc944362009-01-06 14:42:14 -0800433 kfree(pxa_rtc);
434
435 return 0;
436}
437
438#ifdef CONFIG_PM
439static int pxa_rtc_suspend(struct platform_device *pdev, pm_message_t state)
440{
441 struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
442
443 if (device_may_wakeup(&pdev->dev))
444 enable_irq_wake(pxa_rtc->irq_Alrm);
445 return 0;
446}
447
448static int pxa_rtc_resume(struct platform_device *pdev)
449{
450 struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
451
452 if (device_may_wakeup(&pdev->dev))
453 disable_irq_wake(pxa_rtc->irq_Alrm);
454 return 0;
455}
456#else
457#define pxa_rtc_suspend NULL
458#define pxa_rtc_resume NULL
459#endif
460
461static struct platform_driver pxa_rtc_driver = {
Robert Jarzmikdc944362009-01-06 14:42:14 -0800462 .remove = __exit_p(pxa_rtc_remove),
463 .suspend = pxa_rtc_suspend,
464 .resume = pxa_rtc_resume,
465 .driver = {
466 .name = "pxa-rtc",
467 },
468};
469
470static int __init pxa_rtc_init(void)
471{
472 if (cpu_is_pxa27x() || cpu_is_pxa3xx())
Alessandro Zummo0417ce22009-01-06 14:42:15 -0800473 return platform_driver_probe(&pxa_rtc_driver, pxa_rtc_probe);
Robert Jarzmikdc944362009-01-06 14:42:14 -0800474
475 return -ENODEV;
476}
477
478static void __exit pxa_rtc_exit(void)
479{
480 platform_driver_unregister(&pxa_rtc_driver);
481}
482
483module_init(pxa_rtc_init);
484module_exit(pxa_rtc_exit);
485
486MODULE_AUTHOR("Robert Jarzmik");
487MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
488MODULE_LICENSE("GPL");
489MODULE_ALIAS("platform:pxa-rtc");