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David Gibson8d2169e2007-04-27 11:53:52 +10001#ifndef _ASM_POWERPC_MMU_HASH64_H_
2#define _ASM_POWERPC_MMU_HASH64_H_
3/*
4 * PowerPC64 memory management structures
5 *
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
7 * PPC64 rework.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <asm/asm-compat.h>
16#include <asm/page.h>
17
18/*
19 * Segment table
20 */
21
22#define STE_ESID_V 0x80
23#define STE_ESID_KS 0x20
24#define STE_ESID_KP 0x10
25#define STE_ESID_N 0x08
26
27#define STE_VSID_SHIFT 12
28
29/* Location of cpu0's segment table */
30#define STAB0_PAGE 0x6
31#define STAB0_OFFSET (STAB0_PAGE << 12)
32#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
33
34#ifndef __ASSEMBLY__
35extern char initial_stab[];
36#endif /* ! __ASSEMBLY */
37
38/*
39 * SLB
40 */
41
42#define SLB_NUM_BOLTED 3
43#define SLB_CACHE_ENTRIES 8
44
45/* Bits in the SLB ESID word */
46#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
47
48/* Bits in the SLB VSID word */
49#define SLB_VSID_SHIFT 12
Paul Mackerras1189be62007-10-11 20:37:10 +100050#define SLB_VSID_SHIFT_1T 24
51#define SLB_VSID_SSIZE_SHIFT 62
David Gibson8d2169e2007-04-27 11:53:52 +100052#define SLB_VSID_B ASM_CONST(0xc000000000000000)
53#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
54#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
55#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
56#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
57#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
58#define SLB_VSID_L ASM_CONST(0x0000000000000100)
59#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
60#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
61#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
62#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
63#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
64#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
65#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
66
67#define SLB_VSID_KERNEL (SLB_VSID_KP)
68#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
69
70#define SLBIE_C (0x08000000)
Paul Mackerras1189be62007-10-11 20:37:10 +100071#define SLBIE_SSIZE_SHIFT 25
David Gibson8d2169e2007-04-27 11:53:52 +100072
73/*
74 * Hash table
75 */
76
77#define HPTES_PER_GROUP 8
78
Paul Mackerras2454c7e2007-05-10 15:28:44 +100079#define HPTE_V_SSIZE_SHIFT 62
David Gibson8d2169e2007-04-27 11:53:52 +100080#define HPTE_V_AVPN_SHIFT 7
Paul Mackerras2454c7e2007-05-10 15:28:44 +100081#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
David Gibson8d2169e2007-04-27 11:53:52 +100082#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
Paul Mackerras1189be62007-10-11 20:37:10 +100083#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80))
David Gibson8d2169e2007-04-27 11:53:52 +100084#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
85#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
86#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
87#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
88#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
89
90#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
91#define HPTE_R_TS ASM_CONST(0x4000000000000000)
92#define HPTE_R_RPN_SHIFT 12
93#define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
94#define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
95#define HPTE_R_PP ASM_CONST(0x0000000000000003)
96#define HPTE_R_N ASM_CONST(0x0000000000000004)
97#define HPTE_R_C ASM_CONST(0x0000000000000080)
98#define HPTE_R_R ASM_CONST(0x0000000000000100)
99
Sachin P. Santb7abc5c2007-06-14 15:31:34 +1000100#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
101#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
102
David Gibson8d2169e2007-04-27 11:53:52 +1000103/* Values for PP (assumes Ks=0, Kp=1) */
104/* pp0 will always be 0 for linux */
105#define PP_RWXX 0 /* Supervisor read/write, User none */
106#define PP_RWRX 1 /* Supervisor read/write, User read */
107#define PP_RWRW 2 /* Supervisor read/write, User read/write */
108#define PP_RXRX 3 /* Supervisor read, User read */
109
110#ifndef __ASSEMBLY__
111
David Gibson8e561e72007-06-13 14:52:56 +1000112struct hash_pte {
David Gibson8d2169e2007-04-27 11:53:52 +1000113 unsigned long v;
114 unsigned long r;
David Gibson8e561e72007-06-13 14:52:56 +1000115};
David Gibson8d2169e2007-04-27 11:53:52 +1000116
David Gibson8e561e72007-06-13 14:52:56 +1000117extern struct hash_pte *htab_address;
David Gibson8d2169e2007-04-27 11:53:52 +1000118extern unsigned long htab_size_bytes;
119extern unsigned long htab_hash_mask;
120
121/*
122 * Page size definition
123 *
124 * shift : is the "PAGE_SHIFT" value for that page size
125 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
126 * directly to a slbmte "vsid" value
127 * penc : is the HPTE encoding mask for the "LP" field:
128 *
129 */
130struct mmu_psize_def
131{
132 unsigned int shift; /* number of bits */
133 unsigned int penc; /* HPTE encoding */
134 unsigned int tlbiel; /* tlbiel supported for that page size */
135 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
136 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
137};
138
139#endif /* __ASSEMBLY__ */
140
141/*
142 * The kernel use the constants below to index in the page sizes array.
143 * The use of fixed constants for this purpose is better for performances
144 * of the low level hash refill handlers.
145 *
146 * A non supported page size has a "shift" field set to 0
147 *
148 * Any new page size being implemented can get a new entry in here. Whether
149 * the kernel will use it or not is a different matter though. The actual page
150 * size used by hugetlbfs is not defined here and may be made variable
151 */
152
153#define MMU_PAGE_4K 0 /* 4K */
154#define MMU_PAGE_64K 1 /* 64K */
155#define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */
156#define MMU_PAGE_1M 3 /* 1M */
157#define MMU_PAGE_16M 4 /* 16M */
158#define MMU_PAGE_16G 5 /* 16G */
159#define MMU_PAGE_COUNT 6
160
Paul Mackerras2454c7e2007-05-10 15:28:44 +1000161/*
162 * Segment sizes.
163 * These are the values used by hardware in the B field of
164 * SLB entries and the first dword of MMU hashtable entries.
165 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
166 */
167#define MMU_SEGSIZE_256M 0
168#define MMU_SEGSIZE_1T 1
169
Paul Mackerras1189be62007-10-11 20:37:10 +1000170
David Gibson8d2169e2007-04-27 11:53:52 +1000171#ifndef __ASSEMBLY__
172
173/*
Paul Mackerras1189be62007-10-11 20:37:10 +1000174 * The current system page and segment sizes
David Gibson8d2169e2007-04-27 11:53:52 +1000175 */
176extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
177extern int mmu_linear_psize;
178extern int mmu_virtual_psize;
179extern int mmu_vmalloc_psize;
180extern int mmu_io_psize;
Paul Mackerras1189be62007-10-11 20:37:10 +1000181extern int mmu_kernel_ssize;
182extern int mmu_highuser_ssize;
David Gibson8d2169e2007-04-27 11:53:52 +1000183
184/*
185 * If the processor supports 64k normal pages but not 64k cache
186 * inhibited pages, we have to be prepared to switch processes
187 * to use 4k pages when they create cache-inhibited mappings.
188 * If this is the case, mmu_ci_restrictions will be set to 1.
189 */
190extern int mmu_ci_restrictions;
191
192#ifdef CONFIG_HUGETLB_PAGE
193/*
194 * The page size index of the huge pages for use by hugetlbfs
195 */
196extern int mmu_huge_psize;
197
198#endif /* CONFIG_HUGETLB_PAGE */
199
200/*
201 * This function sets the AVPN and L fields of the HPTE appropriately
202 * for the page size
203 */
Paul Mackerras1189be62007-10-11 20:37:10 +1000204static inline unsigned long hpte_encode_v(unsigned long va, int psize,
205 int ssize)
David Gibson8d2169e2007-04-27 11:53:52 +1000206{
Paul Mackerras1189be62007-10-11 20:37:10 +1000207 unsigned long v;
David Gibson8d2169e2007-04-27 11:53:52 +1000208 v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
209 v <<= HPTE_V_AVPN_SHIFT;
210 if (psize != MMU_PAGE_4K)
211 v |= HPTE_V_LARGE;
Paul Mackerras1189be62007-10-11 20:37:10 +1000212 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
David Gibson8d2169e2007-04-27 11:53:52 +1000213 return v;
214}
215
216/*
217 * This function sets the ARPN, and LP fields of the HPTE appropriately
218 * for the page size. We assume the pa is already "clean" that is properly
219 * aligned for the requested page size
220 */
221static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
222{
223 unsigned long r;
224
225 /* A 4K page needs no special encoding */
226 if (psize == MMU_PAGE_4K)
227 return pa & HPTE_R_RPN;
228 else {
229 unsigned int penc = mmu_psize_defs[psize].penc;
230 unsigned int shift = mmu_psize_defs[psize].shift;
231 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
232 }
233 return r;
234}
235
236/*
Paul Mackerras1189be62007-10-11 20:37:10 +1000237 * Build a VA given VSID, EA and segment size
238 */
239static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
240 int ssize)
241{
242 if (ssize == MMU_SEGSIZE_256M)
243 return (vsid << 28) | (ea & 0xfffffffUL);
244 return (vsid << 40) | (ea & 0xffffffffffUL);
245}
246
247/*
248 * This hashes a virtual address
David Gibson8d2169e2007-04-27 11:53:52 +1000249 */
250
Paul Mackerras1189be62007-10-11 20:37:10 +1000251static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
252 int ssize)
David Gibson8d2169e2007-04-27 11:53:52 +1000253{
Paul Mackerras1189be62007-10-11 20:37:10 +1000254 unsigned long hash, vsid;
255
256 if (ssize == MMU_SEGSIZE_256M) {
257 hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift);
258 } else {
259 vsid = va >> 40;
260 hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift);
261 }
262 return hash & 0x7fffffffffUL;
David Gibson8d2169e2007-04-27 11:53:52 +1000263}
264
265extern int __hash_page_4K(unsigned long ea, unsigned long access,
266 unsigned long vsid, pte_t *ptep, unsigned long trap,
Paul Mackerras1189be62007-10-11 20:37:10 +1000267 unsigned int local, int ssize);
David Gibson8d2169e2007-04-27 11:53:52 +1000268extern int __hash_page_64K(unsigned long ea, unsigned long access,
269 unsigned long vsid, pte_t *ptep, unsigned long trap,
Paul Mackerras1189be62007-10-11 20:37:10 +1000270 unsigned int local, int ssize);
David Gibson8d2169e2007-04-27 11:53:52 +1000271struct mm_struct;
272extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
273extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
274 unsigned long ea, unsigned long vsid, int local,
275 unsigned long trap);
276
277extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
278 unsigned long pstart, unsigned long mode,
Paul Mackerras1189be62007-10-11 20:37:10 +1000279 int psize, int ssize);
David Gibson8d2169e2007-04-27 11:53:52 +1000280
281extern void htab_initialize(void);
282extern void htab_initialize_secondary(void);
283extern void hpte_init_native(void);
284extern void hpte_init_lpar(void);
285extern void hpte_init_iSeries(void);
286extern void hpte_init_beat(void);
Ishizaki Kou7f2c8572007-10-02 18:23:46 +1000287extern void hpte_init_beat_v3(void);
David Gibson8d2169e2007-04-27 11:53:52 +1000288
289extern void stabs_alloc(void);
290extern void slb_initialize(void);
291extern void slb_flush_and_rebolt(void);
292extern void stab_initialize(unsigned long stab);
293
Michael Neuling67439b72007-08-03 11:55:39 +1000294extern void slb_vmalloc_update(void);
David Gibson8d2169e2007-04-27 11:53:52 +1000295#endif /* __ASSEMBLY__ */
296
297/*
298 * VSID allocation
299 *
300 * We first generate a 36-bit "proto-VSID". For kernel addresses this
301 * is equal to the ESID, for user addresses it is:
302 * (context << 15) | (esid & 0x7fff)
303 *
304 * The two forms are distinguishable because the top bit is 0 for user
305 * addresses, whereas the top two bits are 1 for kernel addresses.
306 * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
307 * now.
308 *
309 * The proto-VSIDs are then scrambled into real VSIDs with the
310 * multiplicative hash:
311 *
312 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
313 * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
314 * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
315 *
316 * This scramble is only well defined for proto-VSIDs below
317 * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
318 * reserved. VSID_MULTIPLIER is prime, so in particular it is
319 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
320 * Because the modulus is 2^n-1 we can compute it efficiently without
321 * a divide or extra multiply (see below).
322 *
323 * This scheme has several advantages over older methods:
324 *
325 * - We have VSIDs allocated for every kernel address
326 * (i.e. everything above 0xC000000000000000), except the very top
327 * segment, which simplifies several things.
328 *
329 * - We allow for 15 significant bits of ESID and 20 bits of
330 * context for user addresses. i.e. 8T (43 bits) of address space for
331 * up to 1M contexts (although the page table structure and context
332 * allocation will need changes to take advantage of this).
333 *
334 * - The scramble function gives robust scattering in the hash
335 * table (at least based on some initial results). The previous
336 * method was more susceptible to pathological cases giving excessive
337 * hash collisions.
338 */
339/*
340 * WARNING - If you change these you must make sure the asm
341 * implementations in slb_allocate (slb_low.S), do_stab_bolted
342 * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
343 *
344 * You'll also need to change the precomputed VSID values in head.S
345 * which are used by the iSeries firmware.
346 */
347
Paul Mackerras1189be62007-10-11 20:37:10 +1000348#define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */
349#define VSID_BITS_256M 36
350#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
David Gibson8d2169e2007-04-27 11:53:52 +1000351
Paul Mackerras1189be62007-10-11 20:37:10 +1000352#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
353#define VSID_BITS_1T 24
354#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
355
356#define CONTEXT_BITS 19
357#define USER_ESID_BITS 16
358#define USER_ESID_BITS_1T 4
David Gibson8d2169e2007-04-27 11:53:52 +1000359
360#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
361
362/*
363 * This macro generates asm code to compute the VSID scramble
364 * function. Used in slb_allocate() and do_stab_bolted. The function
365 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
366 *
367 * rt = register continaing the proto-VSID and into which the
368 * VSID will be stored
369 * rx = scratch register (clobbered)
370 *
371 * - rt and rx must be different registers
Paul Mackerras1189be62007-10-11 20:37:10 +1000372 * - The answer will end up in the low VSID_BITS bits of rt. The higher
David Gibson8d2169e2007-04-27 11:53:52 +1000373 * bits may contain other garbage, so you may need to mask the
374 * result.
375 */
Paul Mackerras1189be62007-10-11 20:37:10 +1000376#define ASM_VSID_SCRAMBLE(rt, rx, size) \
377 lis rx,VSID_MULTIPLIER_##size@h; \
378 ori rx,rx,VSID_MULTIPLIER_##size@l; \
David Gibson8d2169e2007-04-27 11:53:52 +1000379 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
380 \
Paul Mackerras1189be62007-10-11 20:37:10 +1000381 srdi rx,rt,VSID_BITS_##size; \
382 clrldi rt,rt,(64-VSID_BITS_##size); \
David Gibson8d2169e2007-04-27 11:53:52 +1000383 add rt,rt,rx; /* add high and low bits */ \
384 /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
385 * 2^36-1+2^28-1. That in particular means that if r3 >= \
386 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
387 * the bit clear, r3 already has the answer we want, if it \
388 * doesn't, the answer is the low 36 bits of r3+1. So in all \
389 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
390 addi rx,rt,1; \
Paul Mackerras1189be62007-10-11 20:37:10 +1000391 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
David Gibson8d2169e2007-04-27 11:53:52 +1000392 add rt,rt,rx
393
394
395#ifndef __ASSEMBLY__
396
397typedef unsigned long mm_context_id_t;
398
399typedef struct {
400 mm_context_id_t id;
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +1000401 u16 user_psize; /* page size index */
402
403#ifdef CONFIG_PPC_MM_SLICES
404 u64 low_slices_psize; /* SLB page size encodings */
405 u64 high_slices_psize; /* 4 bits per slice for now */
406#else
407 u16 sllp; /* SLB page size encoding */
David Gibson8d2169e2007-04-27 11:53:52 +1000408#endif
409 unsigned long vdso_base;
410} mm_context_t;
411
412
David Gibson8d2169e2007-04-27 11:53:52 +1000413#if 0
Paul Mackerras1189be62007-10-11 20:37:10 +1000414/*
415 * The code below is equivalent to this function for arguments
416 * < 2^VSID_BITS, which is all this should ever be called
417 * with. However gcc is not clever enough to compute the
418 * modulus (2^n-1) without a second multiply.
419 */
420#define vsid_scrample(protovsid, size) \
421 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
David Gibson8d2169e2007-04-27 11:53:52 +1000422
Paul Mackerras1189be62007-10-11 20:37:10 +1000423#else /* 1 */
424#define vsid_scramble(protovsid, size) \
425 ({ \
426 unsigned long x; \
427 x = (protovsid) * VSID_MULTIPLIER_##size; \
428 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
429 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
430 })
David Gibson8d2169e2007-04-27 11:53:52 +1000431#endif /* 1 */
David Gibson8d2169e2007-04-27 11:53:52 +1000432
433/* This is only valid for addresses >= KERNELBASE */
Paul Mackerras1189be62007-10-11 20:37:10 +1000434static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
David Gibson8d2169e2007-04-27 11:53:52 +1000435{
Paul Mackerras1189be62007-10-11 20:37:10 +1000436 if (ssize == MMU_SEGSIZE_256M)
437 return vsid_scramble(ea >> SID_SHIFT, 256M);
438 return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
David Gibson8d2169e2007-04-27 11:53:52 +1000439}
440
Paul Mackerras1189be62007-10-11 20:37:10 +1000441/* Returns the segment size indicator for a user address */
442static inline int user_segment_size(unsigned long addr)
David Gibson8d2169e2007-04-27 11:53:52 +1000443{
Paul Mackerras1189be62007-10-11 20:37:10 +1000444 /* Use 1T segments if possible for addresses >= 1T */
445 if (addr >= (1UL << SID_SHIFT_1T))
446 return mmu_highuser_ssize;
447 return MMU_SEGSIZE_256M;
David Gibson8d2169e2007-04-27 11:53:52 +1000448}
449
Paul Mackerras1189be62007-10-11 20:37:10 +1000450/* This is only valid for user addresses (which are below 2^44) */
451static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
452 int ssize)
453{
454 if (ssize == MMU_SEGSIZE_256M)
455 return vsid_scramble((context << USER_ESID_BITS)
456 | (ea >> SID_SHIFT), 256M);
457 return vsid_scramble((context << USER_ESID_BITS_1T)
458 | (ea >> SID_SHIFT_1T), 1T);
459}
460
461/*
462 * This is only used on legacy iSeries in lparmap.c,
463 * hence the 256MB segment assumption.
464 */
465#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER_256M) % \
466 VSID_MODULUS_256M)
David Gibson8d2169e2007-04-27 11:53:52 +1000467#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
468
469/* Physical address used by some IO functions */
470typedef unsigned long phys_addr_t;
471
472#endif /* __ASSEMBLY__ */
473
474#endif /* _ASM_POWERPC_MMU_HASH64_H_ */