Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Red Hat |
| 3 | * Author: Rob Clark <robdclark@gmail.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License version 2 as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #ifndef __MSM_DRV_H__ |
| 19 | #define __MSM_DRV_H__ |
| 20 | |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/clk.h> |
| 23 | #include <linux/cpufreq.h> |
| 24 | #include <linux/module.h> |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 25 | #include <linux/component.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/pm.h> |
| 28 | #include <linux/pm_runtime.h> |
| 29 | #include <linux/slab.h> |
| 30 | #include <linux/list.h> |
| 31 | #include <linux/iommu.h> |
| 32 | #include <linux/types.h> |
Archit Taneja | 3d6df06 | 2015-06-09 14:17:22 +0530 | [diff] [blame] | 33 | #include <linux/of_graph.h> |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 34 | #include <linux/of_device.h> |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 35 | #include <linux/mdss_io_util.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 36 | #include <asm/sizes.h> |
| 37 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 38 | #include <drm/drmP.h> |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 39 | #include <drm/drm_atomic.h> |
| 40 | #include <drm/drm_atomic_helper.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 41 | #include <drm/drm_crtc_helper.h> |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 42 | #include <drm/drm_plane_helper.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 43 | #include <drm/drm_fb_helper.h> |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 44 | #include <drm/msm_drm.h> |
Daniel Vetter | d9fc941 | 2014-09-23 15:46:53 +0200 | [diff] [blame] | 45 | #include <drm/drm_gem.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 46 | |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 47 | #include "sde_power_handle.h" |
| 48 | |
| 49 | #define GET_MAJOR_REV(rev) ((rev) >> 28) |
| 50 | #define GET_MINOR_REV(rev) (((rev) >> 16) & 0xFFF) |
| 51 | #define GET_STEP_REV(rev) ((rev) & 0xFFFF) |
Lloyd Atkinson | 154b6aa | 2016-05-24 17:11:37 -0400 | [diff] [blame] | 52 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 53 | struct msm_kms; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 54 | struct msm_gpu; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 55 | struct msm_mmu; |
Archit Taneja | 990a400 | 2016-05-07 23:11:25 +0530 | [diff] [blame] | 56 | struct msm_mdss; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 57 | struct msm_rd_state; |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 58 | struct msm_perf_state; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 59 | struct msm_gem_submit; |
Rob Clark | ca762a8 | 2016-03-15 17:22:13 -0400 | [diff] [blame] | 60 | struct msm_fence_context; |
Rob Clark | fde5de6 | 2016-03-15 15:35:08 -0400 | [diff] [blame] | 61 | struct msm_fence_cb; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 62 | |
Alan Kwong | 112a84f | 2016-05-24 20:49:21 -0400 | [diff] [blame] | 63 | #define NUM_DOMAINS 4 /* one for KMS, then one per gpu core (?) */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 64 | #define MAX_CRTCS 8 |
| 65 | #define MAX_PLANES 12 |
| 66 | #define MAX_ENCODERS 8 |
| 67 | #define MAX_BRIDGES 8 |
| 68 | #define MAX_CONNECTORS 8 |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 69 | |
| 70 | struct msm_file_private { |
| 71 | /* currently we don't do anything useful with this.. but when |
| 72 | * per-context address spaces are supported we'd keep track of |
| 73 | * the context's page-tables here. |
| 74 | */ |
| 75 | int dummy; |
| 76 | }; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 77 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 78 | enum msm_mdp_plane_property { |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 79 | /* blob properties, always put these first */ |
Clarence Ip | b43d459 | 2016-09-08 14:21:35 -0400 | [diff] [blame] | 80 | PLANE_PROP_SCALER_V1, |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 81 | PLANE_PROP_SCALER_V2, |
Clarence Ip | 5fc00c5 | 2016-09-23 15:03:34 -0400 | [diff] [blame] | 82 | PLANE_PROP_CSC_V1, |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 83 | PLANE_PROP_INFO, |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 84 | PLANE_PROP_SCALER_LUT_ED, |
| 85 | PLANE_PROP_SCALER_LUT_CIR, |
| 86 | PLANE_PROP_SCALER_LUT_SEP, |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 87 | PLANE_PROP_SKIN_COLOR, |
| 88 | PLANE_PROP_SKY_COLOR, |
| 89 | PLANE_PROP_FOLIAGE_COLOR, |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 90 | |
| 91 | /* # of blob properties */ |
| 92 | PLANE_PROP_BLOBCOUNT, |
| 93 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 94 | /* range properties */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 95 | PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT, |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 96 | PLANE_PROP_ALPHA, |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 97 | PLANE_PROP_COLOR_FILL, |
Clarence Ip | dedbba9 | 2016-09-27 17:43:10 -0400 | [diff] [blame] | 98 | PLANE_PROP_H_DECIMATE, |
| 99 | PLANE_PROP_V_DECIMATE, |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 100 | PLANE_PROP_INPUT_FENCE, |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 101 | PLANE_PROP_HUE_ADJUST, |
| 102 | PLANE_PROP_SATURATION_ADJUST, |
| 103 | PLANE_PROP_VALUE_ADJUST, |
| 104 | PLANE_PROP_CONTRAST_ADJUST, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 105 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 106 | /* enum/bitmask properties */ |
| 107 | PLANE_PROP_ROTATION, |
| 108 | PLANE_PROP_BLEND_OP, |
| 109 | PLANE_PROP_SRC_CONFIG, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 110 | |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 111 | /* total # of properties */ |
| 112 | PLANE_PROP_COUNT |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 113 | }; |
| 114 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 115 | enum msm_mdp_crtc_property { |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 116 | CRTC_PROP_INFO, |
| 117 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 118 | /* # of blob properties */ |
| 119 | CRTC_PROP_BLOBCOUNT, |
| 120 | |
| 121 | /* range properties */ |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 122 | CRTC_PROP_INPUT_FENCE_TIMEOUT = CRTC_PROP_BLOBCOUNT, |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 123 | CRTC_PROP_OUTPUT_FENCE, |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 124 | CRTC_PROP_OUTPUT_FENCE_OFFSET, |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 125 | |
| 126 | /* total # of properties */ |
| 127 | CRTC_PROP_COUNT |
| 128 | }; |
| 129 | |
Clarence Ip | dd8021c | 2016-07-20 16:39:47 -0400 | [diff] [blame] | 130 | enum msm_mdp_conn_property { |
| 131 | /* blob properties, always put these first */ |
| 132 | CONNECTOR_PROP_SDE_INFO, |
| 133 | |
| 134 | /* # of blob properties */ |
| 135 | CONNECTOR_PROP_BLOBCOUNT, |
| 136 | |
| 137 | /* range properties */ |
| 138 | CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT, |
| 139 | CONNECTOR_PROP_RETIRE_FENCE, |
Alan Kwong | bb27c09 | 2016-07-20 16:41:25 -0400 | [diff] [blame] | 140 | CONNECTOR_PROP_DST_X, |
| 141 | CONNECTOR_PROP_DST_Y, |
| 142 | CONNECTOR_PROP_DST_W, |
| 143 | CONNECTOR_PROP_DST_H, |
Clarence Ip | dd8021c | 2016-07-20 16:39:47 -0400 | [diff] [blame] | 144 | |
| 145 | /* enum/bitmask properties */ |
Lloyd Atkinson | b619197 | 2016-08-10 18:31:46 -0400 | [diff] [blame] | 146 | CONNECTOR_PROP_TOPOLOGY_NAME, |
| 147 | CONNECTOR_PROP_TOPOLOGY_CONTROL, |
Clarence Ip | dd8021c | 2016-07-20 16:39:47 -0400 | [diff] [blame] | 148 | |
| 149 | /* total # of properties */ |
| 150 | CONNECTOR_PROP_COUNT |
| 151 | }; |
| 152 | |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 153 | struct msm_vblank_ctrl { |
| 154 | struct work_struct work; |
| 155 | struct list_head event_list; |
| 156 | spinlock_t lock; |
| 157 | }; |
| 158 | |
Clarence Ip | a403932 | 2016-07-15 16:23:59 -0400 | [diff] [blame] | 159 | #define MAX_H_TILES_PER_DISPLAY 2 |
| 160 | |
| 161 | /** |
| 162 | * enum msm_display_compression - compression method used for pixel stream |
| 163 | * @MSM_DISPLAY_COMPRESS_NONE: Pixel data is not compressed |
| 164 | * @MSM_DISPLAY_COMPRESS_DSC: DSC compresison is used |
| 165 | * @MSM_DISPLAY_COMPRESS_FBC: FBC compression is used |
| 166 | */ |
| 167 | enum msm_display_compression { |
| 168 | MSM_DISPLAY_COMPRESS_NONE, |
| 169 | MSM_DISPLAY_COMPRESS_DSC, |
| 170 | MSM_DISPLAY_COMPRESS_FBC, |
| 171 | }; |
| 172 | |
| 173 | /** |
| 174 | * enum msm_display_caps - features/capabilities supported by displays |
| 175 | * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported |
| 176 | * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported |
| 177 | * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported |
| 178 | * @MSM_DISPLAY_CAP_EDID: EDID supported |
| 179 | */ |
| 180 | enum msm_display_caps { |
| 181 | MSM_DISPLAY_CAP_VID_MODE = BIT(0), |
| 182 | MSM_DISPLAY_CAP_CMD_MODE = BIT(1), |
| 183 | MSM_DISPLAY_CAP_HOT_PLUG = BIT(2), |
| 184 | MSM_DISPLAY_CAP_EDID = BIT(3), |
| 185 | }; |
| 186 | |
| 187 | /** |
| 188 | * struct msm_display_info - defines display properties |
| 189 | * @intf_type: DRM_MODE_CONNECTOR_ display type |
| 190 | * @capabilities: Bitmask of display flags |
| 191 | * @num_of_h_tiles: Number of horizontal tiles in case of split interface |
| 192 | * @h_tile_instance: Controller instance used per tile. Number of elements is |
| 193 | * based on num_of_h_tiles |
| 194 | * @is_connected: Set to true if display is connected |
| 195 | * @width_mm: Physical width |
| 196 | * @height_mm: Physical height |
| 197 | * @max_width: Max width of display. In case of hot pluggable display |
| 198 | * this is max width supported by controller |
| 199 | * @max_height: Max height of display. In case of hot pluggable display |
| 200 | * this is max height supported by controller |
| 201 | * @compression: Compression supported by the display |
| 202 | */ |
| 203 | struct msm_display_info { |
| 204 | int intf_type; |
| 205 | uint32_t capabilities; |
| 206 | |
| 207 | uint32_t num_of_h_tiles; |
| 208 | uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; |
| 209 | |
| 210 | bool is_connected; |
| 211 | |
| 212 | unsigned int width_mm; |
| 213 | unsigned int height_mm; |
| 214 | |
| 215 | uint32_t max_width; |
| 216 | uint32_t max_height; |
| 217 | |
| 218 | enum msm_display_compression compression; |
| 219 | }; |
| 220 | |
Clarence Ip | 3649f8b | 2016-10-31 09:59:44 -0400 | [diff] [blame] | 221 | /** |
| 222 | * struct msm_drm_event - defines custom event notification struct |
| 223 | * @base: base object required for event notification by DRM framework. |
| 224 | * @event: event object required for event notification by DRM framework. |
| 225 | * @info: contains information of DRM object for which events has been |
| 226 | * requested. |
| 227 | * @data: memory location which contains response payload for event. |
| 228 | */ |
| 229 | struct msm_drm_event { |
| 230 | struct drm_pending_event base; |
| 231 | struct drm_event event; |
| 232 | struct drm_msm_event_req info; |
| 233 | u8 data[]; |
| 234 | }; |
Ajay Singh Parmar | 64c1919 | 2016-06-10 16:44:56 -0700 | [diff] [blame] | 235 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 236 | struct msm_drm_private { |
| 237 | |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 238 | struct drm_device *dev; |
| 239 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 240 | struct msm_kms *kms; |
| 241 | |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 242 | struct sde_power_handle phandle; |
| 243 | struct sde_power_client *pclient; |
| 244 | |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 245 | /* subordinate devices, if present: */ |
Rob Clark | 067fef3 | 2014-11-04 13:33:14 -0500 | [diff] [blame] | 246 | struct platform_device *gpu_pdev; |
| 247 | |
Archit Taneja | 990a400 | 2016-05-07 23:11:25 +0530 | [diff] [blame] | 248 | /* top level MDSS wrapper device (for MDP5 only) */ |
| 249 | struct msm_mdss *mdss; |
| 250 | |
Rob Clark | 067fef3 | 2014-11-04 13:33:14 -0500 | [diff] [blame] | 251 | /* possibly this should be in the kms component, but it is |
| 252 | * shared by both mdp4 and mdp5.. |
| 253 | */ |
| 254 | struct hdmi *hdmi; |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 255 | |
Hai Li | ab5b010 | 2015-01-07 18:47:44 -0500 | [diff] [blame] | 256 | /* eDP is for mdp5 only, but kms has not been created |
| 257 | * when edp_bind() and edp_init() are called. Here is the only |
| 258 | * place to keep the edp instance. |
| 259 | */ |
| 260 | struct msm_edp *edp; |
| 261 | |
Hai Li | a689554 | 2015-03-31 14:36:33 -0400 | [diff] [blame] | 262 | /* DSI is shared by mdp4 and mdp5 */ |
| 263 | struct msm_dsi *dsi[2]; |
| 264 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 265 | /* when we have more than one 'msm_gpu' these need to be an array: */ |
| 266 | struct msm_gpu *gpu; |
| 267 | struct msm_file_private *lastctx; |
| 268 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 269 | struct drm_fb_helper *fbdev; |
| 270 | |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 271 | struct msm_rd_state *rd; |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 272 | struct msm_perf_state *perf; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 273 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 274 | /* list of GEM objects: */ |
| 275 | struct list_head inactive_list; |
| 276 | |
| 277 | struct workqueue_struct *wq; |
Rob Clark | ba00c3f | 2016-03-16 18:18:17 -0400 | [diff] [blame] | 278 | struct workqueue_struct *atomic_wq; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 279 | |
Rob Clark | f86afec | 2014-11-25 12:41:18 -0500 | [diff] [blame] | 280 | /* crtcs pending async atomic updates: */ |
| 281 | uint32_t pending_crtcs; |
| 282 | wait_queue_head_t pending_crtcs_event; |
| 283 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 284 | /* registered MMUs: */ |
| 285 | unsigned int num_mmus; |
| 286 | struct msm_mmu *mmus[NUM_DOMAINS]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 287 | |
Rob Clark | a862391 | 2013-10-08 12:57:48 -0400 | [diff] [blame] | 288 | unsigned int num_planes; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 289 | struct drm_plane *planes[MAX_PLANES]; |
Rob Clark | a862391 | 2013-10-08 12:57:48 -0400 | [diff] [blame] | 290 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 291 | unsigned int num_crtcs; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 292 | struct drm_crtc *crtcs[MAX_CRTCS]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 293 | |
| 294 | unsigned int num_encoders; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 295 | struct drm_encoder *encoders[MAX_ENCODERS]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 296 | |
Rob Clark | a3376e3 | 2013-08-30 13:02:15 -0400 | [diff] [blame] | 297 | unsigned int num_bridges; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 298 | struct drm_bridge *bridges[MAX_BRIDGES]; |
Rob Clark | a3376e3 | 2013-08-30 13:02:15 -0400 | [diff] [blame] | 299 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 300 | unsigned int num_connectors; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 301 | struct drm_connector *connectors[MAX_CONNECTORS]; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 302 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 303 | /* Properties */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 304 | struct drm_property *plane_property[PLANE_PROP_COUNT]; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 305 | struct drm_property *crtc_property[CRTC_PROP_COUNT]; |
Clarence Ip | dd8021c | 2016-07-20 16:39:47 -0400 | [diff] [blame] | 306 | struct drm_property *conn_property[CONNECTOR_PROP_COUNT]; |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 307 | |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 308 | /* Color processing properties for the crtc */ |
| 309 | struct drm_property **cp_property; |
| 310 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 311 | /* VRAM carveout, used when no IOMMU: */ |
| 312 | struct { |
| 313 | unsigned long size; |
| 314 | dma_addr_t paddr; |
| 315 | /* NOTE: mm managed at the page level, size is in # of pages |
| 316 | * and position mm_node->start is in # of pages: |
| 317 | */ |
| 318 | struct drm_mm mm; |
| 319 | } vram; |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 320 | |
Rob Clark | e1e9db2 | 2016-05-27 11:16:28 -0400 | [diff] [blame] | 321 | struct notifier_block vmap_notifier; |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 322 | struct shrinker shrinker; |
| 323 | |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 324 | struct msm_vblank_ctrl vblank_ctrl; |
Rob Clark | d78d383 | 2016-08-22 15:28:38 -0400 | [diff] [blame] | 325 | |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 326 | /* list of clients waiting for events */ |
| 327 | struct list_head client_event_list; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 328 | }; |
| 329 | |
| 330 | struct msm_format { |
| 331 | uint32_t pixel_format; |
| 332 | }; |
| 333 | |
Daniel Vetter | b4274fb | 2014-11-26 17:02:18 +0100 | [diff] [blame] | 334 | int msm_atomic_check(struct drm_device *dev, |
| 335 | struct drm_atomic_state *state); |
Dhaval Patel | 7a7d85d | 2016-08-26 16:35:34 -0700 | [diff] [blame] | 336 | /* callback from wq once fence has passed: */ |
| 337 | struct msm_fence_cb { |
| 338 | struct work_struct work; |
| 339 | uint32_t fence; |
| 340 | void (*func)(struct msm_fence_cb *cb); |
| 341 | }; |
| 342 | |
| 343 | void __msm_fence_worker(struct work_struct *work); |
| 344 | |
| 345 | #define INIT_FENCE_CB(_cb, _func) do { \ |
| 346 | INIT_WORK(&(_cb)->work, __msm_fence_worker); \ |
| 347 | (_cb)->func = _func; \ |
| 348 | } while (0) |
| 349 | |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 350 | int msm_atomic_commit(struct drm_device *dev, |
Maarten Lankhorst | a3ccfb9 | 2016-04-26 16:11:38 +0200 | [diff] [blame] | 351 | struct drm_atomic_state *state, bool nonblock); |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 352 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 353 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); |
Lloyd Atkinson | 1e2497e | 2016-09-26 17:55:48 -0400 | [diff] [blame] | 354 | void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 355 | |
Rob Clark | 40e6815 | 2016-05-03 09:50:26 -0400 | [diff] [blame] | 356 | void msm_gem_submit_free(struct msm_gem_submit *submit); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 357 | int msm_ioctl_gem_submit(struct drm_device *dev, void *data, |
| 358 | struct drm_file *file); |
| 359 | |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 360 | void msm_gem_shrinker_init(struct drm_device *dev); |
| 361 | void msm_gem_shrinker_cleanup(struct drm_device *dev); |
| 362 | |
Daniel Thompson | 77a147e | 2014-11-12 11:38:14 +0000 | [diff] [blame] | 363 | int msm_gem_mmap_obj(struct drm_gem_object *obj, |
| 364 | struct vm_area_struct *vma); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 365 | int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); |
| 366 | int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
| 367 | uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); |
| 368 | int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, |
| 369 | uint32_t *iova); |
| 370 | int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); |
Rob Clark | 2638d90 | 2014-11-08 09:13:37 -0500 | [diff] [blame] | 371 | uint32_t msm_gem_iova(struct drm_gem_object *obj, int id); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 372 | struct page **msm_gem_get_pages(struct drm_gem_object *obj); |
| 373 | void msm_gem_put_pages(struct drm_gem_object *obj); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 374 | void msm_gem_put_iova(struct drm_gem_object *obj, int id); |
| 375 | int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, |
| 376 | struct drm_mode_create_dumb *args); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 377 | int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, |
| 378 | uint32_t handle, uint64_t *offset); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 379 | struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); |
| 380 | void *msm_gem_prime_vmap(struct drm_gem_object *obj); |
| 381 | void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); |
Daniel Thompson | 77a147e | 2014-11-12 11:38:14 +0000 | [diff] [blame] | 382 | int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 383 | struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, |
Maarten Lankhorst | b5e9c1a | 2014-01-09 11:03:14 +0100 | [diff] [blame] | 384 | struct dma_buf_attachment *attach, struct sg_table *sg); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 385 | int msm_gem_prime_pin(struct drm_gem_object *obj); |
| 386 | void msm_gem_prime_unpin(struct drm_gem_object *obj); |
Rob Clark | 18f2304 | 2016-05-26 16:24:35 -0400 | [diff] [blame] | 387 | void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj); |
| 388 | void *msm_gem_get_vaddr(struct drm_gem_object *obj); |
| 389 | void msm_gem_put_vaddr_locked(struct drm_gem_object *obj); |
| 390 | void msm_gem_put_vaddr(struct drm_gem_object *obj); |
Rob Clark | 4cd33c4 | 2016-05-17 15:44:49 -0400 | [diff] [blame] | 391 | int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv); |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 392 | void msm_gem_purge(struct drm_gem_object *obj); |
Rob Clark | e1e9db2 | 2016-05-27 11:16:28 -0400 | [diff] [blame] | 393 | void msm_gem_vunmap(struct drm_gem_object *obj); |
Rob Clark | b6295f9 | 2016-03-15 18:26:28 -0400 | [diff] [blame] | 394 | int msm_gem_sync_object(struct drm_gem_object *obj, |
| 395 | struct msm_fence_context *fctx, bool exclusive); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 396 | void msm_gem_move_to_active(struct drm_gem_object *obj, |
Rob Clark | b6295f9 | 2016-03-15 18:26:28 -0400 | [diff] [blame] | 397 | struct msm_gpu *gpu, bool exclusive, struct fence *fence); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 398 | void msm_gem_move_to_inactive(struct drm_gem_object *obj); |
Rob Clark | ba00c3f | 2016-03-16 18:18:17 -0400 | [diff] [blame] | 399 | int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 400 | int msm_gem_cpu_fini(struct drm_gem_object *obj); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 401 | void msm_gem_free_object(struct drm_gem_object *obj); |
| 402 | int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, |
| 403 | uint32_t size, uint32_t flags, uint32_t *handle); |
| 404 | struct drm_gem_object *msm_gem_new(struct drm_device *dev, |
| 405 | uint32_t size, uint32_t flags); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 406 | struct drm_gem_object *msm_gem_import(struct drm_device *dev, |
Rob Clark | 79f0e20 | 2016-03-16 12:40:35 -0400 | [diff] [blame] | 407 | struct dma_buf *dmabuf, struct sg_table *sgt); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 408 | |
Rob Clark | 2638d90 | 2014-11-08 09:13:37 -0500 | [diff] [blame] | 409 | int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id); |
| 410 | void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id); |
| 411 | uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 412 | struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); |
| 413 | const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); |
| 414 | struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, |
Ville Syrjälä | 1eb8345 | 2015-11-11 19:11:29 +0200 | [diff] [blame] | 415 | const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 416 | struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, |
Ville Syrjälä | 1eb8345 | 2015-11-11 19:11:29 +0200 | [diff] [blame] | 417 | struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 418 | |
| 419 | struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); |
Archit Taneja | 1aaa57f | 2016-02-25 11:19:45 +0530 | [diff] [blame] | 420 | void msm_fbdev_free(struct drm_device *dev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 421 | |
Rob Clark | dada25b | 2013-12-01 12:12:54 -0500 | [diff] [blame] | 422 | struct hdmi; |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 423 | int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, |
Rob Clark | 067fef3 | 2014-11-04 13:33:14 -0500 | [diff] [blame] | 424 | struct drm_encoder *encoder); |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 425 | void __init msm_hdmi_register(void); |
| 426 | void __exit msm_hdmi_unregister(void); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 427 | |
Hai Li | 0045398 | 2014-12-12 14:41:17 -0500 | [diff] [blame] | 428 | struct msm_edp; |
| 429 | void __init msm_edp_register(void); |
| 430 | void __exit msm_edp_unregister(void); |
| 431 | int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, |
| 432 | struct drm_encoder *encoder); |
| 433 | |
Hai Li | a689554 | 2015-03-31 14:36:33 -0400 | [diff] [blame] | 434 | struct msm_dsi; |
| 435 | enum msm_dsi_encoder_id { |
| 436 | MSM_DSI_VIDEO_ENCODER_ID = 0, |
| 437 | MSM_DSI_CMD_ENCODER_ID = 1, |
| 438 | MSM_DSI_ENCODER_NUM = 2 |
| 439 | }; |
| 440 | #ifdef CONFIG_DRM_MSM_DSI |
| 441 | void __init msm_dsi_register(void); |
| 442 | void __exit msm_dsi_unregister(void); |
| 443 | int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, |
| 444 | struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]); |
| 445 | #else |
| 446 | static inline void __init msm_dsi_register(void) |
| 447 | { |
| 448 | } |
| 449 | static inline void __exit msm_dsi_unregister(void) |
| 450 | { |
| 451 | } |
| 452 | static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, |
| 453 | struct drm_device *dev, |
| 454 | struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]) |
| 455 | { |
| 456 | return -EINVAL; |
| 457 | } |
| 458 | #endif |
| 459 | |
Archit Taneja | 1dd0a0b | 2016-05-30 16:36:50 +0530 | [diff] [blame] | 460 | void __init msm_mdp_register(void); |
| 461 | void __exit msm_mdp_unregister(void); |
| 462 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 463 | #ifdef CONFIG_DEBUG_FS |
| 464 | void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); |
| 465 | void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); |
| 466 | void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 467 | int msm_debugfs_late_init(struct drm_device *dev); |
| 468 | int msm_rd_debugfs_init(struct drm_minor *minor); |
| 469 | void msm_rd_debugfs_cleanup(struct drm_minor *minor); |
| 470 | void msm_rd_dump_submit(struct msm_gem_submit *submit); |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 471 | int msm_perf_debugfs_init(struct drm_minor *minor); |
| 472 | void msm_perf_debugfs_cleanup(struct drm_minor *minor); |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 473 | #else |
| 474 | static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } |
| 475 | static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {} |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 476 | #endif |
| 477 | |
| 478 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
| 479 | const char *dbgname); |
Lloyd Atkinson | 1a0c917 | 2016-10-04 10:01:24 -0400 | [diff] [blame] | 480 | void msm_iounmap(struct platform_device *dev, void __iomem *addr); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 481 | void msm_writel(u32 data, void __iomem *addr); |
| 482 | u32 msm_readl(const void __iomem *addr); |
| 483 | |
| 484 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
| 485 | #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
| 486 | |
| 487 | static inline int align_pitch(int width, int bpp) |
| 488 | { |
| 489 | int bytespp = (bpp + 7) / 8; |
| 490 | /* adreno needs pitch aligned to 32 pixels: */ |
| 491 | return bytespp * ALIGN(width, 32); |
| 492 | } |
| 493 | |
| 494 | /* for the generated headers: */ |
| 495 | #define INVALID_IDX(idx) ({BUG(); 0;}) |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 496 | #define fui(x) ({BUG(); 0;}) |
| 497 | #define util_float_to_half(x) ({BUG(); 0;}) |
| 498 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 499 | |
| 500 | #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) |
| 501 | |
| 502 | /* for conditionally setting boolean flag(s): */ |
| 503 | #define COND(bool, val) ((bool) ? (val) : 0) |
| 504 | |
Rob Clark | 340ff41 | 2016-03-16 14:57:22 -0400 | [diff] [blame] | 505 | static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) |
| 506 | { |
| 507 | ktime_t now = ktime_get(); |
| 508 | unsigned long remaining_jiffies; |
| 509 | |
| 510 | if (ktime_compare(*timeout, now) < 0) { |
| 511 | remaining_jiffies = 0; |
| 512 | } else { |
| 513 | ktime_t rem = ktime_sub(*timeout, now); |
| 514 | struct timespec ts = ktime_to_timespec(rem); |
| 515 | remaining_jiffies = timespec_to_jiffies(&ts); |
| 516 | } |
| 517 | |
| 518 | return remaining_jiffies; |
| 519 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 520 | |
| 521 | #endif /* __MSM_DRV_H__ */ |