viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 1 | /* |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 2 | * SPEAr platform shared irq layer source file |
| 3 | * |
Viresh Kumar | df1590d | 2012-11-12 22:56:03 +0530 | [diff] [blame] | 4 | * Copyright (C) 2009-2012 ST Microelectronics |
Viresh Kumar | 10d8935 | 2012-06-20 12:53:02 -0700 | [diff] [blame] | 5 | * Viresh Kumar <viresh.linux@gmail.com> |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 6 | * |
Viresh Kumar | df1590d | 2012-11-12 22:56:03 +0530 | [diff] [blame] | 7 | * Copyright (C) 2012 ST Microelectronics |
Viresh Kumar | 9cc2368 | 2014-04-18 15:07:16 -0700 | [diff] [blame] | 8 | * Shiraz Hashim <shiraz.linux.kernel@gmail.com> |
Viresh Kumar | df1590d | 2012-11-12 22:56:03 +0530 | [diff] [blame] | 9 | * |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 10 | * This file is licensed under the terms of the GNU General Public |
| 11 | * License version 2. This program is licensed "as is" without any |
| 12 | * warranty of any kind, whether express or implied. |
| 13 | */ |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 14 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 15 | |
| 16 | #include <linux/err.h> |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 17 | #include <linux/export.h> |
| 18 | #include <linux/interrupt.h> |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 19 | #include <linux/io.h> |
| 20 | #include <linux/irq.h> |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 21 | #include <linux/irqdomain.h> |
| 22 | #include <linux/of.h> |
| 23 | #include <linux/of_address.h> |
| 24 | #include <linux/of_irq.h> |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 25 | #include <linux/spinlock.h> |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 26 | |
Rob Herring | e9c5155 | 2013-01-02 09:37:56 -0600 | [diff] [blame] | 27 | #include "irqchip.h" |
| 28 | |
Thomas Gleixner | 078bc00 | 2014-06-19 21:34:38 +0000 | [diff] [blame] | 29 | /* |
| 30 | * struct shirq_regs: shared irq register configuration |
| 31 | * |
| 32 | * enb_reg: enable register offset |
| 33 | * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt |
| 34 | * status_reg: status register offset |
| 35 | * status_reg_mask: status register valid mask |
Thomas Gleixner | 078bc00 | 2014-06-19 21:34:38 +0000 | [diff] [blame] | 36 | */ |
| 37 | struct shirq_regs { |
| 38 | u32 enb_reg; |
| 39 | u32 reset_to_enb; |
| 40 | u32 status_reg; |
Thomas Gleixner | 078bc00 | 2014-06-19 21:34:38 +0000 | [diff] [blame] | 41 | }; |
| 42 | |
| 43 | /* |
| 44 | * struct spear_shirq: shared irq structure |
| 45 | * |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 46 | * base: Base register address |
| 47 | * regs: Register configuration for shared irq block |
Thomas Gleixner | 4ecc832 | 2014-06-19 21:34:41 +0000 | [diff] [blame] | 48 | * mask: Mask to apply to the status register |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 49 | * virq_base: Base virtual interrupt number |
| 50 | * nr_irqs: Number of interrupts handled by this block |
| 51 | * offset: Bit offset of the first interrupt |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 52 | * irq_chip: Interrupt controller chip used for this instance, |
| 53 | * if NULL group is disabled, but accounted |
Thomas Gleixner | 078bc00 | 2014-06-19 21:34:38 +0000 | [diff] [blame] | 54 | */ |
| 55 | struct spear_shirq { |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 56 | void __iomem *base; |
| 57 | struct shirq_regs regs; |
Thomas Gleixner | 4ecc832 | 2014-06-19 21:34:41 +0000 | [diff] [blame] | 58 | u32 mask; |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 59 | u32 virq_base; |
| 60 | u32 nr_irqs; |
| 61 | u32 offset; |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 62 | struct irq_chip *irq_chip; |
Thomas Gleixner | 078bc00 | 2014-06-19 21:34:38 +0000 | [diff] [blame] | 63 | }; |
| 64 | |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 65 | /* spear300 shared irq registers offsets and masks */ |
| 66 | #define SPEAR300_INT_ENB_MASK_REG 0x54 |
| 67 | #define SPEAR300_INT_STS_MASK_REG 0x58 |
| 68 | |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 69 | static DEFINE_RAW_SPINLOCK(shirq_lock); |
| 70 | |
| 71 | static void shirq_irq_mask(struct irq_data *d) |
| 72 | { |
| 73 | struct spear_shirq *shirq = irq_data_get_irq_chip_data(d); |
| 74 | u32 val, shift = d->irq - shirq->virq_base + shirq->offset; |
| 75 | u32 __iomem *reg = shirq->base + shirq->regs.enb_reg; |
| 76 | |
| 77 | raw_spin_lock(&shirq_lock); |
| 78 | val = readl(reg) & ~(0x1 << shift); |
| 79 | writel(val, reg); |
| 80 | raw_spin_unlock(&shirq_lock); |
| 81 | } |
| 82 | |
| 83 | static void shirq_irq_unmask(struct irq_data *d) |
| 84 | { |
| 85 | struct spear_shirq *shirq = irq_data_get_irq_chip_data(d); |
| 86 | u32 val, shift = d->irq - shirq->virq_base + shirq->offset; |
| 87 | u32 __iomem *reg = shirq->base + shirq->regs.enb_reg; |
| 88 | |
| 89 | raw_spin_lock(&shirq_lock); |
| 90 | val = readl(reg) | (0x1 << shift); |
| 91 | writel(val, reg); |
| 92 | raw_spin_unlock(&shirq_lock); |
| 93 | } |
| 94 | |
| 95 | static struct irq_chip shirq_chip = { |
| 96 | .name = "spear-shirq", |
| 97 | .irq_mask = shirq_irq_mask, |
| 98 | .irq_unmask = shirq_irq_unmask, |
| 99 | }; |
| 100 | |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 101 | static struct spear_shirq spear300_shirq_ras1 = { |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 102 | .offset = 0, |
| 103 | .nr_irqs = 9, |
Thomas Gleixner | 4ecc832 | 2014-06-19 21:34:41 +0000 | [diff] [blame] | 104 | .mask = ((0x1 << 9) - 1) << 0, |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 105 | .irq_chip = &shirq_chip, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 106 | .regs = { |
| 107 | .enb_reg = SPEAR300_INT_ENB_MASK_REG, |
| 108 | .status_reg = SPEAR300_INT_STS_MASK_REG, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 109 | }, |
| 110 | }; |
| 111 | |
| 112 | static struct spear_shirq *spear300_shirq_blocks[] = { |
| 113 | &spear300_shirq_ras1, |
| 114 | }; |
| 115 | |
| 116 | /* spear310 shared irq registers offsets and masks */ |
| 117 | #define SPEAR310_INT_STS_MASK_REG 0x04 |
| 118 | |
| 119 | static struct spear_shirq spear310_shirq_ras1 = { |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 120 | .offset = 0, |
| 121 | .nr_irqs = 8, |
Thomas Gleixner | 4ecc832 | 2014-06-19 21:34:41 +0000 | [diff] [blame] | 122 | .mask = ((0x1 << 8) - 1) << 0, |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 123 | .irq_chip = &dummy_irq_chip, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 124 | .regs = { |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 125 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 126 | }, |
| 127 | }; |
| 128 | |
| 129 | static struct spear_shirq spear310_shirq_ras2 = { |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 130 | .offset = 8, |
| 131 | .nr_irqs = 5, |
Thomas Gleixner | 4ecc832 | 2014-06-19 21:34:41 +0000 | [diff] [blame] | 132 | .mask = ((0x1 << 5) - 1) << 8, |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 133 | .irq_chip = &dummy_irq_chip, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 134 | .regs = { |
| 135 | .enb_reg = -1, |
| 136 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 137 | }, |
| 138 | }; |
| 139 | |
| 140 | static struct spear_shirq spear310_shirq_ras3 = { |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 141 | .offset = 13, |
| 142 | .nr_irqs = 1, |
Thomas Gleixner | 4ecc832 | 2014-06-19 21:34:41 +0000 | [diff] [blame] | 143 | .mask = ((0x1 << 1) - 1) << 13, |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 144 | .irq_chip = &dummy_irq_chip, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 145 | .regs = { |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 146 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 147 | }, |
| 148 | }; |
| 149 | |
| 150 | static struct spear_shirq spear310_shirq_intrcomm_ras = { |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 151 | .offset = 14, |
| 152 | .nr_irqs = 3, |
Thomas Gleixner | 4ecc832 | 2014-06-19 21:34:41 +0000 | [diff] [blame] | 153 | .mask = ((0x1 << 3) - 1) << 14, |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 154 | .irq_chip = &dummy_irq_chip, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 155 | .regs = { |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 156 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 157 | }, |
| 158 | }; |
| 159 | |
| 160 | static struct spear_shirq *spear310_shirq_blocks[] = { |
| 161 | &spear310_shirq_ras1, |
| 162 | &spear310_shirq_ras2, |
| 163 | &spear310_shirq_ras3, |
| 164 | &spear310_shirq_intrcomm_ras, |
| 165 | }; |
| 166 | |
| 167 | /* spear320 shared irq registers offsets and masks */ |
| 168 | #define SPEAR320_INT_STS_MASK_REG 0x04 |
| 169 | #define SPEAR320_INT_CLR_MASK_REG 0x04 |
| 170 | #define SPEAR320_INT_ENB_MASK_REG 0x08 |
| 171 | |
Thomas Gleixner | 03319a1 | 2014-06-19 21:34:40 +0000 | [diff] [blame] | 172 | static struct spear_shirq spear320_shirq_ras3 = { |
| 173 | .offset = 0, |
| 174 | .nr_irqs = 7, |
Thomas Gleixner | 4ecc832 | 2014-06-19 21:34:41 +0000 | [diff] [blame] | 175 | .mask = ((0x1 << 7) - 1) << 0, |
Thomas Gleixner | 03319a1 | 2014-06-19 21:34:40 +0000 | [diff] [blame] | 176 | }; |
| 177 | |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 178 | static struct spear_shirq spear320_shirq_ras1 = { |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 179 | .offset = 7, |
| 180 | .nr_irqs = 3, |
Thomas Gleixner | 4ecc832 | 2014-06-19 21:34:41 +0000 | [diff] [blame] | 181 | .mask = ((0x1 << 3) - 1) << 7, |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 182 | .irq_chip = &dummy_irq_chip, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 183 | .regs = { |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 184 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 185 | }, |
| 186 | }; |
| 187 | |
| 188 | static struct spear_shirq spear320_shirq_ras2 = { |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 189 | .offset = 10, |
| 190 | .nr_irqs = 1, |
Thomas Gleixner | 4ecc832 | 2014-06-19 21:34:41 +0000 | [diff] [blame] | 191 | .mask = ((0x1 << 1) - 1) << 10, |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 192 | .irq_chip = &dummy_irq_chip, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 193 | .regs = { |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 194 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 195 | }, |
| 196 | }; |
| 197 | |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 198 | static struct spear_shirq spear320_shirq_intrcomm_ras = { |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 199 | .offset = 11, |
| 200 | .nr_irqs = 11, |
Thomas Gleixner | 4ecc832 | 2014-06-19 21:34:41 +0000 | [diff] [blame] | 201 | .mask = ((0x1 << 11) - 1) << 11, |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 202 | .irq_chip = &dummy_irq_chip, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 203 | .regs = { |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 204 | .status_reg = SPEAR320_INT_STS_MASK_REG, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 205 | }, |
| 206 | }; |
| 207 | |
| 208 | static struct spear_shirq *spear320_shirq_blocks[] = { |
| 209 | &spear320_shirq_ras3, |
| 210 | &spear320_shirq_ras1, |
| 211 | &spear320_shirq_ras2, |
| 212 | &spear320_shirq_intrcomm_ras, |
| 213 | }; |
| 214 | |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 215 | static void shirq_handler(unsigned irq, struct irq_desc *desc) |
| 216 | { |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 217 | struct spear_shirq *shirq = irq_get_handler_data(irq); |
Thomas Gleixner | 25dc49e | 2014-06-19 21:34:42 +0000 | [diff] [blame] | 218 | u32 pend; |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 219 | |
Thomas Gleixner | 25dc49e | 2014-06-19 21:34:42 +0000 | [diff] [blame] | 220 | pend = readl(shirq->base + shirq->regs.status_reg) & shirq->mask; |
| 221 | pend >>= shirq->offset; |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 222 | |
Thomas Gleixner | 25dc49e | 2014-06-19 21:34:42 +0000 | [diff] [blame] | 223 | while (pend) { |
| 224 | int irq = __ffs(pend); |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 225 | |
Thomas Gleixner | 25dc49e | 2014-06-19 21:34:42 +0000 | [diff] [blame] | 226 | pend &= ~(0x1 << irq); |
| 227 | generic_handle_irq(shirq->virq_base + irq); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 228 | } |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 229 | } |
| 230 | |
Thomas Gleixner | f37ecbc | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 231 | static void __init spear_shirq_register(struct spear_shirq *shirq, |
| 232 | int parent_irq) |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 233 | { |
| 234 | int i; |
| 235 | |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 236 | if (!shirq->irq_chip) |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 237 | return; |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 238 | |
Thomas Gleixner | f37ecbc | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 239 | irq_set_chained_handler(parent_irq, shirq_handler); |
| 240 | irq_set_handler_data(parent_irq, shirq); |
| 241 | |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 242 | for (i = 0; i < shirq->nr_irqs; i++) { |
| 243 | irq_set_chip_and_handler(shirq->virq_base + i, |
Thomas Gleixner | f07e42f | 2014-06-19 21:34:43 +0000 | [diff] [blame^] | 244 | shirq->irq_chip, handle_simple_irq); |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 245 | set_irq_flags(shirq->virq_base + i, IRQF_VALID); |
| 246 | irq_set_chip_data(shirq->virq_base + i, shirq); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 247 | } |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 248 | } |
| 249 | |
| 250 | static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr, |
| 251 | struct device_node *np) |
| 252 | { |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 253 | int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0; |
Thomas Gleixner | a26c06f | 2014-06-19 21:34:37 +0000 | [diff] [blame] | 254 | struct irq_domain *shirq_domain; |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 255 | void __iomem *base; |
| 256 | |
| 257 | base = of_iomap(np, 0); |
| 258 | if (!base) { |
| 259 | pr_err("%s: failed to map shirq registers\n", __func__); |
| 260 | return -ENXIO; |
| 261 | } |
| 262 | |
| 263 | for (i = 0; i < block_nr; i++) |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 264 | nr_irqs += shirq_blocks[i]->nr_irqs; |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 265 | |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 266 | virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); |
| 267 | if (IS_ERR_VALUE(virq_base)) { |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 268 | pr_err("%s: irq desc alloc failed\n", __func__); |
| 269 | goto err_unmap; |
| 270 | } |
| 271 | |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 272 | shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 273 | &irq_domain_simple_ops, NULL); |
| 274 | if (WARN_ON(!shirq_domain)) { |
| 275 | pr_warn("%s: irq domain init failed\n", __func__); |
| 276 | goto err_free_desc; |
| 277 | } |
| 278 | |
| 279 | for (i = 0; i < block_nr; i++) { |
| 280 | shirq_blocks[i]->base = base; |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 281 | shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain, |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 282 | hwirq); |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 283 | |
Thomas Gleixner | f37ecbc | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 284 | parent_irq = irq_of_parse_and_map(np, i); |
| 285 | spear_shirq_register(shirq_blocks[i], parent_irq); |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 286 | hwirq += shirq_blocks[i]->nr_irqs; |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 287 | } |
| 288 | |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 289 | return 0; |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 290 | |
| 291 | err_free_desc: |
Thomas Gleixner | c5d1d85 | 2014-06-19 21:34:39 +0000 | [diff] [blame] | 292 | irq_free_descs(virq_base, nr_irqs); |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 293 | err_unmap: |
| 294 | iounmap(base); |
| 295 | return -ENXIO; |
| 296 | } |
| 297 | |
Thomas Gleixner | 078bc00 | 2014-06-19 21:34:38 +0000 | [diff] [blame] | 298 | static int __init spear300_shirq_of_init(struct device_node *np, |
| 299 | struct device_node *parent) |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 300 | { |
| 301 | return shirq_init(spear300_shirq_blocks, |
| 302 | ARRAY_SIZE(spear300_shirq_blocks), np); |
| 303 | } |
Rob Herring | e9c5155 | 2013-01-02 09:37:56 -0600 | [diff] [blame] | 304 | IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init); |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 305 | |
Thomas Gleixner | 078bc00 | 2014-06-19 21:34:38 +0000 | [diff] [blame] | 306 | static int __init spear310_shirq_of_init(struct device_node *np, |
| 307 | struct device_node *parent) |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 308 | { |
| 309 | return shirq_init(spear310_shirq_blocks, |
| 310 | ARRAY_SIZE(spear310_shirq_blocks), np); |
| 311 | } |
Rob Herring | e9c5155 | 2013-01-02 09:37:56 -0600 | [diff] [blame] | 312 | IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init); |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 313 | |
Thomas Gleixner | 078bc00 | 2014-06-19 21:34:38 +0000 | [diff] [blame] | 314 | static int __init spear320_shirq_of_init(struct device_node *np, |
| 315 | struct device_node *parent) |
Shiraz Hashim | 80515a5a | 2012-08-03 15:33:10 +0530 | [diff] [blame] | 316 | { |
| 317 | return shirq_init(spear320_shirq_blocks, |
| 318 | ARRAY_SIZE(spear320_shirq_blocks), np); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 319 | } |
Rob Herring | e9c5155 | 2013-01-02 09:37:56 -0600 | [diff] [blame] | 320 | IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init); |