blob: 5c24e938042fd6bccb4e207d58dcb988d7c62611 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
Kristen Accardi8cf4c192005-08-16 15:16:10 -070026 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 *
28 */
29
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
Tim Schmielaude259682006-01-08 01:02:05 -080033#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <linux/pci.h>
Andrew Morton5d1b8c92005-11-13 16:06:39 -080037#include <linux/interrupt.h>
Kristen Carlson Accardi34d03412007-01-09 13:02:36 -080038#include <linux/time.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090039#include <linux/slab.h>
Andrew Morton5d1b8c92005-11-13 16:06:39 -080040
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#include "../pci.h"
42#include "pciehp.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070043
Bjorn Helgaascd84d342013-05-09 11:26:16 -060044static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
Kenji Kaneshigea0f018d2006-12-21 17:01:06 -080045{
Bjorn Helgaascd84d342013-05-09 11:26:16 -060046 return ctrl->pcie->port;
Kenji Kaneshigea0f018d2006-12-21 17:01:06 -080047}
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080049static irqreturn_t pcie_isr(int irq, void *dev_id);
50static void start_int_poll_timer(struct controller *ctrl, int sec);
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
52/* This is the interrupt polling timeout function. */
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080053static void int_poll_timeout(unsigned long data)
Linus Torvalds1da177e2005-04-16 15:20:36 -070054{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080055 struct controller *ctrl = (struct controller *)data;
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
Linus Torvalds1da177e2005-04-16 15:20:36 -070057 /* Poll for interrupt events. regs == NULL => polling */
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080058 pcie_isr(0, ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080060 init_timer(&ctrl->poll_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 if (!pciehp_poll_time)
Kenji Kaneshige40730d12007-08-09 16:09:38 -070062 pciehp_poll_time = 2; /* default polling interval is 2 sec */
Linus Torvalds1da177e2005-04-16 15:20:36 -070063
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080064 start_int_poll_timer(ctrl, pciehp_poll_time);
Linus Torvalds1da177e2005-04-16 15:20:36 -070065}
66
67/* This function starts the interrupt polling timer. */
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080068static void start_int_poll_timer(struct controller *ctrl, int sec)
Linus Torvalds1da177e2005-04-16 15:20:36 -070069{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080070 /* Clamp to sane value */
71 if ((sec <= 0) || (sec > 60))
Bjorn Helgaasf7625982013-11-14 11:28:18 -070072 sec = 2;
Linus Torvalds1da177e2005-04-16 15:20:36 -070073
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080074 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070078}
79
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -070080static inline int pciehp_request_irq(struct controller *ctrl)
81{
Kenji Kaneshigef7a10e32008-08-22 17:16:48 +090082 int retval, irq = ctrl->pcie->irq;
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -070083
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode) {
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
88 return 0;
89 }
90
91 /* Installs the interrupt handler */
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
93 if (retval)
Taku Izumi7f2feec2008-09-05 12:11:26 +090094 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
95 irq);
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -070096 return retval;
97}
98
99static inline void pciehp_free_irq(struct controller *ctrl)
100{
101 if (pciehp_poll_mode)
102 del_timer_sync(&ctrl->poll_timer);
103 else
Kenji Kaneshigef7a10e32008-08-22 17:16:48 +0900104 free_irq(ctrl->pcie->irq, ctrl);
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700105}
106
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600107static int pcie_poll_cmd(struct controller *ctrl, int timeout)
Kenji Kaneshige6592e022008-05-27 19:05:26 +0900108{
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600109 struct pci_dev *pdev = ctrl_dev(ctrl);
Kenji Kaneshige6592e022008-05-27 19:05:26 +0900110 u16 slot_status;
Kenji Kaneshige6592e022008-05-27 19:05:26 +0900111
Yijing Wangac108362015-06-19 15:57:45 +0800112 while (true) {
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700113 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
Jarod Wilson1469d172015-07-21 12:25:30 -0400114 if (slot_status == (u16) ~0) {
115 ctrl_info(ctrl, "%s: no response from device\n",
116 __func__);
117 return 0;
118 }
119
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700120 if (slot_status & PCI_EXP_SLTSTA_CC) {
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600121 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
122 PCI_EXP_SLTSTA_CC);
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900123 return 1;
Kenji Kaneshige820943b2008-06-20 12:04:33 +0900124 }
Yijing Wangac108362015-06-19 15:57:45 +0800125 if (timeout < 0)
126 break;
127 msleep(10);
128 timeout -= 10;
Kenji Kaneshige6592e022008-05-27 19:05:26 +0900129 }
130 return 0; /* timeout */
Kenji Kaneshige6592e022008-05-27 19:05:26 +0900131}
132
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600133static void pcie_wait_cmd(struct controller *ctrl)
Kenji Kaneshige44ef4ce2006-12-21 17:01:09 -0800134{
Kenji Kaneshige262303fe2006-12-21 17:01:10 -0800135 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600136 unsigned long duration = msecs_to_jiffies(msecs);
137 unsigned long cmd_timeout = ctrl->cmd_started + duration;
138 unsigned long now, timeout;
Kenji Kaneshige262303fe2006-12-21 17:01:10 -0800139 int rc;
Kenji Kaneshige44ef4ce2006-12-21 17:01:09 -0800140
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600141 /*
142 * If the controller does not generate notifications for command
143 * completions, we never need to wait between writes.
144 */
Rajat Jain6c1a32e2014-06-26 11:58:55 -0700145 if (NO_CMD_CMPL(ctrl))
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600146 return;
147
148 if (!ctrl->cmd_busy)
149 return;
150
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600151 /*
152 * Even if the command has already timed out, we want to call
153 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
154 */
155 now = jiffies;
156 if (time_before_eq(cmd_timeout, now))
157 timeout = 1;
158 else
159 timeout = cmd_timeout - now;
160
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600161 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
162 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
Kenji Kaneshiged737bdc2008-05-28 14:59:44 +0900163 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600164 else
Yinghai Lu7cbeb9f2014-09-22 20:05:45 -0600165 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600166
167 /*
168 * Controllers with errata like Intel CF118 don't generate
169 * completion notifications unless the power/indicator/interlock
170 * control bits are changed. On such controllers, we'll emit this
171 * timeout message when we wait for completion of commands that
172 * don't change those bits, e.g., commands that merely enable
173 * interrupts.
174 */
Kenji Kaneshige262303fe2006-12-21 17:01:10 -0800175 if (!rc)
Bjorn Helgaasd537a3a2014-08-15 17:18:44 -0600176 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600177 ctrl->slot_ctrl,
Yinghai Lud4338892014-09-22 20:07:35 -0600178 jiffies_to_msecs(jiffies - ctrl->cmd_started));
Kenji Kaneshige44ef4ce2006-12-21 17:01:09 -0800179}
180
Alex Williamsona5dd4b42015-06-08 17:10:50 -0600181static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
182 u16 mask, bool wait)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183{
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600184 struct pci_dev *pdev = ctrl_dev(ctrl);
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700185 u16 slot_ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186
Kenji Kaneshige44ef4ce2006-12-21 17:01:09 -0800187 mutex_lock(&ctrl->ctrl_lock);
188
Alex Williamsona5dd4b42015-06-08 17:10:50 -0600189 /*
190 * Always wait for any previous command that might still be in progress
191 */
Bjorn Helgaas3461a062014-06-13 15:06:40 -0600192 pcie_wait_cmd(ctrl);
193
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700194 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
Jarod Wilson1469d172015-07-21 12:25:30 -0400195 if (slot_ctrl == (u16) ~0) {
196 ctrl_info(ctrl, "%s: no response from device\n", __func__);
197 goto out;
198 }
199
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700200 slot_ctrl &= ~mask;
Kenji Kaneshigeb7aa1f12008-04-25 14:39:14 -0700201 slot_ctrl |= (cmd & mask);
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700202 ctrl->cmd_busy = 1;
Kenji Kaneshige2d32a9a2008-04-25 14:39:02 -0700203 smp_mb();
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700204 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600205 ctrl->cmd_started = jiffies;
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600206 ctrl->slot_ctrl = slot_ctrl;
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700207
Alex Williamsona5dd4b42015-06-08 17:10:50 -0600208 /*
209 * Optionally wait for the hardware to be ready for a new command,
210 * indicating completion of the above issued command.
211 */
212 if (wait)
213 pcie_wait_cmd(ctrl);
214
Jarod Wilson1469d172015-07-21 12:25:30 -0400215out:
Kenji Kaneshige44ef4ce2006-12-21 17:01:09 -0800216 mutex_unlock(&ctrl->ctrl_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217}
218
Alex Williamsona5dd4b42015-06-08 17:10:50 -0600219/**
220 * pcie_write_cmd - Issue controller command
221 * @ctrl: controller to which the command is issued
222 * @cmd: command value written to slot control register
223 * @mask: bitmask of slot control register to be modified
224 */
225static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
226{
227 pcie_do_write_cmd(ctrl, cmd, mask, true);
228}
229
230/* Same as above without waiting for the hardware to latch */
231static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
232{
233 pcie_do_write_cmd(ctrl, cmd, mask, false);
234}
235
Rajat Jain47033892014-02-04 18:28:43 -0800236bool pciehp_check_link_active(struct controller *ctrl)
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900237{
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600238 struct pci_dev *pdev = ctrl_dev(ctrl);
Yinghai Lu4e2ce402012-01-27 10:55:12 -0800239 u16 lnk_status;
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700240 bool ret;
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900241
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700242 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
Yinghai Lu4e2ce402012-01-27 10:55:12 -0800243 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
244
245 if (ret)
246 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
247
248 return ret;
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900249}
250
Yinghai Lubffe4f72012-01-27 10:55:13 -0800251static void __pcie_wait_link_active(struct controller *ctrl, bool active)
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900252{
253 int timeout = 1000;
254
Rajat Jain47033892014-02-04 18:28:43 -0800255 if (pciehp_check_link_active(ctrl) == active)
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900256 return;
257 while (timeout > 0) {
258 msleep(10);
259 timeout -= 10;
Rajat Jain47033892014-02-04 18:28:43 -0800260 if (pciehp_check_link_active(ctrl) == active)
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900261 return;
262 }
Yinghai Lubffe4f72012-01-27 10:55:13 -0800263 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
264 active ? "set" : "cleared");
265}
266
267static void pcie_wait_link_active(struct controller *ctrl)
268{
269 __pcie_wait_link_active(ctrl, true);
270}
271
Yinghai Lu2f5d8e42012-01-27 10:55:11 -0800272static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
273{
274 u32 l;
275 int count = 0;
276 int delay = 1000, step = 20;
277 bool found = false;
278
279 do {
280 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
281 count++;
282
283 if (found)
284 break;
285
286 msleep(step);
287 delay -= step;
288 } while (delay > 0);
289
290 if (count > 1 && pciehp_debug)
291 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
292 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
293 PCI_FUNC(devfn), count, step, l);
294
295 return found;
296}
297
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900298int pciehp_check_link_status(struct controller *ctrl)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299{
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600300 struct pci_dev *pdev = ctrl_dev(ctrl);
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700301 bool found;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302 u16 lnk_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400304 /*
305 * Data Link Layer Link Active Reporting must be capable for
306 * hot-plug capable downstream port. But old controller might
307 * not implement it. In this case, we wait for 1000 ms.
308 */
309 if (ctrl->link_active_reporting)
310 pcie_wait_link_active(ctrl);
311 else
312 msleep(1000);
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900313
Yinghai Lu2f5d8e42012-01-27 10:55:11 -0800314 /* wait 100ms before read pci conf, and try in 1s */
315 msleep(100);
316 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
317 PCI_DEVFN(0, 0));
Kenji Kaneshige0027cb32011-11-10 16:40:37 +0900318
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700319 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
Taku Izumi7f2feec2008-09-05 12:11:26 +0900320 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900321 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
322 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
Bjorn Helgaas3784e0c2015-06-15 16:28:29 -0500323 ctrl_err(ctrl, "link training error: status %#06x\n",
324 lnk_status);
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700325 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326 }
327
Yinghai Lufdbd3ce2011-11-07 07:53:23 -0800328 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
329
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700330 if (!found)
331 return -1;
Yinghai Lu2f5d8e42012-01-27 10:55:11 -0800332
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700333 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334}
335
Yinghai Lu7f822992012-01-27 10:55:14 -0800336static int __pciehp_link_set(struct controller *ctrl, bool enable)
337{
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600338 struct pci_dev *pdev = ctrl_dev(ctrl);
Yinghai Lu7f822992012-01-27 10:55:14 -0800339 u16 lnk_ctrl;
Yinghai Lu7f822992012-01-27 10:55:14 -0800340
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700341 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
Yinghai Lu7f822992012-01-27 10:55:14 -0800342
343 if (enable)
344 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
345 else
346 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
347
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700348 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
Yinghai Lu7f822992012-01-27 10:55:14 -0800349 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700350 return 0;
Yinghai Lu7f822992012-01-27 10:55:14 -0800351}
352
353static int pciehp_link_enable(struct controller *ctrl)
354{
355 return __pciehp_link_set(ctrl, true);
356}
357
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700358void pciehp_get_attention_status(struct slot *slot, u8 *status)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800360 struct controller *ctrl = slot->ctrl;
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600361 struct pci_dev *pdev = ctrl_dev(ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 u16 slot_ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700364 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900365 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
366 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700368 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
369 case PCI_EXP_SLTCTL_ATTN_IND_ON:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 *status = 1; /* On */
371 break;
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700372 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373 *status = 2; /* Blink */
374 break;
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700375 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 *status = 0; /* Off */
377 break;
378 default:
379 *status = 0xFF;
380 break;
381 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382}
383
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700384void pciehp_get_power_status(struct slot *slot, u8 *status)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800386 struct controller *ctrl = slot->ctrl;
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600387 struct pci_dev *pdev = ctrl_dev(ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 u16 slot_ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700390 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900391 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
392 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700394 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
395 case PCI_EXP_SLTCTL_PWR_ON:
396 *status = 1; /* On */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397 break;
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700398 case PCI_EXP_SLTCTL_PWR_OFF:
399 *status = 0; /* Off */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400 break;
401 default:
402 *status = 0xFF;
403 break;
404 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405}
406
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700407void pciehp_get_latch_status(struct slot *slot, u8 *status)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408{
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700409 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410 u16 slot_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700412 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900413 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414}
415
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700416void pciehp_get_adapter_status(struct slot *slot, u8 *status)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417{
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700418 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419 u16 slot_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700421 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900422 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423}
424
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900425int pciehp_query_power_fault(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426{
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700427 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 u16 slot_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700430 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900431 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432}
433
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700434void pciehp_set_attention_status(struct slot *slot, u8 value)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800436 struct controller *ctrl = slot->ctrl;
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700437 u16 slot_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438
Bjorn Helgaasaf9ab792013-12-15 17:23:54 -0700439 if (!ATTN_LED(ctrl))
440 return;
441
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 switch (value) {
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400443 case 0: /* turn off */
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700444 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
Kenji Kaneshige445f7982009-10-05 17:42:59 +0900445 break;
446 case 1: /* turn on */
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700447 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
Kenji Kaneshige445f7982009-10-05 17:42:59 +0900448 break;
449 case 2: /* turn blink */
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700450 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
Kenji Kaneshige445f7982009-10-05 17:42:59 +0900451 break;
452 default:
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700453 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 }
Alex Williamsona5dd4b42015-06-08 17:10:50 -0600455 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900456 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
457 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458}
459
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900460void pciehp_green_led_on(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800462 struct controller *ctrl = slot->ctrl;
Kenji Kaneshige71ad5562007-08-09 16:09:34 -0700463
Bjorn Helgaasaf9ab792013-12-15 17:23:54 -0700464 if (!PWR_LED(ctrl))
465 return;
466
Alex Williamsona5dd4b42015-06-08 17:10:50 -0600467 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
468 PCI_EXP_SLTCTL_PIC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900469 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700470 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
471 PCI_EXP_SLTCTL_PWR_IND_ON);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472}
473
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900474void pciehp_green_led_off(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800476 struct controller *ctrl = slot->ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477
Bjorn Helgaasaf9ab792013-12-15 17:23:54 -0700478 if (!PWR_LED(ctrl))
479 return;
480
Alex Williamsona5dd4b42015-06-08 17:10:50 -0600481 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
482 PCI_EXP_SLTCTL_PIC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900483 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700484 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
485 PCI_EXP_SLTCTL_PWR_IND_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486}
487
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900488void pciehp_green_led_blink(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800490 struct controller *ctrl = slot->ctrl;
Kenji Kaneshige71ad5562007-08-09 16:09:34 -0700491
Bjorn Helgaasaf9ab792013-12-15 17:23:54 -0700492 if (!PWR_LED(ctrl))
493 return;
494
Alex Williamsona5dd4b42015-06-08 17:10:50 -0600495 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
496 PCI_EXP_SLTCTL_PIC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900497 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700498 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
499 PCI_EXP_SLTCTL_PWR_IND_BLINK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500}
501
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400502int pciehp_power_on_slot(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800504 struct controller *ctrl = slot->ctrl;
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600505 struct pci_dev *pdev = ctrl_dev(ctrl);
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700506 u16 slot_status;
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700507 int retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508
Rajesh Shah5a49f202005-11-23 15:44:54 -0800509 /* Clear sticky power-fault bit from previous power failures */
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700510 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
Bjorn Helgaas2f2ed41c2013-12-14 13:06:40 -0700511 if (slot_status & PCI_EXP_SLTSTA_PFD)
512 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
513 PCI_EXP_SLTSTA_PFD);
Kenji Kaneshige5651c482009-11-13 15:14:10 +0900514 ctrl->power_fault_detected = 0;
Kenji Kaneshigea0f018d2006-12-21 17:01:06 -0800515
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700516 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900517 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700518 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
519 PCI_EXP_SLTCTL_PWR_ON);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520
Yinghai Lu2debd922012-01-27 10:55:15 -0800521 retval = pciehp_link_enable(ctrl);
522 if (retval)
523 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
524
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 return retval;
526}
527
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400528void pciehp_power_off_slot(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800530 struct controller *ctrl = slot->ctrl;
Kenji Kaneshigef1050a32007-12-20 19:45:09 +0900531
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700532 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900533 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700534 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
535 PCI_EXP_SLTCTL_PWR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536}
537
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800538static irqreturn_t pcie_isr(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800540 struct controller *ctrl = (struct controller *)dev_id;
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600541 struct pci_dev *pdev = ctrl_dev(ctrl);
Bjorn Helgaasb440bde2014-09-10 13:45:01 -0600542 struct pci_bus *subordinate = pdev->subordinate;
543 struct pci_dev *dev;
Kenji Kaneshige8720d272009-09-15 17:24:46 +0900544 struct slot *slot = ctrl->slot;
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700545 u16 detected, intr_loc;
Bjorn Helgaas2db0f712015-07-01 17:17:49 -0500546 u8 present;
Bjorn Helgaas4f092fe2015-06-14 21:35:13 -0500547 bool link;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700549 /*
550 * In order to guarantee that all interrupt events are
551 * serviced, we need to re-inspect Slot Status register after
552 * clearing what is presumed to be the last pending interrupt.
553 */
554 intr_loc = 0;
555 do {
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700556 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
Jarod Wilson1469d172015-07-21 12:25:30 -0400557 if (detected == (u16) ~0) {
558 ctrl_info(ctrl, "%s: no response from device\n",
559 __func__);
560 return IRQ_HANDLED;
561 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900563 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
Bjorn Helgaas2db0f712015-07-01 17:17:49 -0500564 PCI_EXP_SLTSTA_PDC |
Rajat Jaine48f1b62014-02-04 18:29:10 -0800565 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
Kenji Kaneshige81b840c2009-02-03 15:06:13 +0900566 detected &= ~intr_loc;
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700567 intr_loc |= detected;
568 if (!intr_loc)
569 return IRQ_NONE;
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700570 if (detected)
571 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
572 intr_loc);
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700573 } while (detected);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574
Bjorn Helgaas3784e0c2015-06-15 16:28:29 -0500575 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", intr_loc);
Kenji Kaneshige71ad5562007-08-09 16:09:34 -0700576
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700577 /* Check Command Complete Interrupt Pending */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900578 if (intr_loc & PCI_EXP_SLTSTA_CC) {
Kenji Kaneshige262303fe2006-12-21 17:01:10 -0800579 ctrl->cmd_busy = 0;
Kenji Kaneshige2d32a9a2008-04-25 14:39:02 -0700580 smp_mb();
Kenji Kaneshiged737bdc2008-05-28 14:59:44 +0900581 wake_up(&ctrl->queue);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582 }
583
Bjorn Helgaasb440bde2014-09-10 13:45:01 -0600584 if (subordinate) {
585 list_for_each_entry(dev, &subordinate->devices, bus_list) {
586 if (dev->ignore_hotplug) {
587 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
588 intr_loc, pci_name(dev));
589 return IRQ_HANDLED;
590 }
591 }
592 }
593
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900594 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
Kenji Kaneshigedbd79ae2008-05-27 19:03:16 +0900595 return IRQ_HANDLED;
596
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700597 /* Check Attention Button Pressed */
Bjorn Helgaas4f092fe2015-06-14 21:35:13 -0500598 if (intr_loc & PCI_EXP_SLTSTA_ABP) {
599 ctrl_info(ctrl, "Button pressed on Slot(%s)\n",
600 slot_name(slot));
601 pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS);
602 }
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800603
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700604 /* Check Presence Detect Changed */
Bjorn Helgaas4f092fe2015-06-14 21:35:13 -0500605 if (intr_loc & PCI_EXP_SLTSTA_PDC) {
606 pciehp_get_adapter_status(slot, &present);
607 ctrl_info(ctrl, "Card %spresent on Slot(%s)\n",
608 present ? "" : "not ", slot_name(slot));
609 pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON :
610 INT_PRESENCE_OFF);
611 }
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800612
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700613 /* Check Power Fault Detected */
Kenji Kaneshige99f01692009-02-03 15:06:16 +0900614 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
615 ctrl->power_fault_detected = 1;
Bjorn Helgaas4f092fe2015-06-14 21:35:13 -0500616 ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(slot));
617 pciehp_queue_interrupt_event(slot, INT_POWER_FAULT);
Kenji Kaneshige99f01692009-02-03 15:06:16 +0900618 }
Rajat Jaine48f1b62014-02-04 18:29:10 -0800619
Bjorn Helgaas4f092fe2015-06-14 21:35:13 -0500620 if (intr_loc & PCI_EXP_SLTSTA_DLLSC) {
621 link = pciehp_check_link_active(ctrl);
622 ctrl_info(ctrl, "slot(%s): Link %s event\n",
623 slot_name(slot), link ? "Up" : "Down");
624 pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP :
625 INT_LINK_DOWN);
626 }
Rajat Jaine48f1b62014-02-04 18:29:10 -0800627
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628 return IRQ_HANDLED;
629}
630
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700631void pcie_enable_notification(struct controller *ctrl)
Mark Lordecdde932007-11-21 15:07:55 -0800632{
Kenji Kaneshigec27fb8832008-04-25 14:39:05 -0700633 u16 cmd, mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634
Kenji Kaneshige5651c482009-11-13 15:14:10 +0900635 /*
636 * TBD: Power fault detected software notification support.
637 *
638 * Power fault detected software notification is not enabled
639 * now, because it caused power fault detected interrupt storm
640 * on some machines. On those machines, power fault detected
641 * bit in the slot status register was set again immediately
642 * when it is cleared in the interrupt service routine, and
643 * next power fault detected interrupt was notified again.
644 */
Rajat Jain4f854f22014-02-04 18:29:23 -0800645
646 /*
647 * Always enable link events: thus link-up and link-down shall
648 * always be treated as hotplug and unplug respectively. Enable
649 * presence detect only if Attention Button is not present.
650 */
651 cmd = PCI_EXP_SLTCTL_DLLSCE;
Kenji Kaneshigeae416e62008-04-25 14:39:06 -0700652 if (ATTN_BUTTN(ctrl))
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900653 cmd |= PCI_EXP_SLTCTL_ABPE;
Rajat Jain4f854f22014-02-04 18:29:23 -0800654 else
655 cmd |= PCI_EXP_SLTCTL_PDCE;
Kenji Kaneshigec27fb8832008-04-25 14:39:05 -0700656 if (!pciehp_poll_mode)
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900657 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
Kenji Kaneshigec27fb8832008-04-25 14:39:05 -0700658
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900659 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
Bjorn Helgaas2db0f712015-07-01 17:17:49 -0500660 PCI_EXP_SLTCTL_PFDE |
Rajat Jain4f854f22014-02-04 18:29:23 -0800661 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
662 PCI_EXP_SLTCTL_DLLSCE);
Kenji Kaneshigec27fb8832008-04-25 14:39:05 -0700663
Alex Williamsona5dd4b42015-06-08 17:10:50 -0600664 pcie_write_cmd_nowait(ctrl, cmd, mask);
Yinghai Lucf8d7b52014-09-22 20:36:09 -0600665 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
666 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667}
Mark Lord08e7a7d2007-11-28 15:11:46 -0800668
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900669static void pcie_disable_notification(struct controller *ctrl)
670{
671 u16 mask;
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700672
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900673 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
674 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
Kenji Kaneshigef22daf12009-10-05 17:40:02 +0900675 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
676 PCI_EXP_SLTCTL_DLLSCE);
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700677 pcie_write_cmd(ctrl, 0, mask);
Yinghai Lucf8d7b52014-09-22 20:36:09 -0600678 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
679 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900680}
681
Alex Williamson2e35afa2013-08-08 14:09:37 -0600682/*
683 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
Rajat Jain2b3940b2014-02-18 18:53:19 -0800684 * bus reset of the bridge, but at the same time we want to ensure that it is
685 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
686 * disable link state notification and presence detection change notification
687 * momentarily, if we see that they could interfere. Also, clear any spurious
Alex Williamson2e35afa2013-08-08 14:09:37 -0600688 * events after.
689 */
690int pciehp_reset_slot(struct slot *slot, int probe)
691{
692 struct controller *ctrl = slot->ctrl;
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600693 struct pci_dev *pdev = ctrl_dev(ctrl);
Rajat Jain06a8d892014-02-04 18:30:40 -0800694 u16 stat_mask = 0, ctrl_mask = 0;
Alex Williamson2e35afa2013-08-08 14:09:37 -0600695
696 if (probe)
697 return 0;
698
Rajat Jain2b3940b2014-02-18 18:53:19 -0800699 if (!ATTN_BUTTN(ctrl)) {
Rajat Jain06a8d892014-02-04 18:30:40 -0800700 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
701 stat_mask |= PCI_EXP_SLTSTA_PDC;
Alex Williamson2e35afa2013-08-08 14:09:37 -0600702 }
Rajat Jain06a8d892014-02-04 18:30:40 -0800703 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
704 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
705
706 pcie_write_cmd(ctrl, 0, ctrl_mask);
Yinghai Lucf8d7b52014-09-22 20:36:09 -0600707 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
708 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
Rajat Jain06a8d892014-02-04 18:30:40 -0800709 if (pciehp_poll_mode)
710 del_timer_sync(&ctrl->poll_timer);
Alex Williamson2e35afa2013-08-08 14:09:37 -0600711
712 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
713
Rajat Jain06a8d892014-02-04 18:30:40 -0800714 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
Alex Williamsona5dd4b42015-06-08 17:10:50 -0600715 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
Yinghai Lucf8d7b52014-09-22 20:36:09 -0600716 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
717 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
Rajat Jain06a8d892014-02-04 18:30:40 -0800718 if (pciehp_poll_mode)
719 int_poll_timeout(ctrl->poll_timer.data);
Alex Williamson2e35afa2013-08-08 14:09:37 -0600720
721 return 0;
722}
723
Eric W. Biedermandbc7e1e2009-01-28 19:31:18 -0800724int pcie_init_notification(struct controller *ctrl)
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900725{
726 if (pciehp_request_irq(ctrl))
727 return -1;
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700728 pcie_enable_notification(ctrl);
Eric W. Biedermandbc7e1e2009-01-28 19:31:18 -0800729 ctrl->notification_enabled = 1;
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900730 return 0;
731}
732
733static void pcie_shutdown_notification(struct controller *ctrl)
734{
Eric W. Biedermandbc7e1e2009-01-28 19:31:18 -0800735 if (ctrl->notification_enabled) {
736 pcie_disable_notification(ctrl);
737 pciehp_free_irq(ctrl);
738 ctrl->notification_enabled = 0;
739 }
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900740}
741
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900742static int pcie_init_slot(struct controller *ctrl)
743{
744 struct slot *slot;
745
746 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
747 if (!slot)
748 return -ENOMEM;
749
Kees Cookd8537542013-07-03 15:04:57 -0700750 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
Yijing Wangc2be6f92013-01-11 10:15:54 +0800751 if (!slot->wq)
752 goto abort;
753
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900754 slot->ctrl = ctrl;
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900755 mutex_init(&slot->lock);
Rajat Jain50b52fd2014-02-04 18:31:11 -0800756 mutex_init(&slot->hotplug_lock);
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900757 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
Kenji Kaneshige8720d272009-09-15 17:24:46 +0900758 ctrl->slot = slot;
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900759 return 0;
Yijing Wangc2be6f92013-01-11 10:15:54 +0800760abort:
761 kfree(slot);
762 return -ENOMEM;
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900763}
764
765static void pcie_cleanup_slot(struct controller *ctrl)
766{
Kenji Kaneshige8720d272009-09-15 17:24:46 +0900767 struct slot *slot = ctrl->slot;
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900768 cancel_delayed_work(&slot->work);
Yijing Wangc2be6f92013-01-11 10:15:54 +0800769 destroy_workqueue(slot->wq);
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900770 kfree(slot);
771}
772
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700773static inline void dbg_ctrl(struct controller *ctrl)
774{
Kenji Kaneshige385e2492009-09-15 17:30:14 +0900775 struct pci_dev *pdev = ctrl->pcie->port;
Bjorn Helgaas3784e0c2015-06-15 16:28:29 -0500776 u16 reg16;
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700777
778 if (!pciehp_debug)
779 return;
780
Taku Izumi7f2feec2008-09-05 12:11:26 +0900781 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600782 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
Taku Izumi7f2feec2008-09-05 12:11:26 +0900783 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600784 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
Taku Izumi7f2feec2008-09-05 12:11:26 +0900785 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700786}
787
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400788#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
Bjorn Helgaasafe24782013-12-14 13:06:36 -0700789
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900790struct controller *pcie_init(struct pcie_device *dev)
Mark Lord08e7a7d2007-11-28 15:11:46 -0800791{
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900792 struct controller *ctrl;
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900793 u32 slot_cap, link_cap;
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700794 struct pci_dev *pdev = dev->port;
Mark Lord08e7a7d2007-11-28 15:11:46 -0800795
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900796 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
797 if (!ctrl) {
Taku Izumi18b341b2008-10-23 11:47:32 +0900798 dev_err(&dev->device, "%s: Out of memory\n", __func__);
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900799 goto abort;
800 }
Kenji Kaneshigef7a10e32008-08-22 17:16:48 +0900801 ctrl->pcie = dev;
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700802 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700803 ctrl->slot_cap = slot_cap;
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700804 mutex_init(&ctrl->ctrl_lock);
805 init_waitqueue_head(&ctrl->queue);
806 dbg_ctrl(ctrl);
Bjorn Helgaas2cc56f32014-06-14 10:56:31 -0600807
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400808 /* Check if Data Link Layer Link Active Reporting is implemented */
809 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
Bjorn Helgaas3784e0c2015-06-15 16:28:29 -0500810 if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400811 ctrl->link_active_reporting = 1;
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900812
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900813 /* Clear all remaining event bits in Slot Status register */
Bjorn Helgaasdf726482013-12-14 13:06:47 -0700814 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
815 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
816 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
Myron Stowe0d25d352014-06-17 13:27:34 -0600817 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
Mark Lord08e7a7d2007-11-28 15:11:46 -0800818
Bjorn Helgaas3784e0c2015-06-15 16:28:29 -0500819 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
Bjorn Helgaasafe24782013-12-14 13:06:36 -0700820 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
821 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
Bjorn Helgaasafe24782013-12-14 13:06:36 -0700822 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
823 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
Bjorn Helgaas3784e0c2015-06-15 16:28:29 -0500824 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
825 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
826 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
827 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
Bjorn Helgaasafe24782013-12-14 13:06:36 -0700828 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
829 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
830 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700831
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900832 if (pcie_init_slot(ctrl))
833 goto abort_ctrl;
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700834
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900835 return ctrl;
836
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900837abort_ctrl:
838 kfree(ctrl);
Mark Lord08e7a7d2007-11-28 15:11:46 -0800839abort:
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900840 return NULL;
841}
842
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900843void pciehp_release_ctrl(struct controller *ctrl)
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900844{
845 pcie_shutdown_notification(ctrl);
846 pcie_cleanup_slot(ctrl);
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900847 kfree(ctrl);
Mark Lord08e7a7d2007-11-28 15:11:46 -0800848}