Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Standard PCI Hot Plug Driver |
| 3 | * |
| 4 | * Copyright (C) 1995,2001 Compaq Computer Corporation |
| 5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) |
| 6 | * Copyright (C) 2001 IBM Corp. |
| 7 | * Copyright (C) 2003-2004 Intel Corporation |
| 8 | * |
| 9 | * All rights reserved. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or (at |
| 14 | * your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, but |
| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
| 19 | * NON INFRINGEMENT. See the GNU General Public License for more |
| 20 | * details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * |
Kristen Accardi | 8cf4c19 | 2005-08-16 15:16:10 -0700 | [diff] [blame] | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 27 | * |
| 28 | */ |
| 29 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <linux/kernel.h> |
| 31 | #include <linux/module.h> |
| 32 | #include <linux/types.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | #include <linux/pci.h> |
Andrew Morton | d4d28dd | 2005-11-13 16:06:40 -0800 | [diff] [blame] | 34 | #include <linux/interrupt.h> |
| 35 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include "shpchp.h" |
| 37 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | /* Slot Available Register I field definition */ |
| 39 | #define SLOT_33MHZ 0x0000001f |
| 40 | #define SLOT_66MHZ_PCIX 0x00001f00 |
| 41 | #define SLOT_100MHZ_PCIX 0x001f0000 |
| 42 | #define SLOT_133MHZ_PCIX 0x1f000000 |
| 43 | |
| 44 | /* Slot Available Register II field definition */ |
| 45 | #define SLOT_66MHZ 0x0000001f |
| 46 | #define SLOT_66MHZ_PCIX_266 0x00000f00 |
| 47 | #define SLOT_100MHZ_PCIX_266 0x0000f000 |
| 48 | #define SLOT_133MHZ_PCIX_266 0x000f0000 |
| 49 | #define SLOT_66MHZ_PCIX_533 0x00f00000 |
| 50 | #define SLOT_100MHZ_PCIX_533 0x0f000000 |
| 51 | #define SLOT_133MHZ_PCIX_533 0xf0000000 |
| 52 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | /* Slot Configuration */ |
| 54 | #define SLOT_NUM 0x0000001F |
| 55 | #define FIRST_DEV_NUM 0x00001F00 |
| 56 | #define PSN 0x07FF0000 |
| 57 | #define UPDOWN 0x20000000 |
| 58 | #define MRLSENSOR 0x40000000 |
| 59 | #define ATTN_BUTTON 0x80000000 |
| 60 | |
Kenji Kaneshige | 2b34da7 | 2006-05-02 11:09:42 +0900 | [diff] [blame] | 61 | /* |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 62 | * Interrupt Locator Register definitions |
| 63 | */ |
| 64 | #define CMD_INTR_PENDING (1 << 0) |
| 65 | #define SLOT_INTR_PENDING(i) (1 << (i + 1)) |
| 66 | |
| 67 | /* |
Kenji Kaneshige | e713872 | 2006-05-02 11:12:37 +0900 | [diff] [blame] | 68 | * Controller SERR-INT Register |
| 69 | */ |
| 70 | #define GLOBAL_INTR_MASK (1 << 0) |
| 71 | #define GLOBAL_SERR_MASK (1 << 1) |
| 72 | #define COMMAND_INTR_MASK (1 << 2) |
| 73 | #define ARBITER_SERR_MASK (1 << 3) |
| 74 | #define COMMAND_DETECTED (1 << 16) |
| 75 | #define ARBITER_DETECTED (1 << 17) |
| 76 | #define SERR_INTR_RSVDZ_MASK 0xfffc0000 |
| 77 | |
| 78 | /* |
Kenji Kaneshige | 2b34da7 | 2006-05-02 11:09:42 +0900 | [diff] [blame] | 79 | * Logical Slot Register definitions |
| 80 | */ |
| 81 | #define SLOT_REG(i) (SLOT1 + (4 * i)) |
| 82 | |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 83 | #define SLOT_STATE_SHIFT (0) |
| 84 | #define SLOT_STATE_MASK (3 << 0) |
| 85 | #define SLOT_STATE_PWRONLY (1) |
| 86 | #define SLOT_STATE_ENABLED (2) |
| 87 | #define SLOT_STATE_DISABLED (3) |
| 88 | #define PWR_LED_STATE_SHIFT (2) |
| 89 | #define PWR_LED_STATE_MASK (3 << 2) |
| 90 | #define ATN_LED_STATE_SHIFT (4) |
| 91 | #define ATN_LED_STATE_MASK (3 << 4) |
| 92 | #define ATN_LED_STATE_ON (1) |
| 93 | #define ATN_LED_STATE_BLINK (2) |
| 94 | #define ATN_LED_STATE_OFF (3) |
| 95 | #define POWER_FAULT (1 << 6) |
| 96 | #define ATN_BUTTON (1 << 7) |
| 97 | #define MRL_SENSOR (1 << 8) |
| 98 | #define MHZ66_CAP (1 << 9) |
| 99 | #define PRSNT_SHIFT (10) |
| 100 | #define PRSNT_MASK (3 << 10) |
| 101 | #define PCIX_CAP_SHIFT (12) |
| 102 | #define PCIX_CAP_MASK_PI1 (3 << 12) |
| 103 | #define PCIX_CAP_MASK_PI2 (7 << 12) |
| 104 | #define PRSNT_CHANGE_DETECTED (1 << 16) |
| 105 | #define ISO_PFAULT_DETECTED (1 << 17) |
| 106 | #define BUTTON_PRESS_DETECTED (1 << 18) |
| 107 | #define MRL_CHANGE_DETECTED (1 << 19) |
| 108 | #define CON_PFAULT_DETECTED (1 << 20) |
| 109 | #define PRSNT_CHANGE_INTR_MASK (1 << 24) |
| 110 | #define ISO_PFAULT_INTR_MASK (1 << 25) |
| 111 | #define BUTTON_PRESS_INTR_MASK (1 << 26) |
| 112 | #define MRL_CHANGE_INTR_MASK (1 << 27) |
| 113 | #define CON_PFAULT_INTR_MASK (1 << 28) |
| 114 | #define MRL_CHANGE_SERR_MASK (1 << 29) |
| 115 | #define CON_PFAULT_SERR_MASK (1 << 30) |
Dan Carpenter | 3b8fdb7 | 2010-05-26 12:46:39 +0200 | [diff] [blame] | 116 | #define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 117 | |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 118 | /* |
Bjorn Helgaas | f762598 | 2013-11-14 11:28:18 -0700 | [diff] [blame] | 119 | * SHPC Command Code definitions |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 120 | * |
| 121 | * Slot Operation 00h - 3Fh |
| 122 | * Set Bus Segment Speed/Mode A 40h - 47h |
| 123 | * Power-Only All Slots 48h |
| 124 | * Enable All Slots 49h |
| 125 | * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh |
| 126 | * Reserved Command Codes 60h - BFh |
| 127 | * Vendor Specific Commands C0h - FFh |
| 128 | */ |
| 129 | #define SET_SLOT_PWR 0x01 /* Slot Operation */ |
| 130 | #define SET_SLOT_ENABLE 0x02 |
| 131 | #define SET_SLOT_DISABLE 0x03 |
| 132 | #define SET_PWR_ON 0x04 |
| 133 | #define SET_PWR_BLINK 0x08 |
| 134 | #define SET_PWR_OFF 0x0c |
| 135 | #define SET_ATTN_ON 0x10 |
| 136 | #define SET_ATTN_BLINK 0x20 |
| 137 | #define SET_ATTN_OFF 0x30 |
| 138 | #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | #define SETA_PCI_66MHZ 0x41 |
| 140 | #define SETA_PCIX_66MHZ 0x42 |
| 141 | #define SETA_PCIX_100MHZ 0x43 |
| 142 | #define SETA_PCIX_133MHZ 0x44 |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 143 | #define SETA_RESERVED1 0x45 |
| 144 | #define SETA_RESERVED2 0x46 |
| 145 | #define SETA_RESERVED3 0x47 |
| 146 | #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ |
| 147 | #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ |
| 148 | #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | #define SETB_PCI_66MHZ 0x51 |
| 150 | #define SETB_PCIX_66MHZ_PM 0x52 |
| 151 | #define SETB_PCIX_100MHZ_PM 0x53 |
| 152 | #define SETB_PCIX_133MHZ_PM 0x54 |
| 153 | #define SETB_PCIX_66MHZ_EM 0x55 |
| 154 | #define SETB_PCIX_100MHZ_EM 0x56 |
| 155 | #define SETB_PCIX_133MHZ_EM 0x57 |
| 156 | #define SETB_PCIX_66MHZ_266 0x58 |
| 157 | #define SETB_PCIX_100MHZ_266 0x59 |
| 158 | #define SETB_PCIX_133MHZ_266 0x5a |
| 159 | #define SETB_PCIX_66MHZ_533 0x5b |
| 160 | #define SETB_PCIX_100MHZ_533 0x5c |
| 161 | #define SETB_PCIX_133MHZ_533 0x5d |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 162 | #define SETB_RESERVED1 0x5e |
| 163 | #define SETB_RESERVED2 0x5f |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 165 | /* |
| 166 | * SHPC controller command error code |
| 167 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | #define SWITCH_OPEN 0x1 |
| 169 | #define INVALID_CMD 0x2 |
| 170 | #define INVALID_SPEED_MODE 0x4 |
| 171 | |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 172 | /* |
| 173 | * For accessing SHPC Working Register Set via PCI Configuration Space |
| 174 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | #define DWORD_SELECT 0x2 |
| 176 | #define DWORD_DATA 0x4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | |
| 178 | /* Field Offset in Logical Slot Register - byte boundary */ |
| 179 | #define SLOT_EVENT_LATCH 0x2 |
| 180 | #define SLOT_SERR_INT_MASK 0x3 |
| 181 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 182 | static irqreturn_t shpc_isr(int irq, void *dev_id); |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 183 | static void start_int_poll_timer(struct controller *ctrl, int sec); |
Kenji Kaneshige | d29aadd | 2006-01-26 09:59:24 +0900 | [diff] [blame] | 184 | static int hpc_check_cmd_status(struct controller *ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 185 | |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 186 | static inline u8 shpc_readb(struct controller *ctrl, int reg) |
| 187 | { |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 188 | return readb(ctrl->creg + reg); |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 189 | } |
| 190 | |
| 191 | static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) |
| 192 | { |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 193 | writeb(val, ctrl->creg + reg); |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 194 | } |
| 195 | |
| 196 | static inline u16 shpc_readw(struct controller *ctrl, int reg) |
| 197 | { |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 198 | return readw(ctrl->creg + reg); |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) |
| 202 | { |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 203 | writew(val, ctrl->creg + reg); |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 204 | } |
| 205 | |
| 206 | static inline u32 shpc_readl(struct controller *ctrl, int reg) |
| 207 | { |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 208 | return readl(ctrl->creg + reg); |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) |
| 212 | { |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 213 | writel(val, ctrl->creg + reg); |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | static inline int shpc_indirect_read(struct controller *ctrl, int index, |
| 217 | u32 *value) |
| 218 | { |
| 219 | int rc; |
| 220 | u32 cap_offset = ctrl->cap_offset; |
| 221 | struct pci_dev *pdev = ctrl->pci_dev; |
| 222 | |
| 223 | rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); |
| 224 | if (rc) |
| 225 | return rc; |
| 226 | return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); |
| 227 | } |
| 228 | |
Kenji Kaneshige | f426395 | 2006-05-12 11:13:02 +0900 | [diff] [blame] | 229 | /* |
| 230 | * This is the interrupt polling timeout function. |
| 231 | */ |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 232 | static void int_poll_timeout(unsigned long data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | { |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 234 | struct controller *ctrl = (struct controller *)data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | |
Kenji Kaneshige | f426395 | 2006-05-12 11:13:02 +0900 | [diff] [blame] | 236 | /* Poll for interrupt events. regs == NULL => polling */ |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 237 | shpc_isr(0, ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 239 | init_timer(&ctrl->poll_timer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | if (!shpchp_poll_time) |
Kenji Kaneshige | f426395 | 2006-05-12 11:13:02 +0900 | [diff] [blame] | 241 | shpchp_poll_time = 2; /* default polling interval is 2 sec */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 243 | start_int_poll_timer(ctrl, shpchp_poll_time); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 244 | } |
| 245 | |
Kenji Kaneshige | f426395 | 2006-05-12 11:13:02 +0900 | [diff] [blame] | 246 | /* |
| 247 | * This function starts the interrupt polling timer. |
| 248 | */ |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 249 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 250 | { |
Kenji Kaneshige | f426395 | 2006-05-12 11:13:02 +0900 | [diff] [blame] | 251 | /* Clamp to sane value */ |
| 252 | if ((sec <= 0) || (sec > 60)) |
| 253 | sec = 2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 254 | |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 255 | ctrl->poll_timer.function = &int_poll_timeout; |
| 256 | ctrl->poll_timer.data = (unsigned long)ctrl; |
| 257 | ctrl->poll_timer.expires = jiffies + sec * HZ; |
| 258 | add_timer(&ctrl->poll_timer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 259 | } |
| 260 | |
Kenji Kaneshige | d1729cc | 2006-09-28 15:51:21 -0700 | [diff] [blame] | 261 | static inline int is_ctrl_busy(struct controller *ctrl) |
| 262 | { |
| 263 | u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); |
| 264 | return cmd_status & 0x1; |
| 265 | } |
| 266 | |
Kenji Kaneshige | b4a1eff | 2006-09-22 12:52:37 -0700 | [diff] [blame] | 267 | /* |
| 268 | * Returns 1 if SHPC finishes executing a command within 1 sec, |
| 269 | * otherwise returns 0. |
| 270 | */ |
| 271 | static inline int shpc_poll_ctrl_busy(struct controller *ctrl) |
| 272 | { |
| 273 | int i; |
Kenji Kaneshige | b4a1eff | 2006-09-22 12:52:37 -0700 | [diff] [blame] | 274 | |
Kenji Kaneshige | d1729cc | 2006-09-28 15:51:21 -0700 | [diff] [blame] | 275 | if (!is_ctrl_busy(ctrl)) |
Kenji Kaneshige | b4a1eff | 2006-09-22 12:52:37 -0700 | [diff] [blame] | 276 | return 1; |
| 277 | |
| 278 | /* Check every 0.1 sec for a total of 1 sec */ |
| 279 | for (i = 0; i < 10; i++) { |
| 280 | msleep(100); |
Kenji Kaneshige | d1729cc | 2006-09-28 15:51:21 -0700 | [diff] [blame] | 281 | if (!is_ctrl_busy(ctrl)) |
Kenji Kaneshige | b4a1eff | 2006-09-22 12:52:37 -0700 | [diff] [blame] | 282 | return 1; |
| 283 | } |
| 284 | |
| 285 | return 0; |
| 286 | } |
| 287 | |
Kenji Kaneshige | bd62e27 | 2005-11-25 12:28:53 +0900 | [diff] [blame] | 288 | static inline int shpc_wait_cmd(struct controller *ctrl) |
| 289 | { |
| 290 | int retval = 0; |
Kenji Kaneshige | b4a1eff | 2006-09-22 12:52:37 -0700 | [diff] [blame] | 291 | unsigned long timeout = msecs_to_jiffies(1000); |
| 292 | int rc; |
| 293 | |
| 294 | if (shpchp_poll_mode) |
| 295 | rc = shpc_poll_ctrl_busy(ctrl); |
| 296 | else |
| 297 | rc = wait_event_interruptible_timeout(ctrl->queue, |
Kenji Kaneshige | 6aa562c | 2006-09-28 15:51:36 -0700 | [diff] [blame] | 298 | !is_ctrl_busy(ctrl), timeout); |
Kenji Kaneshige | d1729cc | 2006-09-28 15:51:21 -0700 | [diff] [blame] | 299 | if (!rc && is_ctrl_busy(ctrl)) { |
Kenji Kaneshige | bd62e27 | 2005-11-25 12:28:53 +0900 | [diff] [blame] | 300 | retval = -EIO; |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 301 | ctrl_err(ctrl, "Command not completed in 1000 msec\n"); |
Kenji Kaneshige | bd62e27 | 2005-11-25 12:28:53 +0900 | [diff] [blame] | 302 | } else if (rc < 0) { |
| 303 | retval = -EINTR; |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 304 | ctrl_info(ctrl, "Command was interrupted by a signal\n"); |
Kenji Kaneshige | bd62e27 | 2005-11-25 12:28:53 +0900 | [diff] [blame] | 305 | } |
Kenji Kaneshige | bd62e27 | 2005-11-25 12:28:53 +0900 | [diff] [blame] | 306 | |
| 307 | return retval; |
| 308 | } |
| 309 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 310 | static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) |
| 311 | { |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 312 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 313 | u16 cmd_status; |
| 314 | int retval = 0; |
| 315 | u16 temp_word; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | |
Kenji Kaneshige | d29aadd | 2006-01-26 09:59:24 +0900 | [diff] [blame] | 317 | mutex_lock(&slot->ctrl->cmd_lock); |
| 318 | |
Kenji Kaneshige | b4a1eff | 2006-09-22 12:52:37 -0700 | [diff] [blame] | 319 | if (!shpc_poll_ctrl_busy(ctrl)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 320 | /* After 1 sec and and the controller is still busy */ |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 321 | ctrl_err(ctrl, "Controller is still busy after 1 sec\n"); |
Kenji Kaneshige | d29aadd | 2006-01-26 09:59:24 +0900 | [diff] [blame] | 322 | retval = -EBUSY; |
| 323 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | ++t_slot; |
| 327 | temp_word = (t_slot << 8) | (cmd & 0xFF); |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 328 | ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd); |
Kenji Kaneshige | 9f593e3 | 2007-01-09 13:03:10 -0800 | [diff] [blame] | 329 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 330 | /* To make sure the Controller Busy bit is 0 before we send out the |
Kenji Kaneshige | 9f593e3 | 2007-01-09 13:03:10 -0800 | [diff] [blame] | 331 | * command. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | */ |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 333 | shpc_writew(ctrl, CMD, temp_word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | |
Kenji Kaneshige | bd62e27 | 2005-11-25 12:28:53 +0900 | [diff] [blame] | 335 | /* |
| 336 | * Wait for command completion. |
| 337 | */ |
| 338 | retval = shpc_wait_cmd(slot->ctrl); |
Kenji Kaneshige | d29aadd | 2006-01-26 09:59:24 +0900 | [diff] [blame] | 339 | if (retval) |
| 340 | goto out; |
| 341 | |
| 342 | cmd_status = hpc_check_cmd_status(slot->ctrl); |
| 343 | if (cmd_status) { |
Ryan Desfosses | 227f064 | 2014-04-18 20:13:50 -0400 | [diff] [blame] | 344 | ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n", |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 345 | cmd, cmd_status); |
Kenji Kaneshige | d29aadd | 2006-01-26 09:59:24 +0900 | [diff] [blame] | 346 | retval = -EIO; |
| 347 | } |
| 348 | out: |
| 349 | mutex_unlock(&slot->ctrl->cmd_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 350 | return retval; |
| 351 | } |
| 352 | |
| 353 | static int hpc_check_cmd_status(struct controller *ctrl) |
| 354 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 355 | int retval = 0; |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 356 | u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; |
Kenji Kaneshige | 9f593e3 | 2007-01-09 13:03:10 -0800 | [diff] [blame] | 357 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 358 | switch (cmd_status >> 1) { |
| 359 | case 0: |
| 360 | retval = 0; |
| 361 | break; |
| 362 | case 1: |
| 363 | retval = SWITCH_OPEN; |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 364 | ctrl_err(ctrl, "Switch opened!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 365 | break; |
| 366 | case 2: |
| 367 | retval = INVALID_CMD; |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 368 | ctrl_err(ctrl, "Invalid HPC command!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 369 | break; |
| 370 | case 4: |
| 371 | retval = INVALID_SPEED_MODE; |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 372 | ctrl_err(ctrl, "Invalid bus speed/mode!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 373 | break; |
| 374 | default: |
| 375 | retval = cmd_status; |
| 376 | } |
| 377 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | return retval; |
| 379 | } |
| 380 | |
| 381 | |
| 382 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
| 383 | { |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 384 | struct controller *ctrl = slot->ctrl; |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 385 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
| 386 | u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 387 | |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 388 | switch (state) { |
| 389 | case ATN_LED_STATE_ON: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 390 | *status = 1; /* On */ |
| 391 | break; |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 392 | case ATN_LED_STATE_BLINK: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 393 | *status = 2; /* Blink */ |
| 394 | break; |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 395 | case ATN_LED_STATE_OFF: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 396 | *status = 0; /* Off */ |
| 397 | break; |
| 398 | default: |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 399 | *status = 0xFF; /* Reserved */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 400 | break; |
| 401 | } |
| 402 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 403 | return 0; |
| 404 | } |
| 405 | |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 406 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | { |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 408 | struct controller *ctrl = slot->ctrl; |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 409 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
| 410 | u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 411 | |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 412 | switch (state) { |
| 413 | case SLOT_STATE_PWRONLY: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 414 | *status = 2; /* Powered only */ |
| 415 | break; |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 416 | case SLOT_STATE_ENABLED: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 417 | *status = 1; /* Enabled */ |
| 418 | break; |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 419 | case SLOT_STATE_DISABLED: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 420 | *status = 0; /* Disabled */ |
| 421 | break; |
| 422 | default: |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 423 | *status = 0xFF; /* Reserved */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 424 | break; |
| 425 | } |
| 426 | |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 427 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | |
| 431 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
| 432 | { |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 433 | struct controller *ctrl = slot->ctrl; |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 434 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 436 | *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 437 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | return 0; |
| 439 | } |
| 440 | |
| 441 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) |
| 442 | { |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 443 | struct controller *ctrl = slot->ctrl; |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 444 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
| 445 | u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 446 | |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 447 | *status = (state != 0x3) ? 1 : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 449 | return 0; |
| 450 | } |
| 451 | |
| 452 | static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) |
| 453 | { |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 454 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 455 | |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 456 | *prog_int = shpc_readb(ctrl, PROG_INTERFACE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 458 | return 0; |
| 459 | } |
| 460 | |
| 461 | static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) |
| 462 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 463 | int retval = 0; |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 464 | struct controller *ctrl = slot->ctrl; |
Kenji Kaneshige | 2b34da7 | 2006-05-02 11:09:42 +0900 | [diff] [blame] | 465 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 466 | u8 m66_cap = !!(slot_reg & MHZ66_CAP); |
Kenji Kaneshige | 795eb5c | 2006-05-02 11:11:54 +0900 | [diff] [blame] | 467 | u8 pi, pcix_cap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 468 | |
Quentin Lambert | 79e50e7 | 2014-09-07 20:03:32 +0200 | [diff] [blame] | 469 | retval = hpc_get_prog_int(slot, &pi); |
| 470 | if (retval) |
Kenji Kaneshige | 795eb5c | 2006-05-02 11:11:54 +0900 | [diff] [blame] | 471 | return retval; |
| 472 | |
| 473 | switch (pi) { |
| 474 | case 1: |
| 475 | pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; |
| 476 | break; |
| 477 | case 2: |
| 478 | pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; |
| 479 | break; |
| 480 | default: |
| 481 | return -ENODEV; |
| 482 | } |
| 483 | |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 484 | ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", |
| 485 | __func__, slot_reg, pcix_cap, m66_cap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 486 | |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 487 | switch (pcix_cap) { |
| 488 | case 0x0: |
| 489 | *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; |
| 490 | break; |
| 491 | case 0x1: |
| 492 | *value = PCI_SPEED_66MHz_PCIX; |
| 493 | break; |
| 494 | case 0x3: |
| 495 | *value = PCI_SPEED_133MHz_PCIX; |
| 496 | break; |
| 497 | case 0x4: |
| 498 | *value = PCI_SPEED_133MHz_PCIX_266; |
| 499 | break; |
| 500 | case 0x5: |
| 501 | *value = PCI_SPEED_133MHz_PCIX_533; |
| 502 | break; |
| 503 | case 0x2: |
| 504 | default: |
| 505 | *value = PCI_SPEED_UNKNOWN; |
| 506 | retval = -ENODEV; |
| 507 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | } |
| 509 | |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 510 | ctrl_dbg(ctrl, "Adapter speed = %d\n", *value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | return retval; |
| 512 | } |
| 513 | |
| 514 | static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) |
| 515 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 516 | int retval = 0; |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 517 | struct controller *ctrl = slot->ctrl; |
| 518 | u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); |
| 519 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | |
| 521 | if (pi == 2) { |
Kenji Kaneshige | 87d6c55 | 2005-11-24 11:35:05 +0900 | [diff] [blame] | 522 | *mode = (sec_bus_status & 0x0100) >> 8; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 523 | } else { |
| 524 | retval = -1; |
| 525 | } |
| 526 | |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 527 | ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 528 | return retval; |
| 529 | } |
| 530 | |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 531 | static int hpc_query_power_fault(struct slot *slot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 532 | { |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 533 | struct controller *ctrl = slot->ctrl; |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 534 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 535 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | /* Note: Logic 0 => fault */ |
Kenji Kaneshige | 5858759 | 2006-05-02 11:10:37 +0900 | [diff] [blame] | 537 | return !(slot_reg & POWER_FAULT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 538 | } |
| 539 | |
| 540 | static int hpc_set_attention_status(struct slot *slot, u8 value) |
| 541 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 542 | u8 slot_cmd = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 543 | |
| 544 | switch (value) { |
Bogicevic Sasa | ff3ce48 | 2015-12-27 13:21:11 -0800 | [diff] [blame] | 545 | case 0: |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 546 | slot_cmd = SET_ATTN_OFF; /* OFF */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 547 | break; |
| 548 | case 1: |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 549 | slot_cmd = SET_ATTN_ON; /* ON */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 550 | break; |
| 551 | case 2: |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 552 | slot_cmd = SET_ATTN_BLINK; /* BLINK */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 553 | break; |
| 554 | default: |
| 555 | return -1; |
| 556 | } |
| 557 | |
Kenji Kaneshige | d4fbf60 | 2006-05-12 11:05:59 +0900 | [diff] [blame] | 558 | return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | |
| 562 | static void hpc_set_green_led_on(struct slot *slot) |
| 563 | { |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 564 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 565 | } |
| 566 | |
| 567 | static void hpc_set_green_led_off(struct slot *slot) |
| 568 | { |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 569 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 570 | } |
| 571 | |
| 572 | static void hpc_set_green_led_blink(struct slot *slot) |
| 573 | { |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 574 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | } |
| 576 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | static void hpc_release_ctlr(struct controller *ctrl) |
| 578 | { |
Kenji Kaneshige | f7391f5 | 2006-02-21 15:45:45 -0800 | [diff] [blame] | 579 | int i; |
Kenji Kaneshige | d49f2c4 | 2006-05-03 23:34:17 +0900 | [diff] [blame] | 580 | u32 slot_reg, serr_int; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 581 | |
Kenji Kaneshige | f7391f5 | 2006-02-21 15:45:45 -0800 | [diff] [blame] | 582 | /* |
Kenji Kaneshige | 795eb5c | 2006-05-02 11:11:54 +0900 | [diff] [blame] | 583 | * Mask event interrupts and SERRs of all slots |
Kenji Kaneshige | f7391f5 | 2006-02-21 15:45:45 -0800 | [diff] [blame] | 584 | */ |
Kenji Kaneshige | 795eb5c | 2006-05-02 11:11:54 +0900 | [diff] [blame] | 585 | for (i = 0; i < ctrl->num_slots; i++) { |
| 586 | slot_reg = shpc_readl(ctrl, SLOT_REG(i)); |
| 587 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
| 588 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | |
| 589 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | |
| 590 | CON_PFAULT_SERR_MASK); |
| 591 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; |
| 592 | shpc_writel(ctrl, SLOT_REG(i), slot_reg); |
| 593 | } |
Kenji Kaneshige | f7391f5 | 2006-02-21 15:45:45 -0800 | [diff] [blame] | 594 | |
| 595 | cleanup_slots(ctrl); |
| 596 | |
Kenji Kaneshige | d49f2c4 | 2006-05-03 23:34:17 +0900 | [diff] [blame] | 597 | /* |
Joe Perches | 3609801 | 2007-12-17 11:40:11 -0800 | [diff] [blame] | 598 | * Mask SERR and System Interrupt generation |
Kenji Kaneshige | d49f2c4 | 2006-05-03 23:34:17 +0900 | [diff] [blame] | 599 | */ |
| 600 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
| 601 | serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | |
| 602 | COMMAND_INTR_MASK | ARBITER_SERR_MASK); |
| 603 | serr_int &= ~SERR_INTR_RSVDZ_MASK; |
| 604 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); |
| 605 | |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 606 | if (shpchp_poll_mode) |
| 607 | del_timer(&ctrl->poll_timer); |
| 608 | else { |
| 609 | free_irq(ctrl->pci_dev->irq, ctrl); |
| 610 | pci_disable_msi(ctrl->pci_dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 611 | } |
Kenji Kaneshige | f7391f5 | 2006-02-21 15:45:45 -0800 | [diff] [blame] | 612 | |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 613 | iounmap(ctrl->creg); |
| 614 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 615 | } |
| 616 | |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 617 | static int hpc_power_on_slot(struct slot *slot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | { |
Kenji Kaneshige | d4fbf60 | 2006-05-12 11:05:59 +0900 | [diff] [blame] | 619 | int retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 621 | retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 622 | if (retval) |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 623 | ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 624 | |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 625 | return retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 626 | } |
| 627 | |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 628 | static int hpc_slot_enable(struct slot *slot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 629 | { |
Kenji Kaneshige | d4fbf60 | 2006-05-12 11:05:59 +0900 | [diff] [blame] | 630 | int retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 631 | |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 632 | /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ |
| 633 | retval = shpc_write_cmd(slot, slot->hp_slot, |
| 634 | SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 635 | if (retval) |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 636 | ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 637 | |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 638 | return retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 639 | } |
| 640 | |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 641 | static int hpc_slot_disable(struct slot *slot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 642 | { |
Kenji Kaneshige | d4fbf60 | 2006-05-12 11:05:59 +0900 | [diff] [blame] | 643 | int retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | |
Kenji Kaneshige | 4085399 | 2006-05-12 11:11:48 +0900 | [diff] [blame] | 645 | /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ |
| 646 | retval = shpc_write_cmd(slot, slot->hp_slot, |
| 647 | SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 648 | if (retval) |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 649 | ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 651 | return retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 652 | } |
| 653 | |
Matthew Wilcox | 3749c51 | 2009-12-13 08:11:32 -0500 | [diff] [blame] | 654 | static int shpc_get_cur_bus_speed(struct controller *ctrl) |
| 655 | { |
| 656 | int retval = 0; |
| 657 | struct pci_bus *bus = ctrl->pci_dev->subordinate; |
| 658 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
| 659 | u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); |
| 660 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
| 661 | u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); |
| 662 | |
| 663 | if ((pi == 1) && (speed_mode > 4)) { |
| 664 | retval = -ENODEV; |
| 665 | goto out; |
| 666 | } |
| 667 | |
| 668 | switch (speed_mode) { |
| 669 | case 0x0: |
| 670 | bus_speed = PCI_SPEED_33MHz; |
| 671 | break; |
| 672 | case 0x1: |
| 673 | bus_speed = PCI_SPEED_66MHz; |
| 674 | break; |
| 675 | case 0x2: |
| 676 | bus_speed = PCI_SPEED_66MHz_PCIX; |
| 677 | break; |
| 678 | case 0x3: |
| 679 | bus_speed = PCI_SPEED_100MHz_PCIX; |
| 680 | break; |
| 681 | case 0x4: |
| 682 | bus_speed = PCI_SPEED_133MHz_PCIX; |
| 683 | break; |
| 684 | case 0x5: |
| 685 | bus_speed = PCI_SPEED_66MHz_PCIX_ECC; |
| 686 | break; |
| 687 | case 0x6: |
| 688 | bus_speed = PCI_SPEED_100MHz_PCIX_ECC; |
| 689 | break; |
| 690 | case 0x7: |
| 691 | bus_speed = PCI_SPEED_133MHz_PCIX_ECC; |
| 692 | break; |
| 693 | case 0x8: |
| 694 | bus_speed = PCI_SPEED_66MHz_PCIX_266; |
| 695 | break; |
| 696 | case 0x9: |
| 697 | bus_speed = PCI_SPEED_100MHz_PCIX_266; |
| 698 | break; |
| 699 | case 0xa: |
| 700 | bus_speed = PCI_SPEED_133MHz_PCIX_266; |
| 701 | break; |
| 702 | case 0xb: |
| 703 | bus_speed = PCI_SPEED_66MHz_PCIX_533; |
| 704 | break; |
| 705 | case 0xc: |
| 706 | bus_speed = PCI_SPEED_100MHz_PCIX_533; |
| 707 | break; |
| 708 | case 0xd: |
| 709 | bus_speed = PCI_SPEED_133MHz_PCIX_533; |
| 710 | break; |
| 711 | default: |
| 712 | retval = -ENODEV; |
| 713 | break; |
| 714 | } |
| 715 | |
| 716 | out: |
| 717 | bus->cur_bus_speed = bus_speed; |
| 718 | dbg("Current bus speed = %d\n", bus_speed); |
| 719 | return retval; |
| 720 | } |
| 721 | |
| 722 | |
Ryan Desfosses | 3c78bc6 | 2014-04-18 20:13:49 -0400 | [diff] [blame] | 723 | static int hpc_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 724 | { |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 725 | int retval; |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 726 | struct controller *ctrl = slot->ctrl; |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 727 | u8 pi, cmd; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 728 | |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 729 | pi = shpc_readb(ctrl, PROG_INTERFACE); |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 730 | if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) |
| 731 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 732 | |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 733 | switch (value) { |
| 734 | case PCI_SPEED_33MHz: |
| 735 | cmd = SETA_PCI_33MHZ; |
| 736 | break; |
| 737 | case PCI_SPEED_66MHz: |
| 738 | cmd = SETA_PCI_66MHZ; |
| 739 | break; |
| 740 | case PCI_SPEED_66MHz_PCIX: |
| 741 | cmd = SETA_PCIX_66MHZ; |
| 742 | break; |
| 743 | case PCI_SPEED_100MHz_PCIX: |
| 744 | cmd = SETA_PCIX_100MHZ; |
| 745 | break; |
| 746 | case PCI_SPEED_133MHz_PCIX: |
| 747 | cmd = SETA_PCIX_133MHZ; |
| 748 | break; |
| 749 | case PCI_SPEED_66MHz_PCIX_ECC: |
| 750 | cmd = SETB_PCIX_66MHZ_EM; |
| 751 | break; |
| 752 | case PCI_SPEED_100MHz_PCIX_ECC: |
| 753 | cmd = SETB_PCIX_100MHZ_EM; |
| 754 | break; |
| 755 | case PCI_SPEED_133MHz_PCIX_ECC: |
| 756 | cmd = SETB_PCIX_133MHZ_EM; |
| 757 | break; |
| 758 | case PCI_SPEED_66MHz_PCIX_266: |
| 759 | cmd = SETB_PCIX_66MHZ_266; |
| 760 | break; |
| 761 | case PCI_SPEED_100MHz_PCIX_266: |
| 762 | cmd = SETB_PCIX_100MHZ_266; |
| 763 | break; |
| 764 | case PCI_SPEED_133MHz_PCIX_266: |
| 765 | cmd = SETB_PCIX_133MHZ_266; |
| 766 | break; |
| 767 | case PCI_SPEED_66MHz_PCIX_533: |
| 768 | cmd = SETB_PCIX_66MHZ_533; |
| 769 | break; |
| 770 | case PCI_SPEED_100MHz_PCIX_533: |
| 771 | cmd = SETB_PCIX_100MHZ_533; |
| 772 | break; |
| 773 | case PCI_SPEED_133MHz_PCIX_533: |
| 774 | cmd = SETB_PCIX_133MHZ_533; |
| 775 | break; |
| 776 | default: |
| 777 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 778 | } |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 779 | |
| 780 | retval = shpc_write_cmd(slot, 0, cmd); |
| 781 | if (retval) |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 782 | ctrl_err(ctrl, "%s: Write command failed!\n", __func__); |
Matthew Wilcox | 3749c51 | 2009-12-13 08:11:32 -0500 | [diff] [blame] | 783 | else |
| 784 | shpc_get_cur_bus_speed(ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 785 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 786 | return retval; |
| 787 | } |
| 788 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 789 | static irqreturn_t shpc_isr(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 790 | { |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 791 | struct controller *ctrl = (struct controller *)dev_id; |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 792 | u32 serr_int, slot_reg, intr_loc, intr_loc2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 793 | int hp_slot; |
| 794 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 795 | /* Check to see if it was our interrupt */ |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 796 | intr_loc = shpc_readl(ctrl, INTR_LOC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 797 | if (!intr_loc) |
| 798 | return IRQ_NONE; |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 799 | |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 800 | ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 801 | |
Quentin Lambert | 382a9c9 | 2014-09-07 20:02:04 +0200 | [diff] [blame] | 802 | if (!shpchp_poll_mode) { |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 803 | /* |
| 804 | * Mask Global Interrupt Mask - see implementation |
| 805 | * note on p. 139 of SHPC spec rev 1.0 |
| 806 | */ |
| 807 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
| 808 | serr_int |= GLOBAL_INTR_MASK; |
| 809 | serr_int &= ~SERR_INTR_RSVDZ_MASK; |
| 810 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 811 | |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 812 | intr_loc2 = shpc_readl(ctrl, INTR_LOC); |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 813 | ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 814 | } |
| 815 | |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 816 | if (intr_loc & CMD_INTR_PENDING) { |
Kenji Kaneshige | 9f593e3 | 2007-01-09 13:03:10 -0800 | [diff] [blame] | 817 | /* |
| 818 | * Command Complete Interrupt Pending |
Kenji Kaneshige | f467f61 | 2005-11-24 11:39:29 +0900 | [diff] [blame] | 819 | * RO only - clear by writing 1 to the Command Completion |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 820 | * Detect bit in Controller SERR-INT register |
| 821 | */ |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 822 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
| 823 | serr_int &= ~SERR_INTR_RSVDZ_MASK; |
| 824 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); |
| 825 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 826 | wake_up_interruptible(&ctrl->queue); |
| 827 | } |
| 828 | |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 829 | if (!(intr_loc & ~CMD_INTR_PENDING)) |
Kenji Kaneshige | e4e7304 | 2006-01-26 10:05:57 +0900 | [diff] [blame] | 830 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 831 | |
Kenji Kaneshige | 9f593e3 | 2007-01-09 13:03:10 -0800 | [diff] [blame] | 832 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 833 | /* To find out which slot has interrupt pending */ |
| 834 | if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) |
| 835 | continue; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 836 | |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 837 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 838 | ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n", |
| 839 | hp_slot, slot_reg); |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 840 | |
| 841 | if (slot_reg & MRL_CHANGE_DETECTED) |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 842 | shpchp_handle_switch_change(hp_slot, ctrl); |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 843 | |
| 844 | if (slot_reg & BUTTON_PRESS_DETECTED) |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 845 | shpchp_handle_attention_button(hp_slot, ctrl); |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 846 | |
| 847 | if (slot_reg & PRSNT_CHANGE_DETECTED) |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 848 | shpchp_handle_presence_change(hp_slot, ctrl); |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 849 | |
| 850 | if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 851 | shpchp_handle_power_fault(hp_slot, ctrl); |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 852 | |
| 853 | /* Clear all slot events */ |
| 854 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; |
| 855 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 856 | } |
Kenji Kaneshige | e4e7304 | 2006-01-26 10:05:57 +0900 | [diff] [blame] | 857 | out: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 858 | if (!shpchp_poll_mode) { |
| 859 | /* Unmask Global Interrupt Mask */ |
Kenji Kaneshige | c4cecc1 | 2006-05-12 11:10:56 +0900 | [diff] [blame] | 860 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
| 861 | serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); |
| 862 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 863 | } |
Kenji Kaneshige | 9f593e3 | 2007-01-09 13:03:10 -0800 | [diff] [blame] | 864 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 865 | return IRQ_HANDLED; |
| 866 | } |
| 867 | |
Matthew Wilcox | 3749c51 | 2009-12-13 08:11:32 -0500 | [diff] [blame] | 868 | static int shpc_get_max_bus_speed(struct controller *ctrl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 869 | { |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 870 | int retval = 0; |
Matthew Wilcox | 3749c51 | 2009-12-13 08:11:32 -0500 | [diff] [blame] | 871 | struct pci_bus *bus = ctrl->pci_dev->subordinate; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 872 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 873 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
| 874 | u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); |
| 875 | u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 876 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 877 | if (pi == 2) { |
Kenji Kaneshige | 6558b6a | 2005-11-24 13:44:01 +0900 | [diff] [blame] | 878 | if (slot_avail2 & SLOT_133MHZ_PCIX_533) |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 879 | bus_speed = PCI_SPEED_133MHz_PCIX_533; |
Kenji Kaneshige | 6558b6a | 2005-11-24 13:44:01 +0900 | [diff] [blame] | 880 | else if (slot_avail2 & SLOT_100MHZ_PCIX_533) |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 881 | bus_speed = PCI_SPEED_100MHz_PCIX_533; |
Kenji Kaneshige | 6558b6a | 2005-11-24 13:44:01 +0900 | [diff] [blame] | 882 | else if (slot_avail2 & SLOT_66MHZ_PCIX_533) |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 883 | bus_speed = PCI_SPEED_66MHz_PCIX_533; |
Kenji Kaneshige | 6558b6a | 2005-11-24 13:44:01 +0900 | [diff] [blame] | 884 | else if (slot_avail2 & SLOT_133MHZ_PCIX_266) |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 885 | bus_speed = PCI_SPEED_133MHz_PCIX_266; |
Kenji Kaneshige | 6558b6a | 2005-11-24 13:44:01 +0900 | [diff] [blame] | 886 | else if (slot_avail2 & SLOT_100MHZ_PCIX_266) |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 887 | bus_speed = PCI_SPEED_100MHz_PCIX_266; |
Kenji Kaneshige | 6558b6a | 2005-11-24 13:44:01 +0900 | [diff] [blame] | 888 | else if (slot_avail2 & SLOT_66MHZ_PCIX_266) |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 889 | bus_speed = PCI_SPEED_66MHz_PCIX_266; |
| 890 | } |
| 891 | |
| 892 | if (bus_speed == PCI_SPEED_UNKNOWN) { |
Kenji Kaneshige | 6558b6a | 2005-11-24 13:44:01 +0900 | [diff] [blame] | 893 | if (slot_avail1 & SLOT_133MHZ_PCIX) |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 894 | bus_speed = PCI_SPEED_133MHz_PCIX; |
Kenji Kaneshige | 6558b6a | 2005-11-24 13:44:01 +0900 | [diff] [blame] | 895 | else if (slot_avail1 & SLOT_100MHZ_PCIX) |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 896 | bus_speed = PCI_SPEED_100MHz_PCIX; |
Kenji Kaneshige | 6558b6a | 2005-11-24 13:44:01 +0900 | [diff] [blame] | 897 | else if (slot_avail1 & SLOT_66MHZ_PCIX) |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 898 | bus_speed = PCI_SPEED_66MHz_PCIX; |
Kenji Kaneshige | 6558b6a | 2005-11-24 13:44:01 +0900 | [diff] [blame] | 899 | else if (slot_avail2 & SLOT_66MHZ) |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 900 | bus_speed = PCI_SPEED_66MHz; |
Kenji Kaneshige | 6558b6a | 2005-11-24 13:44:01 +0900 | [diff] [blame] | 901 | else if (slot_avail1 & SLOT_33MHZ) |
Kenji Kaneshige | 0afabe9 | 2006-03-01 14:55:11 +0900 | [diff] [blame] | 902 | bus_speed = PCI_SPEED_33MHz; |
| 903 | else |
| 904 | retval = -ENODEV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 905 | } |
| 906 | |
Matthew Wilcox | 3749c51 | 2009-12-13 08:11:32 -0500 | [diff] [blame] | 907 | bus->max_bus_speed = bus_speed; |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 908 | ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed); |
Kenji Kaneshige | 1555b33 | 2007-01-09 13:03:01 -0800 | [diff] [blame] | 909 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 910 | return retval; |
| 911 | } |
| 912 | |
Julia Lawall | bd79008 | 2015-12-23 21:35:35 +0100 | [diff] [blame] | 913 | static const struct hpc_ops shpchp_hpc_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 914 | .power_on_slot = hpc_power_on_slot, |
| 915 | .slot_enable = hpc_slot_enable, |
| 916 | .slot_disable = hpc_slot_disable, |
Kenji Kaneshige | 9f593e3 | 2007-01-09 13:03:10 -0800 | [diff] [blame] | 917 | .set_bus_speed_mode = hpc_set_bus_speed_mode, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 918 | .set_attention_status = hpc_set_attention_status, |
| 919 | .get_power_status = hpc_get_power_status, |
| 920 | .get_attention_status = hpc_get_attention_status, |
| 921 | .get_latch_status = hpc_get_latch_status, |
| 922 | .get_adapter_status = hpc_get_adapter_status, |
| 923 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | .get_adapter_speed = hpc_get_adapter_speed, |
| 925 | .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, |
| 926 | .get_prog_int = hpc_get_prog_int, |
| 927 | |
| 928 | .query_power_fault = hpc_query_power_fault, |
| 929 | .green_led_on = hpc_set_green_led_on, |
| 930 | .green_led_off = hpc_set_green_led_off, |
| 931 | .green_led_blink = hpc_set_green_led_blink, |
Kenji Kaneshige | 9f593e3 | 2007-01-09 13:03:10 -0800 | [diff] [blame] | 932 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 933 | .release_ctlr = hpc_release_ctlr, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 934 | }; |
| 935 | |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 936 | int shpc_init(struct controller *ctrl, struct pci_dev *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 937 | { |
Amol Lad | 662a98f | 2006-10-05 12:07:32 +0530 | [diff] [blame] | 938 | int rc = -1, num_slots = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 939 | u8 hp_slot; |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 940 | u32 shpc_base_offset; |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 941 | u32 tempdword, slot_reg, slot_config; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 942 | u8 i; |
| 943 | |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 944 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 945 | ctrl_dbg(ctrl, "Hotplug Controller:\n"); |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 946 | |
Bjorn Helgaas | 4cac2eb | 2011-08-23 10:16:43 -0600 | [diff] [blame] | 947 | if (pdev->vendor == PCI_VENDOR_ID_AMD && |
| 948 | pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) { |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 949 | /* amd shpc driver doesn't use Base Offset; assume 0 */ |
| 950 | ctrl->mmio_base = pci_resource_start(pdev, 0); |
| 951 | ctrl->mmio_size = pci_resource_len(pdev, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 952 | } else { |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 953 | ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); |
| 954 | if (!ctrl->cap_offset) { |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 955 | ctrl_err(ctrl, "Cannot find PCI capability\n"); |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 956 | goto abort; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 957 | } |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 958 | ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset); |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 959 | |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 960 | rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 961 | if (rc) { |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 962 | ctrl_err(ctrl, "Cannot read base_offset\n"); |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 963 | goto abort; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 964 | } |
| 965 | |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 966 | rc = shpc_indirect_read(ctrl, 3, &tempdword); |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 967 | if (rc) { |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 968 | ctrl_err(ctrl, "Cannot read slot config\n"); |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 969 | goto abort; |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 970 | } |
| 971 | num_slots = tempdword & SLOT_NUM; |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 972 | ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots); |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 973 | |
| 974 | for (i = 0; i < 9 + num_slots; i++) { |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 975 | rc = shpc_indirect_read(ctrl, i, &tempdword); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 976 | if (rc) { |
Ryan Desfosses | 227f064 | 2014-04-18 20:13:50 -0400 | [diff] [blame] | 977 | ctrl_err(ctrl, "Cannot read creg (index = %d)\n", |
| 978 | i); |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 979 | goto abort; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 980 | } |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 981 | ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 982 | } |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 983 | |
| 984 | ctrl->mmio_base = |
| 985 | pci_resource_start(pdev, 0) + shpc_base_offset; |
| 986 | ctrl->mmio_size = 0x24 + 0x4 * num_slots; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 987 | } |
| 988 | |
Taku Izumi | f98ca31 | 2008-10-23 11:52:12 +0900 | [diff] [blame] | 989 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
| 990 | pdev->vendor, pdev->device, pdev->subsystem_vendor, |
| 991 | pdev->subsystem_device); |
Kenji Kaneshige | 9f593e3 | 2007-01-09 13:03:10 -0800 | [diff] [blame] | 992 | |
Amol Lad | 662a98f | 2006-10-05 12:07:32 +0530 | [diff] [blame] | 993 | rc = pci_enable_device(pdev); |
| 994 | if (rc) { |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 995 | ctrl_err(ctrl, "pci_enable_device failed\n"); |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 996 | goto abort; |
Amol Lad | 662a98f | 2006-10-05 12:07:32 +0530 | [diff] [blame] | 997 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 998 | |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 999 | if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 1000 | ctrl_err(ctrl, "Cannot reserve MMIO region\n"); |
Amol Lad | 662a98f | 2006-10-05 12:07:32 +0530 | [diff] [blame] | 1001 | rc = -1; |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 1002 | goto abort; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1003 | } |
| 1004 | |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 1005 | ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); |
| 1006 | if (!ctrl->creg) { |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 1007 | ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n", |
| 1008 | ctrl->mmio_size, ctrl->mmio_base); |
Kenji Kaneshige | 0455986 | 2005-11-24 11:36:59 +0900 | [diff] [blame] | 1009 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); |
Amol Lad | 662a98f | 2006-10-05 12:07:32 +0530 | [diff] [blame] | 1010 | rc = -1; |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 1011 | goto abort; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1012 | } |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 1013 | ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1014 | |
Ingo Molnar | 6aa4cdd | 2006-01-13 16:02:15 +0100 | [diff] [blame] | 1015 | mutex_init(&ctrl->crit_sect); |
Kenji Kaneshige | d29aadd | 2006-01-26 09:59:24 +0900 | [diff] [blame] | 1016 | mutex_init(&ctrl->cmd_lock); |
| 1017 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1018 | /* Setup wait queue */ |
| 1019 | init_waitqueue_head(&ctrl->queue); |
| 1020 | |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 1021 | ctrl->hpc_ops = &shpchp_hpc_ops; |
| 1022 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1023 | /* Return PCI Controller Info */ |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 1024 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 1025 | ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; |
| 1026 | ctrl->num_slots = slot_config & SLOT_NUM; |
| 1027 | ctrl->first_slot = (slot_config & PSN) >> 16; |
| 1028 | ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1029 | |
| 1030 | /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 1031 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 1032 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
Kenji Kaneshige | e713872 | 2006-05-02 11:12:37 +0900 | [diff] [blame] | 1033 | tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | |
| 1034 | COMMAND_INTR_MASK | ARBITER_SERR_MASK); |
| 1035 | tempdword &= ~SERR_INTR_RSVDZ_MASK; |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 1036 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
| 1037 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 1038 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1039 | |
| 1040 | /* Mask the MRL sensor SERR Mask of individual slot in |
| 1041 | * Slot SERR-INT Mask & clear all the existing event if any |
| 1042 | */ |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 1043 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
Kenji Kaneshige | 2b34da7 | 2006-05-02 11:09:42 +0900 | [diff] [blame] | 1044 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 1045 | ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", |
| 1046 | hp_slot, slot_reg); |
Kenji Kaneshige | 795eb5c | 2006-05-02 11:11:54 +0900 | [diff] [blame] | 1047 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
| 1048 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | |
| 1049 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | |
| 1050 | CON_PFAULT_SERR_MASK); |
| 1051 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; |
| 1052 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1053 | } |
Kenji Kaneshige | 9f593e3 | 2007-01-09 13:03:10 -0800 | [diff] [blame] | 1054 | |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 1055 | if (shpchp_poll_mode) { |
| 1056 | /* Install interrupt polling timer. Start with 10 sec delay */ |
| 1057 | init_timer(&ctrl->poll_timer); |
| 1058 | start_int_poll_timer(ctrl, 10); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1059 | } else { |
| 1060 | /* Installs the interrupt handler */ |
| 1061 | rc = pci_enable_msi(pdev); |
| 1062 | if (rc) { |
Ryan Desfosses | 227f064 | 2014-04-18 20:13:50 -0400 | [diff] [blame] | 1063 | ctrl_info(ctrl, "Can't get msi for the hotplug controller\n"); |
| 1064 | ctrl_info(ctrl, "Use INTx for the hotplug controller\n"); |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 1065 | } |
Kenji Kaneshige | 9f593e3 | 2007-01-09 13:03:10 -0800 | [diff] [blame] | 1066 | |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 1067 | rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, |
| 1068 | MY_NAME, (void *)ctrl); |
Tejun Heo | e24dcbe | 2010-10-18 08:33:02 +0200 | [diff] [blame] | 1069 | ctrl_dbg(ctrl, "request_irq %d (returns %d)\n", |
| 1070 | ctrl->pci_dev->irq, rc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1071 | if (rc) { |
Ryan Desfosses | 227f064 | 2014-04-18 20:13:50 -0400 | [diff] [blame] | 1072 | ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n", |
| 1073 | ctrl->pci_dev->irq); |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 1074 | goto abort_iounmap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1075 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1076 | } |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 1077 | ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1078 | |
Matthew Wilcox | 3749c51 | 2009-12-13 08:11:32 -0500 | [diff] [blame] | 1079 | shpc_get_max_bus_speed(ctrl); |
| 1080 | shpc_get_cur_bus_speed(ctrl); |
| 1081 | |
Kenji Kaneshige | 795eb5c | 2006-05-02 11:11:54 +0900 | [diff] [blame] | 1082 | /* |
| 1083 | * Unmask all event interrupts of all slots |
| 1084 | */ |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 1085 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
Kenji Kaneshige | 2b34da7 | 2006-05-02 11:09:42 +0900 | [diff] [blame] | 1086 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 1087 | ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", |
| 1088 | hp_slot, slot_reg); |
Kenji Kaneshige | 795eb5c | 2006-05-02 11:11:54 +0900 | [diff] [blame] | 1089 | slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
| 1090 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | |
| 1091 | CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); |
| 1092 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1093 | } |
| 1094 | if (!shpchp_poll_mode) { |
| 1095 | /* Unmask all general input interrupts and SERR */ |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 1096 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
Kenji Kaneshige | e713872 | 2006-05-02 11:12:37 +0900 | [diff] [blame] | 1097 | tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | |
| 1098 | SERR_INTR_RSVDZ_MASK); |
Kenji Kaneshige | 75d97c5 | 2006-05-02 11:08:42 +0900 | [diff] [blame] | 1099 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
| 1100 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
Taku Izumi | be7bce2 | 2008-10-23 11:54:39 +0900 | [diff] [blame] | 1101 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1102 | } |
| 1103 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1104 | return 0; |
| 1105 | |
| 1106 | /* We end up here for the many possible ways to fail this API. */ |
Kenji Kaneshige | 0abe68c | 2006-12-16 15:25:34 -0800 | [diff] [blame] | 1107 | abort_iounmap: |
| 1108 | iounmap(ctrl->creg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1109 | abort: |
Amol Lad | 662a98f | 2006-10-05 12:07:32 +0530 | [diff] [blame] | 1110 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1111 | } |