blob: 4ae5a3d1074e19c9a203f7433cfc12e1c7724042 [file] [log] [blame]
Dave Airlied985c102006-01-02 21:32:48 +11001/* radeon_state.c -- State support for Radeon -*- linux-c -*- */
2/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Gareth Hughes <gareth@valinux.com>
27 * Kevin E. Martin <martin@valinux.com>
28 */
29
30#include "drmP.h"
31#include "drm.h"
Pauli Nieminenb4fe9452010-02-01 19:11:16 +020032#include "drm_buffer.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include "drm_sarea.h"
34#include "radeon_drm.h"
35#include "radeon_drv.h"
36
37/* ================================================================
38 * Helper functions for client state checking and fixup
39 */
40
Dave Airlieb5e89ed2005-09-25 14:28:13 +100041static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
42 dev_priv,
Eric Anholt6c340ea2007-08-25 20:23:09 +100043 struct drm_file * file_priv,
Dave Airlieb3a83632005-09-30 18:37:36 +100044 u32 *offset)
Dave Airlieb5e89ed2005-09-25 14:28:13 +100045{
Michel Daenzer214ff132006-09-22 04:12:11 +100046 u64 off = *offset;
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +110047 u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -070048 struct drm_radeon_driver_file_fields *radeon_priv;
49
Dave Airlied5ea7022006-03-19 19:37:55 +110050 /* Hrm ... the story of the offset ... So this function converts
51 * the various ideas of what userland clients might have for an
52 * offset in the card address space into an offset into the card
53 * address space :) So with a sane client, it should just keep
54 * the value intact and just do some boundary checking. However,
55 * not all clients are sane. Some older clients pass us 0 based
56 * offsets relative to the start of the framebuffer and some may
57 * assume the AGP aperture it appended to the framebuffer, so we
58 * try to detect those cases and fix them up.
59 *
60 * Note: It might be a good idea here to make sure the offset lands
61 * in some "allowed" area to protect things like the PCIE GART...
62 */
63
64 /* First, the best case, the offset already lands in either the
65 * framebuffer or the GART mapped space
66 */
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +110067 if (radeon_check_offset(dev_priv, off))
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 return 0;
69
Dave Airlied5ea7022006-03-19 19:37:55 +110070 /* Ok, that didn't happen... now check if we have a zero based
71 * offset that fits in the framebuffer + gart space, apply the
72 * magic offset we get from SETPARAM or calculated from fb_location
73 */
74 if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
Eric Anholt6c340ea2007-08-25 20:23:09 +100075 radeon_priv = file_priv->driver_priv;
Dave Airlied5ea7022006-03-19 19:37:55 +110076 off += radeon_priv->radeon_fb_delta;
77 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
Dave Airlied5ea7022006-03-19 19:37:55 +110079 /* Finally, assume we aimed at a GART offset if beyond the fb */
Michel Daenzer214ff132006-09-22 04:12:11 +100080 if (off > fb_end)
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +110081 off = off - fb_end - 1 + dev_priv->gart_vm_start;
Linus Torvalds1da177e2005-04-16 15:20:36 -070082
Dave Airlied5ea7022006-03-19 19:37:55 +110083 /* Now recheck and fail if out of bounds */
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +110084 if (radeon_check_offset(dev_priv, off)) {
Michel Daenzer214ff132006-09-22 04:12:11 +100085 DRM_DEBUG("offset fixed up to 0x%x\n", (unsigned int)off);
Dave Airlied5ea7022006-03-19 19:37:55 +110086 *offset = off;
87 return 0;
88 }
Eric Anholt20caafa2007-08-25 19:22:43 +100089 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -070090}
91
Dave Airlieb5e89ed2005-09-25 14:28:13 +100092static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
93 dev_priv,
Eric Anholt6c340ea2007-08-25 20:23:09 +100094 struct drm_file *file_priv,
Pauli Nieminenb4fe9452010-02-01 19:11:16 +020095 int id, struct drm_buffer *buf)
Dave Airlieb5e89ed2005-09-25 14:28:13 +100096{
Pauli Nieminenb4fe9452010-02-01 19:11:16 +020097 u32 *data;
Dave Airlieb5e89ed2005-09-25 14:28:13 +100098 switch (id) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
100 case RADEON_EMIT_PP_MISC:
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200101 data = drm_buffer_pointer_to_dword(buf,
102 (RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4);
103
104 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000105 DRM_ERROR("Invalid depth buffer offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000106 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107 }
Dave Airlie566d84d2010-02-24 17:17:13 +1000108 dev_priv->have_z_offset = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 break;
110
111 case RADEON_EMIT_PP_CNTL:
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200112 data = drm_buffer_pointer_to_dword(buf,
113 (RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4);
114
115 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000116 DRM_ERROR("Invalid colour buffer offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000117 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 }
119 break;
120
121 case R200_EMIT_PP_TXOFFSET_0:
122 case R200_EMIT_PP_TXOFFSET_1:
123 case R200_EMIT_PP_TXOFFSET_2:
124 case R200_EMIT_PP_TXOFFSET_3:
125 case R200_EMIT_PP_TXOFFSET_4:
126 case R200_EMIT_PP_TXOFFSET_5:
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200127 data = drm_buffer_pointer_to_dword(buf, 0);
128 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000129 DRM_ERROR("Invalid R200 texture offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000130 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 }
132 break;
133
134 case RADEON_EMIT_PP_TXFILTER_0:
135 case RADEON_EMIT_PP_TXFILTER_1:
136 case RADEON_EMIT_PP_TXFILTER_2:
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200137 data = drm_buffer_pointer_to_dword(buf,
138 (RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4);
139 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000140 DRM_ERROR("Invalid R100 texture offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000141 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142 }
143 break;
144
145 case R200_EMIT_PP_CUBIC_OFFSETS_0:
146 case R200_EMIT_PP_CUBIC_OFFSETS_1:
147 case R200_EMIT_PP_CUBIC_OFFSETS_2:
148 case R200_EMIT_PP_CUBIC_OFFSETS_3:
149 case R200_EMIT_PP_CUBIC_OFFSETS_4:
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000150 case R200_EMIT_PP_CUBIC_OFFSETS_5:{
151 int i;
152 for (i = 0; i < 5; i++) {
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200153 data = drm_buffer_pointer_to_dword(buf, i);
Dave Airlied985c102006-01-02 21:32:48 +1100154 if (radeon_check_and_fixup_offset(dev_priv,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000155 file_priv,
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200156 data)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000157 DRM_ERROR
158 ("Invalid R200 cubic texture offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000159 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000160 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000162 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164
165 case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
166 case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
167 case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{
168 int i;
169 for (i = 0; i < 5; i++) {
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200170 data = drm_buffer_pointer_to_dword(buf, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 if (radeon_check_and_fixup_offset(dev_priv,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000172 file_priv,
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200173 data)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174 DRM_ERROR
175 ("Invalid R100 cubic texture offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000176 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 }
178 }
179 }
180 break;
181
Roland Scheidegger18f29052006-08-30 23:17:55 +0100182 case R200_EMIT_VAP_CTL:{
183 RING_LOCALS;
184 BEGIN_RING(2);
185 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
186 ADVANCE_RING();
187 }
188 break;
189
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190 case RADEON_EMIT_RB3D_COLORPITCH:
191 case RADEON_EMIT_RE_LINE_PATTERN:
192 case RADEON_EMIT_SE_LINE_WIDTH:
193 case RADEON_EMIT_PP_LUM_MATRIX:
194 case RADEON_EMIT_PP_ROT_MATRIX_0:
195 case RADEON_EMIT_RB3D_STENCILREFMASK:
196 case RADEON_EMIT_SE_VPORT_XSCALE:
197 case RADEON_EMIT_SE_CNTL:
198 case RADEON_EMIT_SE_CNTL_STATUS:
199 case RADEON_EMIT_RE_MISC:
200 case RADEON_EMIT_PP_BORDER_COLOR_0:
201 case RADEON_EMIT_PP_BORDER_COLOR_1:
202 case RADEON_EMIT_PP_BORDER_COLOR_2:
203 case RADEON_EMIT_SE_ZBIAS_FACTOR:
204 case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
205 case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
206 case R200_EMIT_PP_TXCBLEND_0:
207 case R200_EMIT_PP_TXCBLEND_1:
208 case R200_EMIT_PP_TXCBLEND_2:
209 case R200_EMIT_PP_TXCBLEND_3:
210 case R200_EMIT_PP_TXCBLEND_4:
211 case R200_EMIT_PP_TXCBLEND_5:
212 case R200_EMIT_PP_TXCBLEND_6:
213 case R200_EMIT_PP_TXCBLEND_7:
214 case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
215 case R200_EMIT_TFACTOR_0:
216 case R200_EMIT_VTX_FMT_0:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217 case R200_EMIT_MATRIX_SELECT_0:
218 case R200_EMIT_TEX_PROC_CTL_2:
219 case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
220 case R200_EMIT_PP_TXFILTER_0:
221 case R200_EMIT_PP_TXFILTER_1:
222 case R200_EMIT_PP_TXFILTER_2:
223 case R200_EMIT_PP_TXFILTER_3:
224 case R200_EMIT_PP_TXFILTER_4:
225 case R200_EMIT_PP_TXFILTER_5:
226 case R200_EMIT_VTE_CNTL:
227 case R200_EMIT_OUTPUT_VTX_COMP_SEL:
228 case R200_EMIT_PP_TAM_DEBUG3:
229 case R200_EMIT_PP_CNTL_X:
230 case R200_EMIT_RB3D_DEPTHXY_OFFSET:
231 case R200_EMIT_RE_AUX_SCISSOR_CNTL:
232 case R200_EMIT_RE_SCISSOR_TL_0:
233 case R200_EMIT_RE_SCISSOR_TL_1:
234 case R200_EMIT_RE_SCISSOR_TL_2:
235 case R200_EMIT_SE_VAP_CNTL_STATUS:
236 case R200_EMIT_SE_VTX_STATE_CNTL:
237 case R200_EMIT_RE_POINTSIZE:
238 case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
239 case R200_EMIT_PP_CUBIC_FACES_0:
240 case R200_EMIT_PP_CUBIC_FACES_1:
241 case R200_EMIT_PP_CUBIC_FACES_2:
242 case R200_EMIT_PP_CUBIC_FACES_3:
243 case R200_EMIT_PP_CUBIC_FACES_4:
244 case R200_EMIT_PP_CUBIC_FACES_5:
245 case RADEON_EMIT_PP_TEX_SIZE_0:
246 case RADEON_EMIT_PP_TEX_SIZE_1:
247 case RADEON_EMIT_PP_TEX_SIZE_2:
248 case R200_EMIT_RB3D_BLENDCOLOR:
249 case R200_EMIT_TCL_POINT_SPRITE_CNTL:
250 case RADEON_EMIT_PP_CUBIC_FACES_0:
251 case RADEON_EMIT_PP_CUBIC_FACES_1:
252 case RADEON_EMIT_PP_CUBIC_FACES_2:
253 case R200_EMIT_PP_TRI_PERF_CNTL:
Dave Airlie9d176012005-09-11 19:55:53 +1000254 case R200_EMIT_PP_AFS_0:
255 case R200_EMIT_PP_AFS_1:
256 case R200_EMIT_ATF_TFACTOR:
257 case R200_EMIT_PP_TXCTLALL_0:
258 case R200_EMIT_PP_TXCTLALL_1:
259 case R200_EMIT_PP_TXCTLALL_2:
260 case R200_EMIT_PP_TXCTLALL_3:
261 case R200_EMIT_PP_TXCTLALL_4:
262 case R200_EMIT_PP_TXCTLALL_5:
Dave Airlied6fece02006-06-24 17:04:07 +1000263 case R200_EMIT_VAP_PVS_CNTL:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 /* These packets don't contain memory offsets */
265 break;
266
267 default:
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000268 DRM_ERROR("Unknown state packet ID %d\n", id);
Eric Anholt20caafa2007-08-25 19:22:43 +1000269 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 }
271
272 return 0;
273}
274
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000275static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
276 dev_priv,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000277 struct drm_file *file_priv,
Dave Airlied985c102006-01-02 21:32:48 +1100278 drm_radeon_kcmd_buffer_t *
279 cmdbuf,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000280 unsigned int *cmdsz)
281{
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200282 u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000283 u32 offset, narrays;
284 int count, i, k;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200286 count = ((*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16);
287 *cmdsz = 2 + count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200289 if ((*cmd & 0xc0000000) != RADEON_CP_PACKET3) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000290 DRM_ERROR("Not a type 3 packet\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000291 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292 }
293
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200294 if (4 * *cmdsz > drm_buffer_unprocessed(cmdbuf->buffer)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000295 DRM_ERROR("Packet size larger than size of data provided\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000296 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297 }
298
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200299 switch (*cmd & 0xff00) {
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000300 /* XXX Are there old drivers needing other packets? */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000302 case RADEON_3D_DRAW_IMMD:
303 case RADEON_3D_DRAW_VBUF:
304 case RADEON_3D_DRAW_INDX:
305 case RADEON_WAIT_FOR_IDLE:
306 case RADEON_CP_NOP:
307 case RADEON_3D_CLEAR_ZMASK:
308/* case RADEON_CP_NEXT_CHAR:
309 case RADEON_CP_PLY_NEXTSCAN:
310 case RADEON_CP_SET_SCISSORS: */ /* probably safe but will never need them? */
311 /* these packets are safe */
312 break;
313
314 case RADEON_CP_3D_DRAW_IMMD_2:
315 case RADEON_CP_3D_DRAW_VBUF_2:
316 case RADEON_CP_3D_DRAW_INDX_2:
317 case RADEON_3D_CLEAR_HIZ:
318 /* safe but r200 only */
319 if (dev_priv->microcode_version != UCODE_R200) {
320 DRM_ERROR("Invalid 3d packet for r100-class chip\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000321 return -EINVAL;
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000322 }
323 break;
324
325 case RADEON_3D_LOAD_VBPNTR:
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000326
327 if (count > 18) { /* 12 arrays max */
328 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
329 count);
Eric Anholt20caafa2007-08-25 19:22:43 +1000330 return -EINVAL;
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000331 }
332
333 /* carefully check packet contents */
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200334 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
335
336 narrays = *cmd & ~0xc000;
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000337 k = 0;
338 i = 2;
339 while ((k < narrays) && (i < (count + 2))) {
340 i++; /* skip attribute field */
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200341 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
Eric Anholt6c340ea2007-08-25 20:23:09 +1000342 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200343 cmd)) {
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000344 DRM_ERROR
345 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
346 k, i);
Eric Anholt20caafa2007-08-25 19:22:43 +1000347 return -EINVAL;
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000348 }
349 k++;
350 i++;
351 if (k == narrays)
352 break;
353 /* have one more to process, they come in pairs */
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200354 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
355
Eric Anholt6c340ea2007-08-25 20:23:09 +1000356 if (radeon_check_and_fixup_offset(dev_priv,
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200357 file_priv, cmd))
Eric Anholt6c340ea2007-08-25 20:23:09 +1000358 {
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000359 DRM_ERROR
360 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
361 k, i);
Eric Anholt20caafa2007-08-25 19:22:43 +1000362 return -EINVAL;
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000363 }
364 k++;
365 i++;
366 }
367 /* do the counts match what we expect ? */
368 if ((k != narrays) || (i != (count + 2))) {
369 DRM_ERROR
370 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
371 k, i, narrays, count + 1);
Eric Anholt20caafa2007-08-25 19:22:43 +1000372 return -EINVAL;
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000373 }
374 break;
375
376 case RADEON_3D_RNDR_GEN_INDX_PRIM:
377 if (dev_priv->microcode_version != UCODE_R100) {
378 DRM_ERROR("Invalid 3d packet for r200-class chip\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000379 return -EINVAL;
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000380 }
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200381
382 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
383 if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) {
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000384 DRM_ERROR("Invalid rndr_gen_indx offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000385 return -EINVAL;
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000386 }
387 break;
388
389 case RADEON_CP_INDX_BUFFER:
390 if (dev_priv->microcode_version != UCODE_R200) {
391 DRM_ERROR("Invalid 3d packet for r100-class chip\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000392 return -EINVAL;
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000393 }
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200394
395 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
396 if ((*cmd & 0x8000ffff) != 0x80000810) {
397 DRM_ERROR("Invalid indx_buffer reg address %08X\n", *cmd);
Eric Anholt20caafa2007-08-25 19:22:43 +1000398 return -EINVAL;
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000399 }
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200400 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
401 if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) {
402 DRM_ERROR("Invalid indx_buffer offset is %08X\n", *cmd);
Eric Anholt20caafa2007-08-25 19:22:43 +1000403 return -EINVAL;
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000404 }
405 break;
406
407 case RADEON_CNTL_HOSTDATA_BLT:
408 case RADEON_CNTL_PAINT_MULTI:
409 case RADEON_CNTL_BITBLT_MULTI:
410 /* MSB of opcode: next DWORD GUI_CNTL */
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200411 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
412 if (*cmd & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000413 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200414 u32 *cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
415 offset = *cmd2 << 10;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000416 if (radeon_check_and_fixup_offset
Eric Anholt6c340ea2007-08-25 20:23:09 +1000417 (dev_priv, file_priv, &offset)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000418 DRM_ERROR("Invalid first packet offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000419 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 }
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200421 *cmd2 = (*cmd2 & 0xffc00000) | offset >> 10;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422 }
423
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200424 if ((*cmd & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
425 (*cmd & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
426 u32 *cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3);
Jean Delvarec9ff04c2010-05-11 14:01:45 +1000427 offset = *cmd3 << 10;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000428 if (radeon_check_and_fixup_offset
Eric Anholt6c340ea2007-08-25 20:23:09 +1000429 (dev_priv, file_priv, &offset)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000430 DRM_ERROR("Invalid second packet offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000431 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432 }
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200433 *cmd3 = (*cmd3 & 0xffc00000) | offset >> 10;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434 }
Roland Scheideggera1aa28972006-10-24 21:45:00 +1000435 break;
436
437 default:
Pauli Nieminenb4fe9452010-02-01 19:11:16 +0200438 DRM_ERROR("Invalid packet type %x\n", *cmd & 0xff00);
Eric Anholt20caafa2007-08-25 19:22:43 +1000439 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440 }
441
442 return 0;
443}
444
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445/* ================================================================
446 * CP hardware state programming functions
447 */
448
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000449static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
Dave Airliec60ce622007-07-11 15:27:12 +1000450 struct drm_clip_rect * box)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451{
452 RING_LOCALS;
453
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000454 DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n",
455 box->x1, box->y1, box->x2, box->y2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000457 BEGIN_RING(4);
458 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
459 OUT_RING((box->y1 << 16) | box->x1);
460 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
461 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462 ADVANCE_RING();
463}
464
465/* Emit 1.1 state
466 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000467static int radeon_emit_state(drm_radeon_private_t * dev_priv,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000468 struct drm_file *file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000469 drm_radeon_context_regs_t * ctx,
470 drm_radeon_texture_regs_t * tex,
471 unsigned int dirty)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472{
473 RING_LOCALS;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000474 DRM_DEBUG("dirty=0x%08x\n", dirty);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000476 if (dirty & RADEON_UPLOAD_CONTEXT) {
Eric Anholt6c340ea2007-08-25 20:23:09 +1000477 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000478 &ctx->rb3d_depthoffset)) {
479 DRM_ERROR("Invalid depth buffer offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000480 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481 }
482
Eric Anholt6c340ea2007-08-25 20:23:09 +1000483 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000484 &ctx->rb3d_coloroffset)) {
485 DRM_ERROR("Invalid depth buffer offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000486 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487 }
488
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000489 BEGIN_RING(14);
490 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
491 OUT_RING(ctx->pp_misc);
492 OUT_RING(ctx->pp_fog_color);
493 OUT_RING(ctx->re_solid_color);
494 OUT_RING(ctx->rb3d_blendcntl);
495 OUT_RING(ctx->rb3d_depthoffset);
496 OUT_RING(ctx->rb3d_depthpitch);
497 OUT_RING(ctx->rb3d_zstencilcntl);
498 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
499 OUT_RING(ctx->pp_cntl);
500 OUT_RING(ctx->rb3d_cntl);
501 OUT_RING(ctx->rb3d_coloroffset);
502 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
503 OUT_RING(ctx->rb3d_colorpitch);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504 ADVANCE_RING();
505 }
506
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000507 if (dirty & RADEON_UPLOAD_VERTFMT) {
508 BEGIN_RING(2);
509 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
510 OUT_RING(ctx->se_coord_fmt);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511 ADVANCE_RING();
512 }
513
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000514 if (dirty & RADEON_UPLOAD_LINE) {
515 BEGIN_RING(5);
516 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
517 OUT_RING(ctx->re_line_pattern);
518 OUT_RING(ctx->re_line_state);
519 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
520 OUT_RING(ctx->se_line_width);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521 ADVANCE_RING();
522 }
523
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000524 if (dirty & RADEON_UPLOAD_BUMPMAP) {
525 BEGIN_RING(5);
526 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
527 OUT_RING(ctx->pp_lum_matrix);
528 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
529 OUT_RING(ctx->pp_rot_matrix_0);
530 OUT_RING(ctx->pp_rot_matrix_1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531 ADVANCE_RING();
532 }
533
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000534 if (dirty & RADEON_UPLOAD_MASKS) {
535 BEGIN_RING(4);
536 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
537 OUT_RING(ctx->rb3d_stencilrefmask);
538 OUT_RING(ctx->rb3d_ropcntl);
539 OUT_RING(ctx->rb3d_planemask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540 ADVANCE_RING();
541 }
542
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000543 if (dirty & RADEON_UPLOAD_VIEWPORT) {
544 BEGIN_RING(7);
545 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
546 OUT_RING(ctx->se_vport_xscale);
547 OUT_RING(ctx->se_vport_xoffset);
548 OUT_RING(ctx->se_vport_yscale);
549 OUT_RING(ctx->se_vport_yoffset);
550 OUT_RING(ctx->se_vport_zscale);
551 OUT_RING(ctx->se_vport_zoffset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552 ADVANCE_RING();
553 }
554
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000555 if (dirty & RADEON_UPLOAD_SETUP) {
556 BEGIN_RING(4);
557 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
558 OUT_RING(ctx->se_cntl);
559 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
560 OUT_RING(ctx->se_cntl_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561 ADVANCE_RING();
562 }
563
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000564 if (dirty & RADEON_UPLOAD_MISC) {
565 BEGIN_RING(2);
566 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
567 OUT_RING(ctx->re_misc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568 ADVANCE_RING();
569 }
570
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000571 if (dirty & RADEON_UPLOAD_TEX0) {
Eric Anholt6c340ea2007-08-25 20:23:09 +1000572 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000573 &tex[0].pp_txoffset)) {
574 DRM_ERROR("Invalid texture offset for unit 0\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000575 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576 }
577
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000578 BEGIN_RING(9);
579 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
580 OUT_RING(tex[0].pp_txfilter);
581 OUT_RING(tex[0].pp_txformat);
582 OUT_RING(tex[0].pp_txoffset);
583 OUT_RING(tex[0].pp_txcblend);
584 OUT_RING(tex[0].pp_txablend);
585 OUT_RING(tex[0].pp_tfactor);
586 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
587 OUT_RING(tex[0].pp_border_color);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588 ADVANCE_RING();
589 }
590
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000591 if (dirty & RADEON_UPLOAD_TEX1) {
Eric Anholt6c340ea2007-08-25 20:23:09 +1000592 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000593 &tex[1].pp_txoffset)) {
594 DRM_ERROR("Invalid texture offset for unit 1\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000595 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596 }
597
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000598 BEGIN_RING(9);
599 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
600 OUT_RING(tex[1].pp_txfilter);
601 OUT_RING(tex[1].pp_txformat);
602 OUT_RING(tex[1].pp_txoffset);
603 OUT_RING(tex[1].pp_txcblend);
604 OUT_RING(tex[1].pp_txablend);
605 OUT_RING(tex[1].pp_tfactor);
606 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
607 OUT_RING(tex[1].pp_border_color);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608 ADVANCE_RING();
609 }
610
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000611 if (dirty & RADEON_UPLOAD_TEX2) {
Eric Anholt6c340ea2007-08-25 20:23:09 +1000612 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000613 &tex[2].pp_txoffset)) {
614 DRM_ERROR("Invalid texture offset for unit 2\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000615 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616 }
617
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000618 BEGIN_RING(9);
619 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
620 OUT_RING(tex[2].pp_txfilter);
621 OUT_RING(tex[2].pp_txformat);
622 OUT_RING(tex[2].pp_txoffset);
623 OUT_RING(tex[2].pp_txcblend);
624 OUT_RING(tex[2].pp_txablend);
625 OUT_RING(tex[2].pp_tfactor);
626 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
627 OUT_RING(tex[2].pp_border_color);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628 ADVANCE_RING();
629 }
630
631 return 0;
632}
633
634/* Emit 1.2 state
635 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000636static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000637 struct drm_file *file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000638 drm_radeon_state_t * state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639{
640 RING_LOCALS;
641
642 if (state->dirty & RADEON_UPLOAD_ZBIAS) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000643 BEGIN_RING(3);
644 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
645 OUT_RING(state->context2.se_zbias_factor);
646 OUT_RING(state->context2.se_zbias_constant);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647 ADVANCE_RING();
648 }
649
Eric Anholt6c340ea2007-08-25 20:23:09 +1000650 return radeon_emit_state(dev_priv, file_priv, &state->context,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000651 state->tex, state->dirty);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652}
653
654/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
655 * 1.3 cmdbuffers allow all previous state to be updated as well as
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000656 * the tcl scalar and vector areas.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000658static struct {
659 int start;
660 int len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661 const char *name;
662} packet[RADEON_MAX_STATE_PACKETS] = {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000663 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
664 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
665 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
666 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
667 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
668 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
669 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
670 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
671 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
672 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
673 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
674 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
675 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
676 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
677 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
678 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
679 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
680 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
681 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
682 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
683 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
684 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
685 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
686 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
687 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
688 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
689 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
690 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
691 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
692 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
693 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
694 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
695 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
696 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
697 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
698 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
699 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
700 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
701 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
702 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
703 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
704 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
705 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
706 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
707 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
708 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
709 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
710 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
711 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
712 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
Dave Airlied985c102006-01-02 21:32:48 +1100713 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
714 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000715 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
716 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
717 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
718 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
719 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
720 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
721 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
722 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
723 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
724 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
725 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
726 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
727 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
Dave Airlied985c102006-01-02 21:32:48 +1100728 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000729 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
730 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
731 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
732 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
733 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
734 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
735 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
736 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
737 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
738 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
739 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
740 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
741 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
742 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
743 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
744 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
745 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
746 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
747 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
748 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
749 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
750 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
Dave Airlied985c102006-01-02 21:32:48 +1100751 {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000752 {R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
753 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
754 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
755 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
756 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
757 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
758 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
759 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
Dave Airlied6fece02006-06-24 17:04:07 +1000760 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761};
762
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763/* ================================================================
764 * Performance monitoring functions
765 */
766
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000767static void radeon_clear_box(drm_radeon_private_t * dev_priv,
Dave Airlie7c1c2872008-11-28 14:22:24 +1000768 struct drm_radeon_master_private *master_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000769 int x, int y, int w, int h, int r, int g, int b)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770{
771 u32 color;
772 RING_LOCALS;
773
Dave Airlie7c1c2872008-11-28 14:22:24 +1000774 x += master_priv->sarea_priv->boxes[0].x1;
775 y += master_priv->sarea_priv->boxes[0].y1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000777 switch (dev_priv->color_fmt) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778 case RADEON_COLOR_FORMAT_RGB565:
779 color = (((r & 0xf8) << 8) |
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000780 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781 break;
782 case RADEON_COLOR_FORMAT_ARGB8888:
783 default:
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000784 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785 break;
786 }
787
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000788 BEGIN_RING(4);
789 RADEON_WAIT_UNTIL_3D_IDLE();
790 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
791 OUT_RING(0xffffffff);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 ADVANCE_RING();
793
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000794 BEGIN_RING(6);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000796 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
797 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
798 RADEON_GMC_BRUSH_SOLID_COLOR |
799 (dev_priv->color_fmt << 8) |
800 RADEON_GMC_SRC_DATATYPE_COLOR |
801 RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802
Dave Airlie7c1c2872008-11-28 14:22:24 +1000803 if (master_priv->sarea_priv->pfCurrentPage == 1) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000804 OUT_RING(dev_priv->front_pitch_offset);
805 } else {
806 OUT_RING(dev_priv->back_pitch_offset);
807 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000809 OUT_RING(color);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000811 OUT_RING((x << 16) | y);
812 OUT_RING((w << 16) | h);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813
814 ADVANCE_RING();
815}
816
Dave Airlie7c1c2872008-11-28 14:22:24 +1000817static void radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv, struct drm_radeon_master_private *master_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818{
819 /* Collapse various things into a wait flag -- trying to
820 * guess if userspase slept -- better just to have them tell us.
821 */
822 if (dev_priv->stats.last_frame_reads > 1 ||
823 dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
824 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
825 }
826
827 if (dev_priv->stats.freelist_loops) {
828 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
829 }
830
831 /* Purple box for page flipping
832 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000833 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
Dave Airlie7c1c2872008-11-28 14:22:24 +1000834 radeon_clear_box(dev_priv, master_priv, 4, 4, 8, 8, 255, 0, 255);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835
836 /* Red box if we have to wait for idle at any point
837 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000838 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
Dave Airlie7c1c2872008-11-28 14:22:24 +1000839 radeon_clear_box(dev_priv, master_priv, 16, 4, 8, 8, 255, 0, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840
841 /* Blue box: lost context?
842 */
843
844 /* Yellow box for texture swaps
845 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000846 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
Dave Airlie7c1c2872008-11-28 14:22:24 +1000847 radeon_clear_box(dev_priv, master_priv, 40, 4, 8, 8, 255, 255, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848
849 /* Green box if hardware never idles (as far as we can tell)
850 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000851 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
Dave Airlie7c1c2872008-11-28 14:22:24 +1000852 radeon_clear_box(dev_priv, master_priv, 64, 4, 8, 8, 0, 255, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000854 /* Draw bars indicating number of buffers allocated
Linus Torvalds1da177e2005-04-16 15:20:36 -0700855 * (not a great measure, easily confused)
856 */
857 if (dev_priv->stats.requested_bufs) {
858 if (dev_priv->stats.requested_bufs > 100)
859 dev_priv->stats.requested_bufs = 100;
860
Dave Airlie7c1c2872008-11-28 14:22:24 +1000861 radeon_clear_box(dev_priv, master_priv, 4, 16,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000862 dev_priv->stats.requested_bufs, 4,
863 196, 128, 128);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864 }
865
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000866 memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867
868}
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000869
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870/* ================================================================
871 * CP command dispatch functions
872 */
873
Dave Airlie84b1fd12007-07-11 15:53:27 +1000874static void radeon_cp_dispatch_clear(struct drm_device * dev,
Dave Airlie7c1c2872008-11-28 14:22:24 +1000875 struct drm_master *master,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000876 drm_radeon_clear_t * clear,
877 drm_radeon_clear_rect_t * depth_boxes)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878{
879 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000880 struct drm_radeon_master_private *master_priv = master->driver_priv;
881 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700882 drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
883 int nbox = sarea_priv->nbox;
Dave Airliec60ce622007-07-11 15:27:12 +1000884 struct drm_clip_rect *pbox = sarea_priv->boxes;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700885 unsigned int flags = clear->flags;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000886 u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700887 int i;
888 RING_LOCALS;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000889 DRM_DEBUG("flags = 0x%x\n", flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890
891 dev_priv->stats.clears++;
892
Dave Airlie7c1c2872008-11-28 14:22:24 +1000893 if (sarea_priv->pfCurrentPage == 1) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894 unsigned int tmp = flags;
895
896 flags &= ~(RADEON_FRONT | RADEON_BACK);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000897 if (tmp & RADEON_FRONT)
898 flags |= RADEON_BACK;
899 if (tmp & RADEON_BACK)
900 flags |= RADEON_FRONT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 }
Dave Airlie566d84d2010-02-24 17:17:13 +1000902 if (flags & (RADEON_DEPTH|RADEON_STENCIL)) {
Dave Airliecf22f202010-05-29 06:50:37 +1000903 if (!dev_priv->have_z_offset) {
Dave Airlie566d84d2010-02-24 17:17:13 +1000904 printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n");
Dave Airliecf22f202010-05-29 06:50:37 +1000905 flags &= ~(RADEON_DEPTH | RADEON_STENCIL);
906 }
Dave Airlie566d84d2010-02-24 17:17:13 +1000907 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700908
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000909 if (flags & (RADEON_FRONT | RADEON_BACK)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000911 BEGIN_RING(4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912
913 /* Ensure the 3D stream is idle before doing a
914 * 2D fill to clear the front or back buffer.
915 */
916 RADEON_WAIT_UNTIL_3D_IDLE();
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000917
918 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
919 OUT_RING(clear->color_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920
921 ADVANCE_RING();
922
923 /* Make sure we restore the 3D state next time.
924 */
Dave Airlie7c1c2872008-11-28 14:22:24 +1000925 sarea_priv->ctx_owner = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700926
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000927 for (i = 0; i < nbox; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700928 int x = pbox[i].x1;
929 int y = pbox[i].y1;
930 int w = pbox[i].x2 - x;
931 int h = pbox[i].y2 - y;
932
Márton Németh3e684ea2008-01-24 15:58:57 +1000933 DRM_DEBUG("%d,%d-%d,%d flags 0x%x\n",
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000934 x, y, w, h, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700935
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000936 if (flags & RADEON_FRONT) {
937 BEGIN_RING(6);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000939 OUT_RING(CP_PACKET3
940 (RADEON_CNTL_PAINT_MULTI, 4));
941 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
942 RADEON_GMC_BRUSH_SOLID_COLOR |
943 (dev_priv->
944 color_fmt << 8) |
945 RADEON_GMC_SRC_DATATYPE_COLOR |
946 RADEON_ROP3_P |
947 RADEON_GMC_CLR_CMP_CNTL_DIS);
948
949 OUT_RING(dev_priv->front_pitch_offset);
950 OUT_RING(clear->clear_color);
951
952 OUT_RING((x << 16) | y);
953 OUT_RING((w << 16) | h);
954
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955 ADVANCE_RING();
956 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700957
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000958 if (flags & RADEON_BACK) {
959 BEGIN_RING(6);
960
961 OUT_RING(CP_PACKET3
962 (RADEON_CNTL_PAINT_MULTI, 4));
963 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
964 RADEON_GMC_BRUSH_SOLID_COLOR |
965 (dev_priv->
966 color_fmt << 8) |
967 RADEON_GMC_SRC_DATATYPE_COLOR |
968 RADEON_ROP3_P |
969 RADEON_GMC_CLR_CMP_CNTL_DIS);
970
971 OUT_RING(dev_priv->back_pitch_offset);
972 OUT_RING(clear->clear_color);
973
974 OUT_RING((x << 16) | y);
975 OUT_RING((w << 16) | h);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976
977 ADVANCE_RING();
978 }
979 }
980 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000981
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982 /* hyper z clear */
983 /* no docs available, based on reverse engeneering by Stephane Marchesin */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000984 if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
985 && (flags & RADEON_CLEAR_FASTZ)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986
987 int i;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000988 int depthpixperline =
989 dev_priv->depth_fmt ==
990 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
991 2) : (dev_priv->
992 depth_pitch / 4);
993
Linus Torvalds1da177e2005-04-16 15:20:36 -0700994 u32 clearmask;
995
996 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000997 ((clear->depth_mask & 0xff) << 24);
998
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999 /* Make sure we restore the 3D state next time.
1000 * we haven't touched any "normal" state - still need this?
1001 */
Dave Airlie7c1c2872008-11-28 14:22:24 +10001002 sarea_priv->ctx_owner = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003
Dave Airlie54a56ac2006-09-22 04:25:09 +10001004 if ((dev_priv->flags & RADEON_HAS_HIERZ)
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001005 && (flags & RADEON_USE_HIERZ)) {
1006 /* FIXME : reverse engineer that for Rx00 cards */
1007 /* FIXME : the mask supposedly contains low-res z values. So can't set
1008 just to the max (0xff? or actually 0x3fff?), need to take z clear
1009 value into account? */
1010 /* pattern seems to work for r100, though get slight
1011 rendering errors with glxgears. If hierz is not enabled for r100,
1012 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
1013 other ones are ignored, and the same clear mask can be used. That's
1014 very different behaviour than R200 which needs different clear mask
1015 and different number of tiles to clear if hierz is enabled or not !?!
1016 */
1017 clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
1018 } else {
1019 /* clear mask : chooses the clearing pattern.
1020 rv250: could be used to clear only parts of macrotiles
1021 (but that would get really complicated...)?
1022 bit 0 and 1 (either or both of them ?!?!) are used to
1023 not clear tile (or maybe one of the bits indicates if the tile is
1024 compressed or not), bit 2 and 3 to not clear tile 1,...,.
1025 Pattern is as follows:
1026 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
1027 bits -------------------------------------------------
1028 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
1029 rv100: clearmask covers 2x8 4x1 tiles, but one clear still
1030 covers 256 pixels ?!?
1031 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001032 clearmask = 0x0;
1033 }
1034
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001035 BEGIN_RING(8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036 RADEON_WAIT_UNTIL_2D_IDLE();
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001037 OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
1038 tempRB3D_DEPTHCLEARVALUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001039 /* what offset is this exactly ? */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001040 OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041 /* need ctlstat, otherwise get some strange black flickering */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001042 OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
1043 RADEON_RB3D_ZC_FLUSH_ALL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044 ADVANCE_RING();
1045
1046 for (i = 0; i < nbox; i++) {
1047 int tileoffset, nrtilesx, nrtilesy, j;
1048 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
Dave Airlie54a56ac2006-09-22 04:25:09 +10001049 if ((dev_priv->flags & RADEON_HAS_HIERZ)
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001050 && !(dev_priv->microcode_version == UCODE_R200)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051 /* FIXME : figure this out for r200 (when hierz is enabled). Or
1052 maybe r200 actually doesn't need to put the low-res z value into
1053 the tile cache like r100, but just needs to clear the hi-level z-buffer?
1054 Works for R100, both with hierz and without.
1055 R100 seems to operate on 2x1 8x8 tiles, but...
1056 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
1057 problematic with resolutions which are not 64 pix aligned? */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001058 tileoffset =
1059 ((pbox[i].y1 >> 3) * depthpixperline +
1060 pbox[i].x1) >> 6;
1061 nrtilesx =
1062 ((pbox[i].x2 & ~63) -
1063 (pbox[i].x1 & ~63)) >> 4;
1064 nrtilesy =
1065 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066 for (j = 0; j <= nrtilesy; j++) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001067 BEGIN_RING(4);
1068 OUT_RING(CP_PACKET3
1069 (RADEON_3D_CLEAR_ZMASK, 2));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070 /* first tile */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001071 OUT_RING(tileoffset * 8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072 /* the number of tiles to clear */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001073 OUT_RING(nrtilesx + 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074 /* clear mask : chooses the clearing pattern. */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001075 OUT_RING(clearmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076 ADVANCE_RING();
1077 tileoffset += depthpixperline >> 6;
1078 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001079 } else if (dev_priv->microcode_version == UCODE_R200) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080 /* works for rv250. */
1081 /* find first macro tile (8x2 4x4 z-pixels on rv250) */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001082 tileoffset =
1083 ((pbox[i].y1 >> 3) * depthpixperline +
1084 pbox[i].x1) >> 5;
1085 nrtilesx =
1086 (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
1087 nrtilesy =
1088 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089 for (j = 0; j <= nrtilesy; j++) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001090 BEGIN_RING(4);
1091 OUT_RING(CP_PACKET3
1092 (RADEON_3D_CLEAR_ZMASK, 2));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093 /* first tile */
1094 /* judging by the first tile offset needed, could possibly
1095 directly address/clear 4x4 tiles instead of 8x2 * 4x4
1096 macro tiles, though would still need clear mask for
Adam Buchbinderc41b20e2009-12-11 16:35:39 -05001097 right/bottom if truly 4x4 granularity is desired ? */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001098 OUT_RING(tileoffset * 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099 /* the number of tiles to clear */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001100 OUT_RING(nrtilesx + 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001101 /* clear mask : chooses the clearing pattern. */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001102 OUT_RING(clearmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103 ADVANCE_RING();
1104 tileoffset += depthpixperline >> 5;
1105 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001106 } else { /* rv 100 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107 /* rv100 might not need 64 pix alignment, who knows */
1108 /* offsets are, hmm, weird */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001109 tileoffset =
1110 ((pbox[i].y1 >> 4) * depthpixperline +
1111 pbox[i].x1) >> 6;
1112 nrtilesx =
1113 ((pbox[i].x2 & ~63) -
1114 (pbox[i].x1 & ~63)) >> 4;
1115 nrtilesy =
1116 (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117 for (j = 0; j <= nrtilesy; j++) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001118 BEGIN_RING(4);
1119 OUT_RING(CP_PACKET3
1120 (RADEON_3D_CLEAR_ZMASK, 2));
1121 OUT_RING(tileoffset * 128);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122 /* the number of tiles to clear */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001123 OUT_RING(nrtilesx + 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124 /* clear mask : chooses the clearing pattern. */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001125 OUT_RING(clearmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126 ADVANCE_RING();
1127 tileoffset += depthpixperline >> 6;
1128 }
1129 }
1130 }
1131
1132 /* TODO don't always clear all hi-level z tiles */
Dave Airlie54a56ac2006-09-22 04:25:09 +10001133 if ((dev_priv->flags & RADEON_HAS_HIERZ)
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001134 && (dev_priv->microcode_version == UCODE_R200)
1135 && (flags & RADEON_USE_HIERZ))
1136 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
1137 /* FIXME : the mask supposedly contains low-res z values. So can't set
1138 just to the max (0xff? or actually 0x3fff?), need to take z clear
1139 value into account? */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140 {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001141 BEGIN_RING(4);
1142 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
1143 OUT_RING(0x0); /* First tile */
1144 OUT_RING(0x3cc0);
1145 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 ADVANCE_RING();
1147 }
1148 }
1149
1150 /* We have to clear the depth and/or stencil buffers by
1151 * rendering a quad into just those buffers. Thus, we have to
1152 * make sure the 3D engine is configured correctly.
1153 */
Dave Airlied985c102006-01-02 21:32:48 +11001154 else if ((dev_priv->microcode_version == UCODE_R200) &&
1155 (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156
1157 int tempPP_CNTL;
1158 int tempRE_CNTL;
1159 int tempRB3D_CNTL;
1160 int tempRB3D_ZSTENCILCNTL;
1161 int tempRB3D_STENCILREFMASK;
1162 int tempRB3D_PLANEMASK;
1163 int tempSE_CNTL;
1164 int tempSE_VTE_CNTL;
1165 int tempSE_VTX_FMT_0;
1166 int tempSE_VTX_FMT_1;
1167 int tempSE_VAP_CNTL;
1168 int tempRE_AUX_SCISSOR_CNTL;
1169
1170 tempPP_CNTL = 0;
1171 tempRE_CNTL = 0;
1172
1173 tempRB3D_CNTL = depth_clear->rb3d_cntl;
1174
1175 tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1176 tempRB3D_STENCILREFMASK = 0x0;
1177
1178 tempSE_CNTL = depth_clear->se_cntl;
1179
Linus Torvalds1da177e2005-04-16 15:20:36 -07001180 /* Disable TCL */
1181
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001182 tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
1183 (0x9 <<
1184 SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001185
1186 tempRB3D_PLANEMASK = 0x0;
1187
1188 tempRE_AUX_SCISSOR_CNTL = 0x0;
1189
1190 tempSE_VTE_CNTL =
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001191 SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001192
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001193 /* Vertex format (X, Y, Z, W) */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001194 tempSE_VTX_FMT_0 =
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001195 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
1196 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197 tempSE_VTX_FMT_1 = 0x0;
1198
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001199 /*
1200 * Depth buffer specific enables
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201 */
1202 if (flags & RADEON_DEPTH) {
1203 /* Enable depth buffer */
1204 tempRB3D_CNTL |= RADEON_Z_ENABLE;
1205 } else {
1206 /* Disable depth buffer */
1207 tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
1208 }
1209
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001210 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211 * Stencil buffer specific enables
1212 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001213 if (flags & RADEON_STENCIL) {
1214 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
1215 tempRB3D_STENCILREFMASK = clear->depth_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216 } else {
1217 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
1218 tempRB3D_STENCILREFMASK = 0x00000000;
1219 }
1220
1221 if (flags & RADEON_USE_COMP_ZBUF) {
1222 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001223 RADEON_Z_DECOMPRESSION_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001224 }
1225 if (flags & RADEON_USE_HIERZ) {
1226 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1227 }
1228
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001229 BEGIN_RING(26);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001230 RADEON_WAIT_UNTIL_2D_IDLE();
1231
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001232 OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
1233 OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
1234 OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
1235 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1236 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
1237 tempRB3D_STENCILREFMASK);
1238 OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
1239 OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
1240 OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
1241 OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
1242 OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
1243 OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
1244 OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245 ADVANCE_RING();
1246
1247 /* Make sure we restore the 3D state next time.
1248 */
Dave Airlie7c1c2872008-11-28 14:22:24 +10001249 sarea_priv->ctx_owner = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001251 for (i = 0; i < nbox; i++) {
1252
1253 /* Funny that this should be required --
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254 * sets top-left?
1255 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001256 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001257
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001258 BEGIN_RING(14);
1259 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
1260 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1261 RADEON_PRIM_WALK_RING |
1262 (3 << RADEON_NUM_VERTICES_SHIFT)));
1263 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1264 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1265 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1266 OUT_RING(0x3f800000);
1267 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1268 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1269 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1270 OUT_RING(0x3f800000);
1271 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1272 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1273 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1274 OUT_RING(0x3f800000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001275 ADVANCE_RING();
1276 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001277 } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278
1279 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1280
1281 rb3d_cntl = depth_clear->rb3d_cntl;
1282
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001283 if (flags & RADEON_DEPTH) {
1284 rb3d_cntl |= RADEON_Z_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285 } else {
1286 rb3d_cntl &= ~RADEON_Z_ENABLE;
1287 }
1288
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001289 if (flags & RADEON_STENCIL) {
1290 rb3d_cntl |= RADEON_STENCIL_ENABLE;
1291 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001292 } else {
1293 rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
1294 rb3d_stencilrefmask = 0x00000000;
1295 }
1296
1297 if (flags & RADEON_USE_COMP_ZBUF) {
1298 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001299 RADEON_Z_DECOMPRESSION_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300 }
1301 if (flags & RADEON_USE_HIERZ) {
1302 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1303 }
1304
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001305 BEGIN_RING(13);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001306 RADEON_WAIT_UNTIL_2D_IDLE();
1307
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001308 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
1309 OUT_RING(0x00000000);
1310 OUT_RING(rb3d_cntl);
1311
1312 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1313 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
1314 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
1315 OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001316 ADVANCE_RING();
1317
1318 /* Make sure we restore the 3D state next time.
1319 */
Dave Airlie7c1c2872008-11-28 14:22:24 +10001320 sarea_priv->ctx_owner = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001321
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001322 for (i = 0; i < nbox; i++) {
1323
1324 /* Funny that this should be required --
Linus Torvalds1da177e2005-04-16 15:20:36 -07001325 * sets top-left?
1326 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001327 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001329 BEGIN_RING(15);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001331 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
1332 OUT_RING(RADEON_VTX_Z_PRESENT |
1333 RADEON_VTX_PKCOLOR_PRESENT);
1334 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1335 RADEON_PRIM_WALK_RING |
1336 RADEON_MAOS_ENABLE |
1337 RADEON_VTX_FMT_RADEON_MODE |
1338 (3 << RADEON_NUM_VERTICES_SHIFT)));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001339
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001340 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1341 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1342 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1343 OUT_RING(0x0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001344
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001345 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1346 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1347 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1348 OUT_RING(0x0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001349
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001350 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1351 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1352 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1353 OUT_RING(0x0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354
1355 ADVANCE_RING();
1356 }
1357 }
1358
1359 /* Increment the clear counter. The client-side 3D driver must
1360 * wait on this value before performing the clear ioctl. We
1361 * need this because the card's so damned fast...
1362 */
Dave Airlie7c1c2872008-11-28 14:22:24 +10001363 sarea_priv->last_clear++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001364
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001365 BEGIN_RING(4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001366
Dave Airlie7c1c2872008-11-28 14:22:24 +10001367 RADEON_CLEAR_AGE(sarea_priv->last_clear);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368 RADEON_WAIT_UNTIL_IDLE();
1369
1370 ADVANCE_RING();
1371}
1372
Dave Airlie7c1c2872008-11-28 14:22:24 +10001373static void radeon_cp_dispatch_swap(struct drm_device *dev, struct drm_master *master)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374{
1375 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10001376 struct drm_radeon_master_private *master_priv = master->driver_priv;
1377 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001378 int nbox = sarea_priv->nbox;
Dave Airliec60ce622007-07-11 15:27:12 +10001379 struct drm_clip_rect *pbox = sarea_priv->boxes;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380 int i;
1381 RING_LOCALS;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001382 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001383
1384 /* Do some trivial performance monitoring...
1385 */
1386 if (dev_priv->do_boxes)
Dave Airlie7c1c2872008-11-28 14:22:24 +10001387 radeon_cp_performance_boxes(dev_priv, master_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388
1389 /* Wait for the 3D stream to idle before dispatching the bitblt.
1390 * This will prevent data corruption between the two streams.
1391 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001392 BEGIN_RING(2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001393
1394 RADEON_WAIT_UNTIL_3D_IDLE();
1395
1396 ADVANCE_RING();
1397
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001398 for (i = 0; i < nbox; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399 int x = pbox[i].x1;
1400 int y = pbox[i].y1;
1401 int w = pbox[i].x2 - x;
1402 int h = pbox[i].y2 - y;
1403
Márton Németh3e684ea2008-01-24 15:58:57 +10001404 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001405
Michel Daenzer3e14a282006-09-22 04:26:35 +10001406 BEGIN_RING(9);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407
Michel Daenzer3e14a282006-09-22 04:26:35 +10001408 OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0));
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001409 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1410 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1411 RADEON_GMC_BRUSH_NONE |
1412 (dev_priv->color_fmt << 8) |
1413 RADEON_GMC_SRC_DATATYPE_COLOR |
1414 RADEON_ROP3_S |
1415 RADEON_DP_SRC_SOURCE_MEMORY |
1416 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1417
Linus Torvalds1da177e2005-04-16 15:20:36 -07001418 /* Make this work even if front & back are flipped:
1419 */
Michel Daenzer3e14a282006-09-22 04:26:35 +10001420 OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
Dave Airlie7c1c2872008-11-28 14:22:24 +10001421 if (sarea_priv->pfCurrentPage == 0) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001422 OUT_RING(dev_priv->back_pitch_offset);
1423 OUT_RING(dev_priv->front_pitch_offset);
1424 } else {
1425 OUT_RING(dev_priv->front_pitch_offset);
1426 OUT_RING(dev_priv->back_pitch_offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427 }
1428
Michel Daenzer3e14a282006-09-22 04:26:35 +10001429 OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2));
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001430 OUT_RING((x << 16) | y);
1431 OUT_RING((x << 16) | y);
1432 OUT_RING((w << 16) | h);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433
1434 ADVANCE_RING();
1435 }
1436
1437 /* Increment the frame counter. The client-side 3D driver must
1438 * throttle the framerate by waiting for this value before
1439 * performing the swapbuffer ioctl.
1440 */
Dave Airlie7c1c2872008-11-28 14:22:24 +10001441 sarea_priv->last_frame++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001442
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001443 BEGIN_RING(4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001444
Dave Airlie7c1c2872008-11-28 14:22:24 +10001445 RADEON_FRAME_AGE(sarea_priv->last_frame);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001446 RADEON_WAIT_UNTIL_2D_IDLE();
1447
1448 ADVANCE_RING();
1449}
1450
Dave Airlie7c1c2872008-11-28 14:22:24 +10001451void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452{
1453 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10001454 struct drm_radeon_master_private *master_priv = master->driver_priv;
1455 struct drm_sarea *sarea = (struct drm_sarea *)master_priv->sarea->handle;
1456 int offset = (master_priv->sarea_priv->pfCurrentPage == 1)
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001457 ? dev_priv->front_offset : dev_priv->back_offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001458 RING_LOCALS;
Márton Németh3e684ea2008-01-24 15:58:57 +10001459 DRM_DEBUG("pfCurrentPage=%d\n",
Dave Airlie7c1c2872008-11-28 14:22:24 +10001460 master_priv->sarea_priv->pfCurrentPage);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461
1462 /* Do some trivial performance monitoring...
1463 */
1464 if (dev_priv->do_boxes) {
1465 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
Dave Airlie7c1c2872008-11-28 14:22:24 +10001466 radeon_cp_performance_boxes(dev_priv, master_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001467 }
1468
1469 /* Update the frame offsets for both CRTCs
1470 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001471 BEGIN_RING(6);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001472
1473 RADEON_WAIT_UNTIL_3D_IDLE();
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001474 OUT_RING_REG(RADEON_CRTC_OFFSET,
1475 ((sarea->frame.y * dev_priv->front_pitch +
1476 sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
1477 + offset);
Dave Airlie7c1c2872008-11-28 14:22:24 +10001478 OUT_RING_REG(RADEON_CRTC2_OFFSET, master_priv->sarea_priv->crtc2_base
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001479 + offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480
1481 ADVANCE_RING();
1482
1483 /* Increment the frame counter. The client-side 3D driver must
1484 * throttle the framerate by waiting for this value before
1485 * performing the swapbuffer ioctl.
1486 */
Dave Airlie7c1c2872008-11-28 14:22:24 +10001487 master_priv->sarea_priv->last_frame++;
1488 master_priv->sarea_priv->pfCurrentPage =
1489 1 - master_priv->sarea_priv->pfCurrentPage;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001490
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001491 BEGIN_RING(2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492
Dave Airlie7c1c2872008-11-28 14:22:24 +10001493 RADEON_FRAME_AGE(master_priv->sarea_priv->last_frame);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494
1495 ADVANCE_RING();
1496}
1497
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001498static int bad_prim_vertex_nr(int primitive, int nr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001499{
1500 switch (primitive & RADEON_PRIM_TYPE_MASK) {
1501 case RADEON_PRIM_TYPE_NONE:
1502 case RADEON_PRIM_TYPE_POINT:
1503 return nr < 1;
1504 case RADEON_PRIM_TYPE_LINE:
1505 return (nr & 1) || nr == 0;
1506 case RADEON_PRIM_TYPE_LINE_STRIP:
1507 return nr < 2;
1508 case RADEON_PRIM_TYPE_TRI_LIST:
1509 case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
1510 case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
1511 case RADEON_PRIM_TYPE_RECT_LIST:
1512 return nr % 3 || nr == 0;
1513 case RADEON_PRIM_TYPE_TRI_FAN:
1514 case RADEON_PRIM_TYPE_TRI_STRIP:
1515 return nr < 3;
1516 default:
1517 return 1;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001518 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001519}
1520
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521typedef struct {
1522 unsigned int start;
1523 unsigned int finish;
1524 unsigned int prim;
1525 unsigned int numverts;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001526 unsigned int offset;
1527 unsigned int vc_format;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528} drm_radeon_tcl_prim_t;
1529
Dave Airlie84b1fd12007-07-11 15:53:27 +10001530static void radeon_cp_dispatch_vertex(struct drm_device * dev,
Dave Airlie7c1c2872008-11-28 14:22:24 +10001531 struct drm_file *file_priv,
Dave Airlie056219e2007-07-11 16:17:42 +10001532 struct drm_buf * buf,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001533 drm_radeon_tcl_prim_t * prim)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534{
1535 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10001536 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1537 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001538 int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
1539 int numverts = (int)prim->numverts;
1540 int nbox = sarea_priv->nbox;
1541 int i = 0;
1542 RING_LOCALS;
1543
1544 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
1545 prim->prim,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001546 prim->vc_format, prim->start, prim->finish, prim->numverts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001547
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001548 if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
1549 DRM_ERROR("bad prim %x numverts %d\n",
1550 prim->prim, prim->numverts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551 return;
1552 }
1553
1554 do {
1555 /* Emit the next cliprect */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001556 if (i < nbox) {
1557 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001558 }
1559
1560 /* Emit the vertex buffer rendering commands */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001561 BEGIN_RING(5);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001563 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
1564 OUT_RING(offset);
1565 OUT_RING(numverts);
1566 OUT_RING(prim->vc_format);
1567 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
1568 RADEON_COLOR_ORDER_RGBA |
1569 RADEON_VTX_FMT_RADEON_MODE |
1570 (numverts << RADEON_NUM_VERTICES_SHIFT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001571
1572 ADVANCE_RING();
1573
1574 i++;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001575 } while (i < nbox);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576}
1577
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001578void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001579{
1580 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10001581 struct drm_radeon_master_private *master_priv = master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1583 RING_LOCALS;
1584
Dave Airlie7c1c2872008-11-28 14:22:24 +10001585 buf_priv->age = ++master_priv->sarea_priv->last_dispatch;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001586
1587 /* Emit the vertex buffer age */
Alex Deucherc05ce082009-02-24 16:22:29 -05001588 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1589 BEGIN_RING(3);
1590 R600_DISPATCH_AGE(buf_priv->age);
1591 ADVANCE_RING();
1592 } else {
1593 BEGIN_RING(2);
1594 RADEON_DISPATCH_AGE(buf_priv->age);
1595 ADVANCE_RING();
1596 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597
1598 buf->pending = 1;
1599 buf->used = 0;
1600}
1601
Dave Airlie84b1fd12007-07-11 15:53:27 +10001602static void radeon_cp_dispatch_indirect(struct drm_device * dev,
Dave Airlie056219e2007-07-11 16:17:42 +10001603 struct drm_buf * buf, int start, int end)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604{
1605 drm_radeon_private_t *dev_priv = dev->dev_private;
1606 RING_LOCALS;
Márton Németh3e684ea2008-01-24 15:58:57 +10001607 DRM_DEBUG("buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001609 if (start != end) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001610 int offset = (dev_priv->gart_buffers_offset
1611 + buf->offset + start);
1612 int dwords = (end - start + 3) / sizeof(u32);
1613
1614 /* Indirect buffer data must be an even number of
1615 * dwords, so if we've been given an odd number we must
1616 * pad the data with a Type-2 CP packet.
1617 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001618 if (dwords & 1) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001619 u32 *data = (u32 *)
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001620 ((char *)dev->agp_buffer_map->handle
1621 + buf->offset + start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001622 data[dwords++] = RADEON_CP_PACKET2;
1623 }
1624
1625 /* Fire off the indirect buffer */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001626 BEGIN_RING(3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001627
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001628 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
1629 OUT_RING(offset);
1630 OUT_RING(dwords);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001631
1632 ADVANCE_RING();
1633 }
1634}
1635
Dave Airlie7c1c2872008-11-28 14:22:24 +10001636static void radeon_cp_dispatch_indices(struct drm_device *dev,
1637 struct drm_master *master,
Dave Airlie056219e2007-07-11 16:17:42 +10001638 struct drm_buf * elt_buf,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001639 drm_radeon_tcl_prim_t * prim)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001640{
1641 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10001642 struct drm_radeon_master_private *master_priv = master->driver_priv;
1643 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001644 int offset = dev_priv->gart_buffers_offset + prim->offset;
1645 u32 *data;
1646 int dwords;
1647 int i = 0;
1648 int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
1649 int count = (prim->finish - start) / sizeof(u16);
1650 int nbox = sarea_priv->nbox;
1651
1652 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1653 prim->prim,
1654 prim->vc_format,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001655 prim->start, prim->finish, prim->offset, prim->numverts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001656
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001657 if (bad_prim_vertex_nr(prim->prim, count)) {
1658 DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001659 return;
1660 }
1661
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001662 if (start >= prim->finish || (prim->start & 0x7)) {
1663 DRM_ERROR("buffer prim %d\n", prim->prim);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001664 return;
1665 }
1666
1667 dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1668
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001669 data = (u32 *) ((char *)dev->agp_buffer_map->handle +
1670 elt_buf->offset + prim->start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001671
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001672 data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001673 data[1] = offset;
1674 data[2] = prim->numverts;
1675 data[3] = prim->vc_format;
1676 data[4] = (prim->prim |
1677 RADEON_PRIM_WALK_IND |
1678 RADEON_COLOR_ORDER_RGBA |
1679 RADEON_VTX_FMT_RADEON_MODE |
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001680 (count << RADEON_NUM_VERTICES_SHIFT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001681
1682 do {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001683 if (i < nbox)
1684 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001685
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001686 radeon_cp_dispatch_indirect(dev, elt_buf,
1687 prim->start, prim->finish);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001688
1689 i++;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001690 } while (i < nbox);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001691
1692}
1693
Dave Airlieffbbf7a2005-08-20 17:40:04 +10001694#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
Linus Torvalds1da177e2005-04-16 15:20:36 -07001695
Eric Anholt6c340ea2007-08-25 20:23:09 +10001696static int radeon_cp_dispatch_texture(struct drm_device * dev,
1697 struct drm_file *file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001698 drm_radeon_texture_t * tex,
1699 drm_radeon_tex_image_t * image)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001700{
1701 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie056219e2007-07-11 16:17:42 +10001702 struct drm_buf *buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001703 u32 format;
1704 u32 *buffer;
1705 const u8 __user *data;
Dave Airlieffbbf7a2005-08-20 17:40:04 +10001706 int size, dwords, tex_width, blit_width, spitch;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001707 u32 height;
1708 int i;
1709 u32 texpitch, microtile;
Roland Scheidegger9156cf02008-06-19 11:36:04 +10001710 u32 offset, byte_offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001711 RING_LOCALS;
1712
Eric Anholt6c340ea2007-08-25 20:23:09 +10001713 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001714 DRM_ERROR("Invalid destination offset\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001715 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001716 }
1717
1718 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
1719
1720 /* Flush the pixel cache. This ensures no pixel data gets mixed
1721 * up with the texture data from the host data blit, otherwise
1722 * part of the texture image may be corrupted.
1723 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001724 BEGIN_RING(4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001725 RADEON_FLUSH_CACHE();
1726 RADEON_WAIT_UNTIL_IDLE();
1727 ADVANCE_RING();
1728
Linus Torvalds1da177e2005-04-16 15:20:36 -07001729 /* The compiler won't optimize away a division by a variable,
1730 * even if the only legal values are powers of two. Thus, we'll
1731 * use a shift instead.
1732 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001733 switch (tex->format) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001734 case RADEON_TXFORMAT_ARGB8888:
1735 case RADEON_TXFORMAT_RGBA8888:
1736 format = RADEON_COLOR_FORMAT_ARGB8888;
1737 tex_width = tex->width * 4;
1738 blit_width = image->width * 4;
1739 break;
1740 case RADEON_TXFORMAT_AI88:
1741 case RADEON_TXFORMAT_ARGB1555:
1742 case RADEON_TXFORMAT_RGB565:
1743 case RADEON_TXFORMAT_ARGB4444:
1744 case RADEON_TXFORMAT_VYUY422:
1745 case RADEON_TXFORMAT_YVYU422:
1746 format = RADEON_COLOR_FORMAT_RGB565;
1747 tex_width = tex->width * 2;
1748 blit_width = image->width * 2;
1749 break;
1750 case RADEON_TXFORMAT_I8:
1751 case RADEON_TXFORMAT_RGB332:
1752 format = RADEON_COLOR_FORMAT_CI8;
1753 tex_width = tex->width * 1;
1754 blit_width = image->width * 1;
1755 break;
1756 default:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001757 DRM_ERROR("invalid texture format %d\n", tex->format);
Eric Anholt20caafa2007-08-25 19:22:43 +10001758 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001759 }
Dave Airlieffbbf7a2005-08-20 17:40:04 +10001760 spitch = blit_width >> 6;
1761 if (spitch == 0 && image->height > 1)
Eric Anholt20caafa2007-08-25 19:22:43 +10001762 return -EINVAL;
Dave Airlieffbbf7a2005-08-20 17:40:04 +10001763
Linus Torvalds1da177e2005-04-16 15:20:36 -07001764 texpitch = tex->pitch;
1765 if ((texpitch << 22) & RADEON_DST_TILE_MICRO) {
1766 microtile = 1;
1767 if (tex_width < 64) {
1768 texpitch &= ~(RADEON_DST_TILE_MICRO >> 22);
1769 /* we got tiled coordinates, untile them */
1770 image->x *= 2;
1771 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001772 } else
1773 microtile = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001774
Roland Scheidegger9156cf02008-06-19 11:36:04 +10001775 /* this might fail for zero-sized uploads - are those illegal? */
1776 if (!radeon_check_offset(dev_priv, tex->offset + image->height *
1777 blit_width - 1)) {
1778 DRM_ERROR("Invalid final destination offset\n");
1779 return -EINVAL;
1780 }
1781
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001782 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001783
1784 do {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001785 DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1786 tex->offset >> 10, tex->pitch, tex->format,
1787 image->x, image->y, image->width, image->height);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001788
1789 /* Make a copy of some parameters in case we have to
1790 * update them for a multi-pass texture blit.
1791 */
1792 height = image->height;
1793 data = (const u8 __user *)image->data;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001794
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795 size = height * blit_width;
1796
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001797 if (size > RADEON_MAX_TEXTURE_SIZE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001798 height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1799 size = height * blit_width;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001800 } else if (size < 4 && size > 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001801 size = 4;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001802 } else if (size == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001803 return 0;
1804 }
1805
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001806 buf = radeon_freelist_get(dev);
1807 if (0 && !buf) {
1808 radeon_do_cp_idle(dev_priv);
1809 buf = radeon_freelist_get(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001810 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001811 if (!buf) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001812 DRM_DEBUG("EAGAIN\n");
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001813 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
Eric Anholt20caafa2007-08-25 19:22:43 +10001814 return -EFAULT;
1815 return -EAGAIN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001816 }
1817
Linus Torvalds1da177e2005-04-16 15:20:36 -07001818 /* Dispatch the indirect buffer.
1819 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001820 buffer =
1821 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001822 dwords = size / 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001823
Dave Airlied985c102006-01-02 21:32:48 +11001824#define RADEON_COPY_MT(_buf, _data, _width) \
1825 do { \
1826 if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\
1827 DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \
Eric Anholt20caafa2007-08-25 19:22:43 +10001828 return -EFAULT; \
Dave Airlied985c102006-01-02 21:32:48 +11001829 } \
1830 } while(0)
1831
Linus Torvalds1da177e2005-04-16 15:20:36 -07001832 if (microtile) {
1833 /* texture micro tiling in use, minimum texture width is thus 16 bytes.
1834 however, we cannot use blitter directly for texture width < 64 bytes,
1835 since minimum tex pitch is 64 bytes and we need this to match
1836 the texture width, otherwise the blitter will tile it wrong.
1837 Thus, tiling manually in this case. Additionally, need to special
1838 case tex height = 1, since our actual image will have height 2
1839 and we need to ensure we don't read beyond the texture size
1840 from user space. */
1841 if (tex->height == 1) {
1842 if (tex_width >= 64 || tex_width <= 16) {
Dave Airlied985c102006-01-02 21:32:48 +11001843 RADEON_COPY_MT(buffer, data,
Dave Airlief8e0f292006-01-10 19:56:17 +11001844 (int)(tex_width * sizeof(u32)));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001845 } else if (tex_width == 32) {
Dave Airlied985c102006-01-02 21:32:48 +11001846 RADEON_COPY_MT(buffer, data, 16);
1847 RADEON_COPY_MT(buffer + 8,
1848 data + 16, 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001849 }
1850 } else if (tex_width >= 64 || tex_width == 16) {
Dave Airlied985c102006-01-02 21:32:48 +11001851 RADEON_COPY_MT(buffer, data,
Dave Airlief8e0f292006-01-10 19:56:17 +11001852 (int)(dwords * sizeof(u32)));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001853 } else if (tex_width < 16) {
1854 for (i = 0; i < tex->height; i++) {
Dave Airlied985c102006-01-02 21:32:48 +11001855 RADEON_COPY_MT(buffer, data, tex_width);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001856 buffer += 4;
1857 data += tex_width;
1858 }
1859 } else if (tex_width == 32) {
1860 /* TODO: make sure this works when not fitting in one buffer
1861 (i.e. 32bytes x 2048...) */
1862 for (i = 0; i < tex->height; i += 2) {
Dave Airlied985c102006-01-02 21:32:48 +11001863 RADEON_COPY_MT(buffer, data, 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001864 data += 16;
Dave Airlied985c102006-01-02 21:32:48 +11001865 RADEON_COPY_MT(buffer + 8, data, 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001866 data += 16;
Dave Airlied985c102006-01-02 21:32:48 +11001867 RADEON_COPY_MT(buffer + 4, data, 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001868 data += 16;
Dave Airlied985c102006-01-02 21:32:48 +11001869 RADEON_COPY_MT(buffer + 12, data, 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001870 data += 16;
1871 buffer += 16;
1872 }
1873 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001874 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875 if (tex_width >= 32) {
1876 /* Texture image width is larger than the minimum, so we
1877 * can upload it directly.
1878 */
Dave Airlied985c102006-01-02 21:32:48 +11001879 RADEON_COPY_MT(buffer, data,
Dave Airlief8e0f292006-01-10 19:56:17 +11001880 (int)(dwords * sizeof(u32)));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001881 } else {
1882 /* Texture image width is less than the minimum, so we
1883 * need to pad out each image scanline to the minimum
1884 * width.
1885 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001886 for (i = 0; i < tex->height; i++) {
Dave Airlied985c102006-01-02 21:32:48 +11001887 RADEON_COPY_MT(buffer, data, tex_width);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001888 buffer += 8;
1889 data += tex_width;
1890 }
1891 }
1892 }
1893
Dave Airlied985c102006-01-02 21:32:48 +11001894#undef RADEON_COPY_MT
Roland Scheidegger9156cf02008-06-19 11:36:04 +10001895 byte_offset = (image->y & ~2047) * blit_width;
Eric Anholt6c340ea2007-08-25 20:23:09 +10001896 buf->file_priv = file_priv;
Dave Airlieffbbf7a2005-08-20 17:40:04 +10001897 buf->used = size;
1898 offset = dev_priv->gart_buffers_offset + buf->offset;
1899 BEGIN_RING(9);
1900 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
1901 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1902 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1903 RADEON_GMC_BRUSH_NONE |
1904 (format << 8) |
1905 RADEON_GMC_SRC_DATATYPE_COLOR |
1906 RADEON_ROP3_S |
1907 RADEON_DP_SRC_SOURCE_MEMORY |
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001908 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
Dave Airlieffbbf7a2005-08-20 17:40:04 +10001909 OUT_RING((spitch << 22) | (offset >> 10));
Roland Scheidegger9156cf02008-06-19 11:36:04 +10001910 OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
Dave Airlieffbbf7a2005-08-20 17:40:04 +10001911 OUT_RING(0);
Roland Scheidegger9156cf02008-06-19 11:36:04 +10001912 OUT_RING((image->x << 16) | (image->y % 2048));
Dave Airlieffbbf7a2005-08-20 17:40:04 +10001913 OUT_RING((image->width << 16) | height);
1914 RADEON_WAIT_UNTIL_2D_IDLE();
1915 ADVANCE_RING();
chaohong guoeed0f722007-10-15 10:45:49 +10001916 COMMIT_RING();
Dave Airlieffbbf7a2005-08-20 17:40:04 +10001917
Dave Airlie7c1c2872008-11-28 14:22:24 +10001918 radeon_cp_discard_buffer(dev, file_priv->master, buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001919
1920 /* Update the input parameters for next time */
1921 image->y += height;
1922 image->height -= height;
1923 image->data = (const u8 __user *)image->data + size;
1924 } while (image->height > 0);
1925
1926 /* Flush the pixel cache after the blit completes. This ensures
1927 * the texture data is written out to memory before rendering
1928 * continues.
1929 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001930 BEGIN_RING(4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001931 RADEON_FLUSH_CACHE();
1932 RADEON_WAIT_UNTIL_2D_IDLE();
1933 ADVANCE_RING();
chaohong guoeed0f722007-10-15 10:45:49 +10001934 COMMIT_RING();
1935
Linus Torvalds1da177e2005-04-16 15:20:36 -07001936 return 0;
1937}
1938
Dave Airlie84b1fd12007-07-11 15:53:27 +10001939static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001940{
1941 drm_radeon_private_t *dev_priv = dev->dev_private;
1942 int i;
1943 RING_LOCALS;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001944 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001945
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001946 BEGIN_RING(35);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001947
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001948 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
1949 OUT_RING(0x00000000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001950
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001951 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
1952 for (i = 0; i < 32; i++) {
1953 OUT_RING(stipple[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954 }
1955
1956 ADVANCE_RING();
1957}
1958
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001959static void radeon_apply_surface_regs(int surf_index,
Dave Airlied985c102006-01-02 21:32:48 +11001960 drm_radeon_private_t *dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001961{
1962 if (!dev_priv->mmio)
1963 return;
1964
1965 radeon_do_cp_idle(dev_priv);
1966
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001967 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
1968 dev_priv->surfaces[surf_index].flags);
1969 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
1970 dev_priv->surfaces[surf_index].lower);
1971 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
1972 dev_priv->surfaces[surf_index].upper);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001973}
1974
Linus Torvalds1da177e2005-04-16 15:20:36 -07001975/* Allocates a virtual surface
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001976 * doesn't always allocate a real surface, will stretch an existing
Linus Torvalds1da177e2005-04-16 15:20:36 -07001977 * surface when possible.
1978 *
1979 * Note that refcount can be at most 2, since during a free refcount=3
1980 * might mean we have to allocate a new surface which might not always
1981 * be available.
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02001982 * For example : we allocate three contiguous surfaces ABC. If B is
Linus Torvalds1da177e2005-04-16 15:20:36 -07001983 * freed, we suddenly need two surfaces to store A and C, which might
1984 * not always be available.
1985 */
Dave Airlied985c102006-01-02 21:32:48 +11001986static int alloc_surface(drm_radeon_surface_alloc_t *new,
Eric Anholt6c340ea2007-08-25 20:23:09 +10001987 drm_radeon_private_t *dev_priv,
1988 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001989{
1990 struct radeon_virt_surface *s;
1991 int i;
1992 int virt_surface_index;
1993 uint32_t new_upper, new_lower;
1994
1995 new_lower = new->address;
1996 new_upper = new_lower + new->size - 1;
1997
1998 /* sanity check */
1999 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002000 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
2001 RADEON_SURF_ADDRESS_FIXED_MASK)
2002 || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002003 return -1;
2004
2005 /* make sure there is no overlap with existing surfaces */
2006 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2007 if ((dev_priv->surfaces[i].refcount != 0) &&
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002008 (((new_lower >= dev_priv->surfaces[i].lower) &&
2009 (new_lower < dev_priv->surfaces[i].upper)) ||
2010 ((new_lower < dev_priv->surfaces[i].lower) &&
2011 (new_upper > dev_priv->surfaces[i].lower)))) {
2012 return -1;
2013 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002014 }
2015
2016 /* find a virtual surface */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002017 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
Hannes Eder8f497aa2009-03-05 20:14:18 +01002018 if (dev_priv->virt_surfaces[i].file_priv == NULL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002019 break;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002020 if (i == 2 * RADEON_MAX_SURFACES) {
2021 return -1;
2022 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002023 virt_surface_index = i;
2024
2025 /* try to reuse an existing surface */
2026 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2027 /* extend before */
2028 if ((dev_priv->surfaces[i].refcount == 1) &&
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002029 (new->flags == dev_priv->surfaces[i].flags) &&
2030 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002031 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2032 s->surface_index = i;
2033 s->lower = new_lower;
2034 s->upper = new_upper;
2035 s->flags = new->flags;
Eric Anholt6c340ea2007-08-25 20:23:09 +10002036 s->file_priv = file_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002037 dev_priv->surfaces[i].refcount++;
2038 dev_priv->surfaces[i].lower = s->lower;
2039 radeon_apply_surface_regs(s->surface_index, dev_priv);
2040 return virt_surface_index;
2041 }
2042
2043 /* extend after */
2044 if ((dev_priv->surfaces[i].refcount == 1) &&
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002045 (new->flags == dev_priv->surfaces[i].flags) &&
2046 (new_lower == dev_priv->surfaces[i].upper + 1)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002047 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2048 s->surface_index = i;
2049 s->lower = new_lower;
2050 s->upper = new_upper;
2051 s->flags = new->flags;
Eric Anholt6c340ea2007-08-25 20:23:09 +10002052 s->file_priv = file_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002053 dev_priv->surfaces[i].refcount++;
2054 dev_priv->surfaces[i].upper = s->upper;
2055 radeon_apply_surface_regs(s->surface_index, dev_priv);
2056 return virt_surface_index;
2057 }
2058 }
2059
2060 /* okay, we need a new one */
2061 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2062 if (dev_priv->surfaces[i].refcount == 0) {
2063 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2064 s->surface_index = i;
2065 s->lower = new_lower;
2066 s->upper = new_upper;
2067 s->flags = new->flags;
Eric Anholt6c340ea2007-08-25 20:23:09 +10002068 s->file_priv = file_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002069 dev_priv->surfaces[i].refcount = 1;
2070 dev_priv->surfaces[i].lower = s->lower;
2071 dev_priv->surfaces[i].upper = s->upper;
2072 dev_priv->surfaces[i].flags = s->flags;
2073 radeon_apply_surface_regs(s->surface_index, dev_priv);
2074 return virt_surface_index;
2075 }
2076 }
2077
2078 /* we didn't find anything */
2079 return -1;
2080}
2081
Eric Anholt6c340ea2007-08-25 20:23:09 +10002082static int free_surface(struct drm_file *file_priv,
2083 drm_radeon_private_t * dev_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002084 int lower)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002085{
2086 struct radeon_virt_surface *s;
2087 int i;
2088 /* find the virtual surface */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002089 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002090 s = &(dev_priv->virt_surfaces[i]);
Eric Anholt6c340ea2007-08-25 20:23:09 +10002091 if (s->file_priv) {
2092 if ((lower == s->lower) && (file_priv == s->file_priv))
2093 {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002094 if (dev_priv->surfaces[s->surface_index].
2095 lower == s->lower)
2096 dev_priv->surfaces[s->surface_index].
2097 lower = s->upper;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002098
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002099 if (dev_priv->surfaces[s->surface_index].
2100 upper == s->upper)
2101 dev_priv->surfaces[s->surface_index].
2102 upper = s->lower;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002103
2104 dev_priv->surfaces[s->surface_index].refcount--;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002105 if (dev_priv->surfaces[s->surface_index].
2106 refcount == 0)
2107 dev_priv->surfaces[s->surface_index].
2108 flags = 0;
Eric Anholt6c340ea2007-08-25 20:23:09 +10002109 s->file_priv = NULL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002110 radeon_apply_surface_regs(s->surface_index,
2111 dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002112 return 0;
2113 }
2114 }
2115 }
2116 return 1;
2117}
2118
Eric Anholt6c340ea2007-08-25 20:23:09 +10002119static void radeon_surfaces_release(struct drm_file *file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002120 drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002121{
2122 int i;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002123 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
Eric Anholt6c340ea2007-08-25 20:23:09 +10002124 if (dev_priv->virt_surfaces[i].file_priv == file_priv)
2125 free_surface(file_priv, dev_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002126 dev_priv->virt_surfaces[i].lower);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002127 }
2128}
2129
2130/* ================================================================
2131 * IOCTL functions
2132 */
Eric Anholtc153f452007-09-03 12:06:45 +10002133static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002134{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002135 drm_radeon_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10002136 drm_radeon_surface_alloc_t *alloc = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002137
Eric Anholtc153f452007-09-03 12:06:45 +10002138 if (alloc_surface(alloc, dev_priv, file_priv) == -1)
Eric Anholt20caafa2007-08-25 19:22:43 +10002139 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002140 else
2141 return 0;
2142}
2143
Eric Anholtc153f452007-09-03 12:06:45 +10002144static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002145{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002146 drm_radeon_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10002147 drm_radeon_surface_free_t *memfree = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002148
Eric Anholtc153f452007-09-03 12:06:45 +10002149 if (free_surface(file_priv, dev_priv, memfree->address))
Eric Anholt20caafa2007-08-25 19:22:43 +10002150 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002151 else
2152 return 0;
2153}
2154
Eric Anholtc153f452007-09-03 12:06:45 +10002155static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002156{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002157 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10002158 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2159 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
Eric Anholtc153f452007-09-03 12:06:45 +10002160 drm_radeon_clear_t *clear = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002161 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002162 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002163
Eric Anholt6c340ea2007-08-25 20:23:09 +10002164 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002165
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002166 RING_SPACE_TEST_WITH_RETURN(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002167
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002168 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002169 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2170
Eric Anholtc153f452007-09-03 12:06:45 +10002171 if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002172 sarea_priv->nbox * sizeof(depth_boxes[0])))
Eric Anholt20caafa2007-08-25 19:22:43 +10002173 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002174
Dave Airlie7c1c2872008-11-28 14:22:24 +10002175 radeon_cp_dispatch_clear(dev, file_priv->master, clear, depth_boxes);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002176
2177 COMMIT_RING();
2178 return 0;
2179}
2180
Linus Torvalds1da177e2005-04-16 15:20:36 -07002181/* Not sure why this isn't set all the time:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002182 */
Dave Airlie7c1c2872008-11-28 14:22:24 +10002183static int radeon_do_init_pageflip(struct drm_device *dev, struct drm_master *master)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002184{
2185 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10002186 struct drm_radeon_master_private *master_priv = master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002187 RING_LOCALS;
2188
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002189 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002190
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002191 BEGIN_RING(6);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002192 RADEON_WAIT_UNTIL_3D_IDLE();
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002193 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
2194 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
2195 RADEON_CRTC_OFFSET_FLIP_CNTL);
2196 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
2197 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
2198 RADEON_CRTC_OFFSET_FLIP_CNTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002199 ADVANCE_RING();
2200
2201 dev_priv->page_flipping = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002202
Dave Airlie7c1c2872008-11-28 14:22:24 +10002203 if (master_priv->sarea_priv->pfCurrentPage != 1)
2204 master_priv->sarea_priv->pfCurrentPage = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002205
Linus Torvalds1da177e2005-04-16 15:20:36 -07002206 return 0;
2207}
2208
2209/* Swapping and flipping are different operations, need different ioctls.
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002210 * They can & should be intermixed to support multiple 3d windows.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002211 */
Eric Anholtc153f452007-09-03 12:06:45 +10002212static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002213{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002214 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002215 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002216
Eric Anholt6c340ea2007-08-25 20:23:09 +10002217 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002218
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002219 RING_SPACE_TEST_WITH_RETURN(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002220
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002221 if (!dev_priv->page_flipping)
Dave Airlie7c1c2872008-11-28 14:22:24 +10002222 radeon_do_init_pageflip(dev, file_priv->master);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002223
Dave Airlie7c1c2872008-11-28 14:22:24 +10002224 radeon_cp_dispatch_flip(dev, file_priv->master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002225
2226 COMMIT_RING();
2227 return 0;
2228}
2229
Eric Anholtc153f452007-09-03 12:06:45 +10002230static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002231{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002232 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10002233 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2234 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2235
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002236 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002237
Eric Anholt6c340ea2007-08-25 20:23:09 +10002238 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002239
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002240 RING_SPACE_TEST_WITH_RETURN(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002241
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002242 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002243 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2244
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002245 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2246 r600_cp_dispatch_swap(dev, file_priv);
2247 else
2248 radeon_cp_dispatch_swap(dev, file_priv->master);
Dave Airlie7c1c2872008-11-28 14:22:24 +10002249 sarea_priv->ctx_owner = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002250
2251 COMMIT_RING();
2252 return 0;
2253}
2254
Eric Anholtc153f452007-09-03 12:06:45 +10002255static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002256{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002257 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10002258 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2259 drm_radeon_sarea_t *sarea_priv;
Dave Airliecdd55a22007-07-11 16:32:08 +10002260 struct drm_device_dma *dma = dev->dma;
Dave Airlie056219e2007-07-11 16:17:42 +10002261 struct drm_buf *buf;
Eric Anholtc153f452007-09-03 12:06:45 +10002262 drm_radeon_vertex_t *vertex = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002263 drm_radeon_tcl_prim_t prim;
2264
Eric Anholt6c340ea2007-08-25 20:23:09 +10002265 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002266
Dave Airlie7c1c2872008-11-28 14:22:24 +10002267 sarea_priv = master_priv->sarea_priv;
2268
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002269 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
Eric Anholtc153f452007-09-03 12:06:45 +10002270 DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002271
Eric Anholtc153f452007-09-03 12:06:45 +10002272 if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002273 DRM_ERROR("buffer index %d (of %d max)\n",
Eric Anholtc153f452007-09-03 12:06:45 +10002274 vertex->idx, dma->buf_count - 1);
Eric Anholt20caafa2007-08-25 19:22:43 +10002275 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002276 }
Eric Anholtc153f452007-09-03 12:06:45 +10002277 if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2278 DRM_ERROR("buffer prim %d\n", vertex->prim);
Eric Anholt20caafa2007-08-25 19:22:43 +10002279 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002280 }
2281
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002282 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2283 VB_AGE_TEST_WITH_RETURN(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002284
Eric Anholtc153f452007-09-03 12:06:45 +10002285 buf = dma->buflist[vertex->idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002286
Eric Anholt6c340ea2007-08-25 20:23:09 +10002287 if (buf->file_priv != file_priv) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002288 DRM_ERROR("process %d using buffer owned by %p\n",
Eric Anholt6c340ea2007-08-25 20:23:09 +10002289 DRM_CURRENTPID, buf->file_priv);
Eric Anholt20caafa2007-08-25 19:22:43 +10002290 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002291 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002292 if (buf->pending) {
Eric Anholtc153f452007-09-03 12:06:45 +10002293 DRM_ERROR("sending pending buffer %d\n", vertex->idx);
Eric Anholt20caafa2007-08-25 19:22:43 +10002294 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002295 }
2296
2297 /* Build up a prim_t record:
2298 */
Eric Anholtc153f452007-09-03 12:06:45 +10002299 if (vertex->count) {
2300 buf->used = vertex->count; /* not used? */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002301
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002302 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
Eric Anholt6c340ea2007-08-25 20:23:09 +10002303 if (radeon_emit_state(dev_priv, file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002304 &sarea_priv->context_state,
2305 sarea_priv->tex_state,
2306 sarea_priv->dirty)) {
2307 DRM_ERROR("radeon_emit_state failed\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10002308 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002309 }
2310
2311 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2312 RADEON_UPLOAD_TEX1IMAGES |
2313 RADEON_UPLOAD_TEX2IMAGES |
2314 RADEON_REQUIRE_QUIESCENCE);
2315 }
2316
2317 prim.start = 0;
Eric Anholtc153f452007-09-03 12:06:45 +10002318 prim.finish = vertex->count; /* unused */
2319 prim.prim = vertex->prim;
2320 prim.numverts = vertex->count;
Dave Airlie7c1c2872008-11-28 14:22:24 +10002321 prim.vc_format = sarea_priv->vc_format;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002322
Dave Airlie7c1c2872008-11-28 14:22:24 +10002323 radeon_cp_dispatch_vertex(dev, file_priv, buf, &prim);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002324 }
2325
Eric Anholtc153f452007-09-03 12:06:45 +10002326 if (vertex->discard) {
Dave Airlie7c1c2872008-11-28 14:22:24 +10002327 radeon_cp_discard_buffer(dev, file_priv->master, buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002328 }
2329
2330 COMMIT_RING();
2331 return 0;
2332}
2333
Eric Anholtc153f452007-09-03 12:06:45 +10002334static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002335{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002336 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10002337 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2338 drm_radeon_sarea_t *sarea_priv;
Dave Airliecdd55a22007-07-11 16:32:08 +10002339 struct drm_device_dma *dma = dev->dma;
Dave Airlie056219e2007-07-11 16:17:42 +10002340 struct drm_buf *buf;
Eric Anholtc153f452007-09-03 12:06:45 +10002341 drm_radeon_indices_t *elts = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002342 drm_radeon_tcl_prim_t prim;
2343 int count;
2344
Eric Anholt6c340ea2007-08-25 20:23:09 +10002345 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002346
Dave Airlie7c1c2872008-11-28 14:22:24 +10002347 sarea_priv = master_priv->sarea_priv;
2348
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002349 DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
Eric Anholtc153f452007-09-03 12:06:45 +10002350 DRM_CURRENTPID, elts->idx, elts->start, elts->end,
2351 elts->discard);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002352
Eric Anholtc153f452007-09-03 12:06:45 +10002353 if (elts->idx < 0 || elts->idx >= dma->buf_count) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002354 DRM_ERROR("buffer index %d (of %d max)\n",
Eric Anholtc153f452007-09-03 12:06:45 +10002355 elts->idx, dma->buf_count - 1);
Eric Anholt20caafa2007-08-25 19:22:43 +10002356 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002357 }
Eric Anholtc153f452007-09-03 12:06:45 +10002358 if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2359 DRM_ERROR("buffer prim %d\n", elts->prim);
Eric Anholt20caafa2007-08-25 19:22:43 +10002360 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002361 }
2362
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002363 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2364 VB_AGE_TEST_WITH_RETURN(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002365
Eric Anholtc153f452007-09-03 12:06:45 +10002366 buf = dma->buflist[elts->idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002367
Eric Anholt6c340ea2007-08-25 20:23:09 +10002368 if (buf->file_priv != file_priv) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002369 DRM_ERROR("process %d using buffer owned by %p\n",
Eric Anholt6c340ea2007-08-25 20:23:09 +10002370 DRM_CURRENTPID, buf->file_priv);
Eric Anholt20caafa2007-08-25 19:22:43 +10002371 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002372 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002373 if (buf->pending) {
Eric Anholtc153f452007-09-03 12:06:45 +10002374 DRM_ERROR("sending pending buffer %d\n", elts->idx);
Eric Anholt20caafa2007-08-25 19:22:43 +10002375 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002376 }
2377
Eric Anholtc153f452007-09-03 12:06:45 +10002378 count = (elts->end - elts->start) / sizeof(u16);
2379 elts->start -= RADEON_INDEX_PRIM_OFFSET;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002380
Eric Anholtc153f452007-09-03 12:06:45 +10002381 if (elts->start & 0x7) {
2382 DRM_ERROR("misaligned buffer 0x%x\n", elts->start);
Eric Anholt20caafa2007-08-25 19:22:43 +10002383 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002384 }
Eric Anholtc153f452007-09-03 12:06:45 +10002385 if (elts->start < buf->used) {
2386 DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used);
Eric Anholt20caafa2007-08-25 19:22:43 +10002387 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002388 }
2389
Eric Anholtc153f452007-09-03 12:06:45 +10002390 buf->used = elts->end;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002391
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002392 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
Eric Anholt6c340ea2007-08-25 20:23:09 +10002393 if (radeon_emit_state(dev_priv, file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002394 &sarea_priv->context_state,
2395 sarea_priv->tex_state,
2396 sarea_priv->dirty)) {
2397 DRM_ERROR("radeon_emit_state failed\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10002398 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002399 }
2400
2401 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2402 RADEON_UPLOAD_TEX1IMAGES |
2403 RADEON_UPLOAD_TEX2IMAGES |
2404 RADEON_REQUIRE_QUIESCENCE);
2405 }
2406
Linus Torvalds1da177e2005-04-16 15:20:36 -07002407 /* Build up a prim_t record:
2408 */
Eric Anholtc153f452007-09-03 12:06:45 +10002409 prim.start = elts->start;
2410 prim.finish = elts->end;
2411 prim.prim = elts->prim;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002412 prim.offset = 0; /* offset from start of dma buffers */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002413 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
Dave Airlie7c1c2872008-11-28 14:22:24 +10002414 prim.vc_format = sarea_priv->vc_format;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002415
Dave Airlie7c1c2872008-11-28 14:22:24 +10002416 radeon_cp_dispatch_indices(dev, file_priv->master, buf, &prim);
Eric Anholtc153f452007-09-03 12:06:45 +10002417 if (elts->discard) {
Dave Airlie7c1c2872008-11-28 14:22:24 +10002418 radeon_cp_discard_buffer(dev, file_priv->master, buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002419 }
2420
2421 COMMIT_RING();
2422 return 0;
2423}
2424
Eric Anholtc153f452007-09-03 12:06:45 +10002425static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002426{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002427 drm_radeon_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10002428 drm_radeon_texture_t *tex = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002429 drm_radeon_tex_image_t image;
2430 int ret;
2431
Eric Anholt6c340ea2007-08-25 20:23:09 +10002432 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002433
Eric Anholtc153f452007-09-03 12:06:45 +10002434 if (tex->image == NULL) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002435 DRM_ERROR("null texture image!\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10002436 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002437 }
2438
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002439 if (DRM_COPY_FROM_USER(&image,
Eric Anholtc153f452007-09-03 12:06:45 +10002440 (drm_radeon_tex_image_t __user *) tex->image,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002441 sizeof(image)))
Eric Anholt20caafa2007-08-25 19:22:43 +10002442 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002443
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002444 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2445 VB_AGE_TEST_WITH_RETURN(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002446
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002447 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2448 ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image);
2449 else
2450 ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002451
Linus Torvalds1da177e2005-04-16 15:20:36 -07002452 return ret;
2453}
2454
Eric Anholtc153f452007-09-03 12:06:45 +10002455static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002456{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002457 drm_radeon_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10002458 drm_radeon_stipple_t *stipple = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002459 u32 mask[32];
2460
Eric Anholt6c340ea2007-08-25 20:23:09 +10002461 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002462
Eric Anholtc153f452007-09-03 12:06:45 +10002463 if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32)))
Eric Anholt20caafa2007-08-25 19:22:43 +10002464 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002465
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002466 RING_SPACE_TEST_WITH_RETURN(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002467
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002468 radeon_cp_dispatch_stipple(dev, mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002469
2470 COMMIT_RING();
2471 return 0;
2472}
2473
Eric Anholtc153f452007-09-03 12:06:45 +10002474static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002475{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002476 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airliecdd55a22007-07-11 16:32:08 +10002477 struct drm_device_dma *dma = dev->dma;
Dave Airlie056219e2007-07-11 16:17:42 +10002478 struct drm_buf *buf;
Eric Anholtc153f452007-09-03 12:06:45 +10002479 drm_radeon_indirect_t *indirect = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002480 RING_LOCALS;
2481
Eric Anholt6c340ea2007-08-25 20:23:09 +10002482 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002483
Márton Németh3e684ea2008-01-24 15:58:57 +10002484 DRM_DEBUG("idx=%d s=%d e=%d d=%d\n",
Eric Anholtc153f452007-09-03 12:06:45 +10002485 indirect->idx, indirect->start, indirect->end,
2486 indirect->discard);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002487
Eric Anholtc153f452007-09-03 12:06:45 +10002488 if (indirect->idx < 0 || indirect->idx >= dma->buf_count) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002489 DRM_ERROR("buffer index %d (of %d max)\n",
Eric Anholtc153f452007-09-03 12:06:45 +10002490 indirect->idx, dma->buf_count - 1);
Eric Anholt20caafa2007-08-25 19:22:43 +10002491 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002492 }
2493
Eric Anholtc153f452007-09-03 12:06:45 +10002494 buf = dma->buflist[indirect->idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002495
Eric Anholt6c340ea2007-08-25 20:23:09 +10002496 if (buf->file_priv != file_priv) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002497 DRM_ERROR("process %d using buffer owned by %p\n",
Eric Anholt6c340ea2007-08-25 20:23:09 +10002498 DRM_CURRENTPID, buf->file_priv);
Eric Anholt20caafa2007-08-25 19:22:43 +10002499 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002500 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002501 if (buf->pending) {
Eric Anholtc153f452007-09-03 12:06:45 +10002502 DRM_ERROR("sending pending buffer %d\n", indirect->idx);
Eric Anholt20caafa2007-08-25 19:22:43 +10002503 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002504 }
2505
Eric Anholtc153f452007-09-03 12:06:45 +10002506 if (indirect->start < buf->used) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002507 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
Eric Anholtc153f452007-09-03 12:06:45 +10002508 indirect->start, buf->used);
Eric Anholt20caafa2007-08-25 19:22:43 +10002509 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002510 }
2511
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002512 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2513 VB_AGE_TEST_WITH_RETURN(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002514
Eric Anholtc153f452007-09-03 12:06:45 +10002515 buf->used = indirect->end;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002516
Linus Torvalds1da177e2005-04-16 15:20:36 -07002517 /* Dispatch the indirect buffer full of commands from the
2518 * X server. This is insecure and is thus only available to
2519 * privileged clients.
2520 */
Alex Deucherc05ce082009-02-24 16:22:29 -05002521 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2522 r600_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
2523 else {
2524 /* Wait for the 3D stream to idle before the indirect buffer
2525 * containing 2D acceleration commands is processed.
2526 */
2527 BEGIN_RING(2);
2528 RADEON_WAIT_UNTIL_3D_IDLE();
2529 ADVANCE_RING();
2530 radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002531 }
2532
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002533 if (indirect->discard) {
Alex Deucherc05ce082009-02-24 16:22:29 -05002534 radeon_cp_discard_buffer(dev, file_priv->master, buf);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002535 }
Alex Deucherc05ce082009-02-24 16:22:29 -05002536
Linus Torvalds1da177e2005-04-16 15:20:36 -07002537 COMMIT_RING();
2538 return 0;
2539}
2540
Eric Anholtc153f452007-09-03 12:06:45 +10002541static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002542{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002543 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10002544 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2545 drm_radeon_sarea_t *sarea_priv;
Dave Airliecdd55a22007-07-11 16:32:08 +10002546 struct drm_device_dma *dma = dev->dma;
Dave Airlie056219e2007-07-11 16:17:42 +10002547 struct drm_buf *buf;
Eric Anholtc153f452007-09-03 12:06:45 +10002548 drm_radeon_vertex2_t *vertex = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002549 int i;
2550 unsigned char laststate;
2551
Eric Anholt6c340ea2007-08-25 20:23:09 +10002552 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002553
Dave Airlie7c1c2872008-11-28 14:22:24 +10002554 sarea_priv = master_priv->sarea_priv;
2555
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002556 DRM_DEBUG("pid=%d index=%d discard=%d\n",
Eric Anholtc153f452007-09-03 12:06:45 +10002557 DRM_CURRENTPID, vertex->idx, vertex->discard);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002558
Eric Anholtc153f452007-09-03 12:06:45 +10002559 if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002560 DRM_ERROR("buffer index %d (of %d max)\n",
Eric Anholtc153f452007-09-03 12:06:45 +10002561 vertex->idx, dma->buf_count - 1);
Eric Anholt20caafa2007-08-25 19:22:43 +10002562 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002563 }
2564
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002565 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2566 VB_AGE_TEST_WITH_RETURN(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002567
Eric Anholtc153f452007-09-03 12:06:45 +10002568 buf = dma->buflist[vertex->idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002569
Eric Anholt6c340ea2007-08-25 20:23:09 +10002570 if (buf->file_priv != file_priv) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002571 DRM_ERROR("process %d using buffer owned by %p\n",
Eric Anholt6c340ea2007-08-25 20:23:09 +10002572 DRM_CURRENTPID, buf->file_priv);
Eric Anholt20caafa2007-08-25 19:22:43 +10002573 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002574 }
2575
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002576 if (buf->pending) {
Eric Anholtc153f452007-09-03 12:06:45 +10002577 DRM_ERROR("sending pending buffer %d\n", vertex->idx);
Eric Anholt20caafa2007-08-25 19:22:43 +10002578 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002579 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002580
Linus Torvalds1da177e2005-04-16 15:20:36 -07002581 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
Eric Anholt20caafa2007-08-25 19:22:43 +10002582 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002583
Eric Anholtc153f452007-09-03 12:06:45 +10002584 for (laststate = 0xff, i = 0; i < vertex->nr_prims; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002585 drm_radeon_prim_t prim;
2586 drm_radeon_tcl_prim_t tclprim;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002587
Eric Anholtc153f452007-09-03 12:06:45 +10002588 if (DRM_COPY_FROM_USER(&prim, &vertex->prim[i], sizeof(prim)))
Eric Anholt20caafa2007-08-25 19:22:43 +10002589 return -EFAULT;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002590
2591 if (prim.stateidx != laststate) {
2592 drm_radeon_state_t state;
2593
2594 if (DRM_COPY_FROM_USER(&state,
Eric Anholtc153f452007-09-03 12:06:45 +10002595 &vertex->state[prim.stateidx],
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002596 sizeof(state)))
Eric Anholt20caafa2007-08-25 19:22:43 +10002597 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002598
Eric Anholt6c340ea2007-08-25 20:23:09 +10002599 if (radeon_emit_state2(dev_priv, file_priv, &state)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002600 DRM_ERROR("radeon_emit_state2 failed\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10002601 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002602 }
2603
2604 laststate = prim.stateidx;
2605 }
2606
2607 tclprim.start = prim.start;
2608 tclprim.finish = prim.finish;
2609 tclprim.prim = prim.prim;
2610 tclprim.vc_format = prim.vc_format;
2611
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002612 if (prim.prim & RADEON_PRIM_WALK_IND) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002613 tclprim.offset = prim.numverts * 64;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002614 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002615
Dave Airlie7c1c2872008-11-28 14:22:24 +10002616 radeon_cp_dispatch_indices(dev, file_priv->master, buf, &tclprim);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002617 } else {
2618 tclprim.numverts = prim.numverts;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002619 tclprim.offset = 0; /* not used */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002620
Dave Airlie7c1c2872008-11-28 14:22:24 +10002621 radeon_cp_dispatch_vertex(dev, file_priv, buf, &tclprim);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002622 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002623
Linus Torvalds1da177e2005-04-16 15:20:36 -07002624 if (sarea_priv->nbox == 1)
2625 sarea_priv->nbox = 0;
2626 }
2627
Eric Anholtc153f452007-09-03 12:06:45 +10002628 if (vertex->discard) {
Dave Airlie7c1c2872008-11-28 14:22:24 +10002629 radeon_cp_discard_buffer(dev, file_priv->master, buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002630 }
2631
2632 COMMIT_RING();
2633 return 0;
2634}
2635
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002636static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
Eric Anholt6c340ea2007-08-25 20:23:09 +10002637 struct drm_file *file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002638 drm_radeon_cmd_header_t header,
Dave Airlieb3a83632005-09-30 18:37:36 +10002639 drm_radeon_kcmd_buffer_t *cmdbuf)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002640{
2641 int id = (int)header.packet.packet_id;
2642 int sz, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002643 RING_LOCALS;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002644
Linus Torvalds1da177e2005-04-16 15:20:36 -07002645 if (id >= RADEON_MAX_STATE_PACKETS)
Eric Anholt20caafa2007-08-25 19:22:43 +10002646 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002647
2648 sz = packet[id].len;
2649 reg = packet[id].start;
2650
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002651 if (sz * sizeof(u32) > drm_buffer_unprocessed(cmdbuf->buffer)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002652 DRM_ERROR("Packet size provided larger than data provided\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10002653 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002654 }
2655
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002656 if (radeon_check_and_fixup_packets(dev_priv, file_priv, id,
2657 cmdbuf->buffer)) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002658 DRM_ERROR("Packet verification failed\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10002659 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002660 }
2661
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002662 BEGIN_RING(sz + 1);
2663 OUT_RING(CP_PACKET0(reg, (sz - 1)));
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002664 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002665 ADVANCE_RING();
2666
Linus Torvalds1da177e2005-04-16 15:20:36 -07002667 return 0;
2668}
2669
Dave Airlied985c102006-01-02 21:32:48 +11002670static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002671 drm_radeon_cmd_header_t header,
Dave Airlied985c102006-01-02 21:32:48 +11002672 drm_radeon_kcmd_buffer_t *cmdbuf)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002673{
2674 int sz = header.scalars.count;
2675 int start = header.scalars.offset;
2676 int stride = header.scalars.stride;
2677 RING_LOCALS;
2678
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002679 BEGIN_RING(3 + sz);
2680 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2681 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2682 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002683 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002684 ADVANCE_RING();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002685 return 0;
2686}
2687
2688/* God this is ugly
2689 */
Dave Airlied985c102006-01-02 21:32:48 +11002690static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002691 drm_radeon_cmd_header_t header,
Dave Airlied985c102006-01-02 21:32:48 +11002692 drm_radeon_kcmd_buffer_t *cmdbuf)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002693{
2694 int sz = header.scalars.count;
2695 int start = ((unsigned int)header.scalars.offset) + 0x100;
2696 int stride = header.scalars.stride;
2697 RING_LOCALS;
2698
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002699 BEGIN_RING(3 + sz);
2700 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2701 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2702 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002703 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002704 ADVANCE_RING();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002705 return 0;
2706}
2707
Dave Airlied985c102006-01-02 21:32:48 +11002708static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002709 drm_radeon_cmd_header_t header,
Dave Airlied985c102006-01-02 21:32:48 +11002710 drm_radeon_kcmd_buffer_t *cmdbuf)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002711{
2712 int sz = header.vectors.count;
2713 int start = header.vectors.offset;
2714 int stride = header.vectors.stride;
2715 RING_LOCALS;
2716
Dave Airlief2a22792006-06-24 16:55:34 +10002717 BEGIN_RING(5 + sz);
2718 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002719 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2720 OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2721 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002722 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002723 ADVANCE_RING();
2724
Linus Torvalds1da177e2005-04-16 15:20:36 -07002725 return 0;
2726}
2727
Dave Airlied6fece02006-06-24 17:04:07 +10002728static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
2729 drm_radeon_cmd_header_t header,
2730 drm_radeon_kcmd_buffer_t *cmdbuf)
2731{
2732 int sz = header.veclinear.count * 4;
2733 int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
2734 RING_LOCALS;
2735
2736 if (!sz)
2737 return 0;
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002738 if (sz * 4 > drm_buffer_unprocessed(cmdbuf->buffer))
Eric Anholt20caafa2007-08-25 19:22:43 +10002739 return -EINVAL;
Dave Airlied6fece02006-06-24 17:04:07 +10002740
2741 BEGIN_RING(5 + sz);
2742 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
2743 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2744 OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2745 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002746 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
Dave Airlied6fece02006-06-24 17:04:07 +10002747 ADVANCE_RING();
2748
Dave Airlied6fece02006-06-24 17:04:07 +10002749 return 0;
2750}
2751
Dave Airlie84b1fd12007-07-11 15:53:27 +10002752static int radeon_emit_packet3(struct drm_device * dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +10002753 struct drm_file *file_priv,
Dave Airlieb3a83632005-09-30 18:37:36 +10002754 drm_radeon_kcmd_buffer_t *cmdbuf)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002755{
2756 drm_radeon_private_t *dev_priv = dev->dev_private;
2757 unsigned int cmdsz;
2758 int ret;
2759 RING_LOCALS;
2760
2761 DRM_DEBUG("\n");
2762
Eric Anholt6c340ea2007-08-25 20:23:09 +10002763 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002764 cmdbuf, &cmdsz))) {
2765 DRM_ERROR("Packet verification failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002766 return ret;
2767 }
2768
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002769 BEGIN_RING(cmdsz);
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002770 OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002771 ADVANCE_RING();
2772
Linus Torvalds1da177e2005-04-16 15:20:36 -07002773 return 0;
2774}
2775
Dave Airlie84b1fd12007-07-11 15:53:27 +10002776static int radeon_emit_packet3_cliprect(struct drm_device *dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +10002777 struct drm_file *file_priv,
Dave Airlieb3a83632005-09-30 18:37:36 +10002778 drm_radeon_kcmd_buffer_t *cmdbuf,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002779 int orig_nbox)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002780{
2781 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airliec60ce622007-07-11 15:27:12 +10002782 struct drm_clip_rect box;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002783 unsigned int cmdsz;
2784 int ret;
Dave Airliec60ce622007-07-11 15:27:12 +10002785 struct drm_clip_rect __user *boxes = cmdbuf->boxes;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002786 int i = 0;
2787 RING_LOCALS;
2788
2789 DRM_DEBUG("\n");
2790
Eric Anholt6c340ea2007-08-25 20:23:09 +10002791 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002792 cmdbuf, &cmdsz))) {
2793 DRM_ERROR("Packet verification failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002794 return ret;
2795 }
2796
2797 if (!orig_nbox)
2798 goto out;
2799
2800 do {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002801 if (i < cmdbuf->nbox) {
2802 if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box)))
Eric Anholt20caafa2007-08-25 19:22:43 +10002803 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002804 /* FIXME The second and subsequent times round
2805 * this loop, send a WAIT_UNTIL_3D_IDLE before
2806 * calling emit_clip_rect(). This fixes a
2807 * lockup on fast machines when sending
2808 * several cliprects with a cmdbuf, as when
2809 * waving a 2D window over a 3D
2810 * window. Something in the commands from user
2811 * space seems to hang the card when they're
2812 * sent several times in a row. That would be
2813 * the correct place to fix it but this works
2814 * around it until I can figure that out - Tim
2815 * Smith */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002816 if (i) {
2817 BEGIN_RING(2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002818 RADEON_WAIT_UNTIL_3D_IDLE();
2819 ADVANCE_RING();
2820 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002821 radeon_emit_clip_rect(dev_priv, &box);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002822 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002823
2824 BEGIN_RING(cmdsz);
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002825 OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002826 ADVANCE_RING();
2827
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002828 } while (++i < cmdbuf->nbox);
2829 if (cmdbuf->nbox == 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002830 cmdbuf->nbox = 0;
2831
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002832 return 0;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002833 out:
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002834 drm_buffer_advance(cmdbuf->buffer, cmdsz * 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002835 return 0;
2836}
2837
Dave Airlie84b1fd12007-07-11 15:53:27 +10002838static int radeon_emit_wait(struct drm_device * dev, int flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002839{
2840 drm_radeon_private_t *dev_priv = dev->dev_private;
2841 RING_LOCALS;
2842
Márton Németh3e684ea2008-01-24 15:58:57 +10002843 DRM_DEBUG("%x\n", flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002844 switch (flags) {
2845 case RADEON_WAIT_2D:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002846 BEGIN_RING(2);
2847 RADEON_WAIT_UNTIL_2D_IDLE();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002848 ADVANCE_RING();
2849 break;
2850 case RADEON_WAIT_3D:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002851 BEGIN_RING(2);
2852 RADEON_WAIT_UNTIL_3D_IDLE();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002853 ADVANCE_RING();
2854 break;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002855 case RADEON_WAIT_2D | RADEON_WAIT_3D:
2856 BEGIN_RING(2);
2857 RADEON_WAIT_UNTIL_IDLE();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002858 ADVANCE_RING();
2859 break;
2860 default:
Eric Anholt20caafa2007-08-25 19:22:43 +10002861 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002862 }
2863
2864 return 0;
2865}
2866
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002867static int radeon_cp_cmdbuf(struct drm_device *dev, void *data,
2868 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002869{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002870 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airliecdd55a22007-07-11 16:32:08 +10002871 struct drm_device_dma *dma = dev->dma;
Dave Airlie056219e2007-07-11 16:17:42 +10002872 struct drm_buf *buf = NULL;
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002873 drm_radeon_cmd_header_t stack_header;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002874 int idx;
Eric Anholtc153f452007-09-03 12:06:45 +10002875 drm_radeon_kcmd_buffer_t *cmdbuf = data;
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002876 int orig_nbox;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002877
Eric Anholt6c340ea2007-08-25 20:23:09 +10002878 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002879
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002880 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2881 VB_AGE_TEST_WITH_RETURN(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002882
Eric Anholtc153f452007-09-03 12:06:45 +10002883 if (cmdbuf->bufsz > 64 * 1024 || cmdbuf->bufsz < 0) {
Eric Anholt20caafa2007-08-25 19:22:43 +10002884 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002885 }
2886
2887 /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid
2888 * races between checking values and using those values in other code,
2889 * and simply to avoid a lot of function calls to copy in data.
2890 */
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002891 if (cmdbuf->bufsz != 0) {
2892 int rv;
2893 void __user *buffer = cmdbuf->buffer;
2894 rv = drm_buffer_alloc(&cmdbuf->buffer, cmdbuf->bufsz);
2895 if (rv)
2896 return rv;
2897 rv = drm_buffer_copy_from_user(cmdbuf->buffer, buffer,
2898 cmdbuf->bufsz);
Jean Delvarec9ff04c2010-05-11 14:01:45 +10002899 if (rv) {
2900 drm_buffer_free(cmdbuf->buffer);
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002901 return rv;
Jean Delvarec9ff04c2010-05-11 14:01:45 +10002902 }
2903 } else
2904 goto done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002905
Eric Anholtc153f452007-09-03 12:06:45 +10002906 orig_nbox = cmdbuf->nbox;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002907
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002908 if (dev_priv->microcode_version == UCODE_R300) {
Dave Airlie414ed532005-08-16 20:43:16 +10002909 int temp;
Eric Anholtc153f452007-09-03 12:06:45 +10002910 temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002911
Jean Delvarec9ff04c2010-05-11 14:01:45 +10002912 drm_buffer_free(cmdbuf->buffer);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002913
Dave Airlie414ed532005-08-16 20:43:16 +10002914 return temp;
2915 }
2916
2917 /* microcode_version != r300 */
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002918 while (drm_buffer_unprocessed(cmdbuf->buffer) >= sizeof(stack_header)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002919
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002920 drm_radeon_cmd_header_t *header;
2921 header = drm_buffer_read_object(cmdbuf->buffer,
2922 sizeof(stack_header), &stack_header);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002923
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002924 switch (header->header.cmd_type) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002925 case RADEON_CMD_PACKET:
Linus Torvalds1da177e2005-04-16 15:20:36 -07002926 DRM_DEBUG("RADEON_CMD_PACKET\n");
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002927 if (radeon_emit_packets
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002928 (dev_priv, file_priv, *header, cmdbuf)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002929 DRM_ERROR("radeon_emit_packets failed\n");
2930 goto err;
2931 }
2932 break;
2933
2934 case RADEON_CMD_SCALARS:
2935 DRM_DEBUG("RADEON_CMD_SCALARS\n");
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002936 if (radeon_emit_scalars(dev_priv, *header, cmdbuf)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002937 DRM_ERROR("radeon_emit_scalars failed\n");
2938 goto err;
2939 }
2940 break;
2941
2942 case RADEON_CMD_VECTORS:
2943 DRM_DEBUG("RADEON_CMD_VECTORS\n");
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002944 if (radeon_emit_vectors(dev_priv, *header, cmdbuf)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002945 DRM_ERROR("radeon_emit_vectors failed\n");
2946 goto err;
2947 }
2948 break;
2949
2950 case RADEON_CMD_DMA_DISCARD:
2951 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002952 idx = header->dma.buf_idx;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002953 if (idx < 0 || idx >= dma->buf_count) {
2954 DRM_ERROR("buffer index %d (of %d max)\n",
2955 idx, dma->buf_count - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002956 goto err;
2957 }
2958
2959 buf = dma->buflist[idx];
Eric Anholt6c340ea2007-08-25 20:23:09 +10002960 if (buf->file_priv != file_priv || buf->pending) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002961 DRM_ERROR("bad buffer %p %p %d\n",
Eric Anholt6c340ea2007-08-25 20:23:09 +10002962 buf->file_priv, file_priv,
2963 buf->pending);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002964 goto err;
2965 }
2966
Dave Airlie7c1c2872008-11-28 14:22:24 +10002967 radeon_cp_discard_buffer(dev, file_priv->master, buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002968 break;
2969
2970 case RADEON_CMD_PACKET3:
2971 DRM_DEBUG("RADEON_CMD_PACKET3\n");
Eric Anholtc153f452007-09-03 12:06:45 +10002972 if (radeon_emit_packet3(dev, file_priv, cmdbuf)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002973 DRM_ERROR("radeon_emit_packet3 failed\n");
2974 goto err;
2975 }
2976 break;
2977
2978 case RADEON_CMD_PACKET3_CLIP:
2979 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002980 if (radeon_emit_packet3_cliprect
Eric Anholtc153f452007-09-03 12:06:45 +10002981 (dev, file_priv, cmdbuf, orig_nbox)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002982 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2983 goto err;
2984 }
2985 break;
2986
2987 case RADEON_CMD_SCALARS2:
2988 DRM_DEBUG("RADEON_CMD_SCALARS2\n");
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002989 if (radeon_emit_scalars2(dev_priv, *header, cmdbuf)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002990 DRM_ERROR("radeon_emit_scalars2 failed\n");
2991 goto err;
2992 }
2993 break;
2994
2995 case RADEON_CMD_WAIT:
2996 DRM_DEBUG("RADEON_CMD_WAIT\n");
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02002997 if (radeon_emit_wait(dev, header->wait.flags)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002998 DRM_ERROR("radeon_emit_wait failed\n");
2999 goto err;
3000 }
3001 break;
Dave Airlied6fece02006-06-24 17:04:07 +10003002 case RADEON_CMD_VECLINEAR:
3003 DRM_DEBUG("RADEON_CMD_VECLINEAR\n");
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02003004 if (radeon_emit_veclinear(dev_priv, *header, cmdbuf)) {
Dave Airlied6fece02006-06-24 17:04:07 +10003005 DRM_ERROR("radeon_emit_veclinear failed\n");
3006 goto err;
3007 }
3008 break;
3009
Linus Torvalds1da177e2005-04-16 15:20:36 -07003010 default:
Pauli Nieminenb4fe9452010-02-01 19:11:16 +02003011 DRM_ERROR("bad cmd_type %d at byte %d\n",
3012 header->header.cmd_type,
3013 cmdbuf->buffer->iterator);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003014 goto err;
3015 }
3016 }
3017
Jean Delvarec9ff04c2010-05-11 14:01:45 +10003018 drm_buffer_free(cmdbuf->buffer);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003019
Jean Delvarec9ff04c2010-05-11 14:01:45 +10003020 done:
Linus Torvalds1da177e2005-04-16 15:20:36 -07003021 DRM_DEBUG("DONE\n");
3022 COMMIT_RING();
3023 return 0;
3024
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003025 err:
Jean Delvarec9ff04c2010-05-11 14:01:45 +10003026 drm_buffer_free(cmdbuf->buffer);
Eric Anholt20caafa2007-08-25 19:22:43 +10003027 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003028}
3029
Eric Anholtc153f452007-09-03 12:06:45 +10003030static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003031{
Linus Torvalds1da177e2005-04-16 15:20:36 -07003032 drm_radeon_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10003033 drm_radeon_getparam_t *param = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003034 int value;
3035
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003036 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003037
Eric Anholtc153f452007-09-03 12:06:45 +10003038 switch (param->param) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003039 case RADEON_PARAM_GART_BUFFER_OFFSET:
3040 value = dev_priv->gart_buffers_offset;
3041 break;
3042 case RADEON_PARAM_LAST_FRAME:
3043 dev_priv->stats.last_frame_reads++;
David Millerb07fa022009-02-12 02:15:37 -08003044 value = GET_SCRATCH(dev_priv, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003045 break;
3046 case RADEON_PARAM_LAST_DISPATCH:
David Millerb07fa022009-02-12 02:15:37 -08003047 value = GET_SCRATCH(dev_priv, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003048 break;
3049 case RADEON_PARAM_LAST_CLEAR:
3050 dev_priv->stats.last_clear_reads++;
David Millerb07fa022009-02-12 02:15:37 -08003051 value = GET_SCRATCH(dev_priv, 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003052 break;
3053 case RADEON_PARAM_IRQ_NR:
Alex Deucherb15591f2009-09-17 14:25:12 -04003054 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3055 value = 0;
3056 else
3057 value = drm_dev_to_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003058 break;
3059 case RADEON_PARAM_GART_BASE:
3060 value = dev_priv->gart_vm_start;
3061 break;
3062 case RADEON_PARAM_REGISTER_HANDLE:
Dave Airlied985c102006-01-02 21:32:48 +11003063 value = dev_priv->mmio->offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003064 break;
3065 case RADEON_PARAM_STATUS_HANDLE:
3066 value = dev_priv->ring_rptr_offset;
3067 break;
3068#if BITS_PER_LONG == 32
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003069 /*
3070 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
3071 * pointer which can't fit into an int-sized variable. According to
Jan Engelhardt96de0e22007-10-19 23:21:04 +02003072 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003073 * not supporting it shouldn't be a problem. If the same functionality
3074 * is needed on 64-bit platforms, a new ioctl() would have to be added,
3075 * so backwards-compatibility for the embedded platforms can be
3076 * maintained. --davidm 4-Feb-2004.
3077 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003078 case RADEON_PARAM_SAREA_HANDLE:
3079 /* The lock is the first dword in the sarea. */
Dave Airlie7c1c2872008-11-28 14:22:24 +10003080 /* no users of this parameter */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003081 break;
3082#endif
3083 case RADEON_PARAM_GART_TEX_HANDLE:
3084 value = dev_priv->gart_textures_offset;
3085 break;
Michel Dänzer8624ecb2006-08-07 20:33:57 +10003086 case RADEON_PARAM_SCRATCH_OFFSET:
3087 if (!dev_priv->writeback_works)
Eric Anholt20caafa2007-08-25 19:22:43 +10003088 return -EINVAL;
Alex Deucherc05ce082009-02-24 16:22:29 -05003089 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3090 value = R600_SCRATCH_REG_OFFSET;
3091 else
3092 value = RADEON_SCRATCH_REG_OFFSET;
Michel Dänzer8624ecb2006-08-07 20:33:57 +10003093 break;
Dave Airlied985c102006-01-02 21:32:48 +11003094 case RADEON_PARAM_CARD_TYPE:
Dave Airlie54a56ac2006-09-22 04:25:09 +10003095 if (dev_priv->flags & RADEON_IS_PCIE)
Dave Airlied985c102006-01-02 21:32:48 +11003096 value = RADEON_CARD_PCIE;
Dave Airlie54a56ac2006-09-22 04:25:09 +10003097 else if (dev_priv->flags & RADEON_IS_AGP)
Dave Airlied985c102006-01-02 21:32:48 +11003098 value = RADEON_CARD_AGP;
3099 else
3100 value = RADEON_CARD_PCI;
3101 break;
Dave Airlieddbee332007-07-11 12:16:01 +10003102 case RADEON_PARAM_VBLANK_CRTC:
3103 value = radeon_vblank_crtc_get(dev);
3104 break;
Dave Airlie3d5e2c12008-02-07 15:01:05 +10003105 case RADEON_PARAM_FB_LOCATION:
3106 value = radeon_read_fb_location(dev_priv);
3107 break;
Alex Deucher5b92c402008-05-28 11:57:40 +10003108 case RADEON_PARAM_NUM_GB_PIPES:
3109 value = dev_priv->num_gb_pipes;
3110 break;
Alex Deucherf779b3e2009-08-19 19:11:39 -04003111 case RADEON_PARAM_NUM_Z_PIPES:
3112 value = dev_priv->num_z_pipes;
3113 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003114 default:
Eric Anholtc153f452007-09-03 12:06:45 +10003115 DRM_DEBUG("Invalid parameter %d\n", param->param);
Eric Anholt20caafa2007-08-25 19:22:43 +10003116 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003117 }
3118
Eric Anholtc153f452007-09-03 12:06:45 +10003119 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003120 DRM_ERROR("copy_to_user\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10003121 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003122 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003123
Linus Torvalds1da177e2005-04-16 15:20:36 -07003124 return 0;
3125}
3126
Eric Anholtc153f452007-09-03 12:06:45 +10003127static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003128{
Linus Torvalds1da177e2005-04-16 15:20:36 -07003129 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10003130 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
Eric Anholtc153f452007-09-03 12:06:45 +10003131 drm_radeon_setparam_t *sp = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003132 struct drm_radeon_driver_file_fields *radeon_priv;
3133
Eric Anholtc153f452007-09-03 12:06:45 +10003134 switch (sp->param) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003135 case RADEON_SETPARAM_FB_LOCATION:
Eric Anholt6c340ea2007-08-25 20:23:09 +10003136 radeon_priv = file_priv->driver_priv;
Eric Anholtc153f452007-09-03 12:06:45 +10003137 radeon_priv->radeon_fb_delta = dev_priv->fb_location -
3138 sp->value;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003139 break;
3140 case RADEON_SETPARAM_SWITCH_TILING:
Eric Anholtc153f452007-09-03 12:06:45 +10003141 if (sp->value == 0) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003142 DRM_DEBUG("color tiling disabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003143 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3144 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
Dave Airlie7c1c2872008-11-28 14:22:24 +10003145 if (master_priv->sarea_priv)
3146 master_priv->sarea_priv->tiling_enabled = 0;
Eric Anholtc153f452007-09-03 12:06:45 +10003147 } else if (sp->value == 1) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003148 DRM_DEBUG("color tiling enabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003149 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3150 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
Dave Airlie7c1c2872008-11-28 14:22:24 +10003151 if (master_priv->sarea_priv)
3152 master_priv->sarea_priv->tiling_enabled = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003153 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003154 break;
Dave Airlieea98a922005-09-11 20:28:11 +10003155 case RADEON_SETPARAM_PCIGART_LOCATION:
Eric Anholtc153f452007-09-03 12:06:45 +10003156 dev_priv->pcigart_offset = sp->value;
Dave Airlief2b04cd2007-05-08 15:19:23 +10003157 dev_priv->pcigart_offset_set = 1;
Dave Airlieea98a922005-09-11 20:28:11 +10003158 break;
Dave Airlied5ea7022006-03-19 19:37:55 +11003159 case RADEON_SETPARAM_NEW_MEMMAP:
Eric Anholtc153f452007-09-03 12:06:45 +10003160 dev_priv->new_memmap = sp->value;
Dave Airlied5ea7022006-03-19 19:37:55 +11003161 break;
Dave Airlief2b04cd2007-05-08 15:19:23 +10003162 case RADEON_SETPARAM_PCIGART_TABLE_SIZE:
Eric Anholtc153f452007-09-03 12:06:45 +10003163 dev_priv->gart_info.table_size = sp->value;
Dave Airlief2b04cd2007-05-08 15:19:23 +10003164 if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
3165 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
3166 break;
Dave Airlieddbee332007-07-11 12:16:01 +10003167 case RADEON_SETPARAM_VBLANK_CRTC:
Eric Anholtc153f452007-09-03 12:06:45 +10003168 return radeon_vblank_crtc_set(dev, sp->value);
Dave Airlieddbee332007-07-11 12:16:01 +10003169 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003170 default:
Eric Anholtc153f452007-09-03 12:06:45 +10003171 DRM_DEBUG("Invalid parameter %d\n", sp->param);
Eric Anholt20caafa2007-08-25 19:22:43 +10003172 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003173 }
3174
3175 return 0;
3176}
3177
3178/* When a client dies:
3179 * - Check for and clean up flipped page state
3180 * - Free any alloced GART memory.
Dave Airlied985c102006-01-02 21:32:48 +11003181 * - Free any alloced radeon surfaces.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003182 *
3183 * DRM infrastructure takes care of reclaiming dma buffers.
3184 */
Eric Anholt6c340ea2007-08-25 20:23:09 +10003185void radeon_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003186{
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003187 if (dev->dev_private) {
3188 drm_radeon_private_t *dev_priv = dev->dev_private;
Michel Dänzer453ff942007-05-08 15:21:14 +10003189 dev_priv->page_flipping = 0;
Eric Anholt6c340ea2007-08-25 20:23:09 +10003190 radeon_mem_release(file_priv, dev_priv->gart_heap);
3191 radeon_mem_release(file_priv, dev_priv->fb_heap);
3192 radeon_surfaces_release(file_priv, dev_priv);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003193 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003194}
3195
Dave Airlie84b1fd12007-07-11 15:53:27 +10003196void radeon_driver_lastclose(struct drm_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003197{
David Miller6abf6bb2009-02-14 01:51:07 -08003198 radeon_surfaces_release(PCIGART_FILE_PRIV, dev->dev_private);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003199 radeon_do_release(dev);
3200}
3201
Eric Anholt6c340ea2007-08-25 20:23:09 +10003202int radeon_driver_open(struct drm_device *dev, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003203{
3204 drm_radeon_private_t *dev_priv = dev->dev_private;
3205 struct drm_radeon_driver_file_fields *radeon_priv;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003206
Dave Airlied985c102006-01-02 21:32:48 +11003207 DRM_DEBUG("\n");
Eric Anholt9a298b22009-03-24 12:23:04 -07003208 radeon_priv = kmalloc(sizeof(*radeon_priv), GFP_KERNEL);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003209
Linus Torvalds1da177e2005-04-16 15:20:36 -07003210 if (!radeon_priv)
3211 return -ENOMEM;
3212
Eric Anholt6c340ea2007-08-25 20:23:09 +10003213 file_priv->driver_priv = radeon_priv;
Dave Airlied985c102006-01-02 21:32:48 +11003214
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003215 if (dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003216 radeon_priv->radeon_fb_delta = dev_priv->fb_location;
3217 else
3218 radeon_priv->radeon_fb_delta = 0;
3219 return 0;
3220}
3221
Eric Anholt6c340ea2007-08-25 20:23:09 +10003222void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003223{
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003224 struct drm_radeon_driver_file_fields *radeon_priv =
Eric Anholt6c340ea2007-08-25 20:23:09 +10003225 file_priv->driver_priv;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10003226
Eric Anholt9a298b22009-03-24 12:23:04 -07003227 kfree(radeon_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003228}
3229
Eric Anholtc153f452007-09-03 12:06:45 +10003230struct drm_ioctl_desc radeon_ioctls[] = {
Dave Airlie1b2f1482010-08-14 20:20:34 +10003231 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3232 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3233 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3234 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3235 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH),
3236 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH),
3237 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset, DRM_AUTH),
3238 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH),
3239 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap, DRM_AUTH),
3240 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear, DRM_AUTH),
3241 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH),
3242 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices, DRM_AUTH),
3243 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH),
3244 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH),
3245 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3246 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH),
3247 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH),
3248 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH),
3249 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip, DRM_AUTH),
3250 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH),
3251 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free, DRM_AUTH),
3252 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3253 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH),
3254 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
3255 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
3256 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
3257 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH),
3258 DRM_IOCTL_DEF_DRV(RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003259};
3260
3261int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);