Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 1 | /* |
| 2 | * drivers/mmc/host/omap_hsmmc.c |
| 3 | * |
| 4 | * Driver for OMAP2430/3430 MMC controller. |
| 5 | * |
| 6 | * Copyright (C) 2007 Texas Instruments. |
| 7 | * |
| 8 | * Authors: |
| 9 | * Syed Mohammed Khasim <x0khasim@ti.com> |
| 10 | * Madhusudhan <madhu.cr@ti.com> |
| 11 | * Mohit Jalori <mjalori@ti.com> |
| 12 | * |
| 13 | * This file is licensed under the terms of the GNU General Public License |
| 14 | * version 2. This program is licensed "as is" without any warranty of any |
| 15 | * kind, whether express or implied. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/dma-mapping.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/workqueue.h> |
| 25 | #include <linux/timer.h> |
| 26 | #include <linux/clk.h> |
| 27 | #include <linux/mmc/host.h> |
| 28 | #include <linux/io.h> |
| 29 | #include <linux/semaphore.h> |
| 30 | #include <mach/dma.h> |
| 31 | #include <mach/hardware.h> |
| 32 | #include <mach/board.h> |
| 33 | #include <mach/mmc.h> |
| 34 | #include <mach/cpu.h> |
| 35 | |
| 36 | /* OMAP HSMMC Host Controller Registers */ |
| 37 | #define OMAP_HSMMC_SYSCONFIG 0x0010 |
| 38 | #define OMAP_HSMMC_CON 0x002C |
| 39 | #define OMAP_HSMMC_BLK 0x0104 |
| 40 | #define OMAP_HSMMC_ARG 0x0108 |
| 41 | #define OMAP_HSMMC_CMD 0x010C |
| 42 | #define OMAP_HSMMC_RSP10 0x0110 |
| 43 | #define OMAP_HSMMC_RSP32 0x0114 |
| 44 | #define OMAP_HSMMC_RSP54 0x0118 |
| 45 | #define OMAP_HSMMC_RSP76 0x011C |
| 46 | #define OMAP_HSMMC_DATA 0x0120 |
| 47 | #define OMAP_HSMMC_HCTL 0x0128 |
| 48 | #define OMAP_HSMMC_SYSCTL 0x012C |
| 49 | #define OMAP_HSMMC_STAT 0x0130 |
| 50 | #define OMAP_HSMMC_IE 0x0134 |
| 51 | #define OMAP_HSMMC_ISE 0x0138 |
| 52 | #define OMAP_HSMMC_CAPA 0x0140 |
| 53 | |
| 54 | #define VS18 (1 << 26) |
| 55 | #define VS30 (1 << 25) |
| 56 | #define SDVS18 (0x5 << 9) |
| 57 | #define SDVS30 (0x6 << 9) |
David Brownell | eb25082 | 2009-02-17 14:49:01 -0800 | [diff] [blame] | 58 | #define SDVS33 (0x7 << 9) |
Kim Kyuwon | 1b331e6 | 2009-02-20 13:10:08 +0100 | [diff] [blame^] | 59 | #define SDVS_MASK 0x00000E00 |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 60 | #define SDVSCLR 0xFFFFF1FF |
| 61 | #define SDVSDET 0x00000400 |
| 62 | #define AUTOIDLE 0x1 |
| 63 | #define SDBP (1 << 8) |
| 64 | #define DTO 0xe |
| 65 | #define ICE 0x1 |
| 66 | #define ICS 0x2 |
| 67 | #define CEN (1 << 2) |
| 68 | #define CLKD_MASK 0x0000FFC0 |
| 69 | #define CLKD_SHIFT 6 |
| 70 | #define DTO_MASK 0x000F0000 |
| 71 | #define DTO_SHIFT 16 |
| 72 | #define INT_EN_MASK 0x307F0033 |
| 73 | #define INIT_STREAM (1 << 1) |
| 74 | #define DP_SELECT (1 << 21) |
| 75 | #define DDIR (1 << 4) |
| 76 | #define DMA_EN 0x1 |
| 77 | #define MSBS (1 << 5) |
| 78 | #define BCE (1 << 1) |
| 79 | #define FOUR_BIT (1 << 1) |
| 80 | #define CC 0x1 |
| 81 | #define TC 0x02 |
| 82 | #define OD 0x1 |
| 83 | #define ERR (1 << 15) |
| 84 | #define CMD_TIMEOUT (1 << 16) |
| 85 | #define DATA_TIMEOUT (1 << 20) |
| 86 | #define CMD_CRC (1 << 17) |
| 87 | #define DATA_CRC (1 << 21) |
| 88 | #define CARD_ERR (1 << 28) |
| 89 | #define STAT_CLEAR 0xFFFFFFFF |
| 90 | #define INIT_STREAM_CMD 0x00000000 |
| 91 | #define DUAL_VOLT_OCR_BIT 7 |
| 92 | #define SRC (1 << 25) |
| 93 | #define SRD (1 << 26) |
| 94 | |
| 95 | /* |
| 96 | * FIXME: Most likely all the data using these _DEVID defines should come |
| 97 | * from the platform_data, or implemented in controller and slot specific |
| 98 | * functions. |
| 99 | */ |
| 100 | #define OMAP_MMC1_DEVID 0 |
| 101 | #define OMAP_MMC2_DEVID 1 |
| 102 | |
| 103 | #define OMAP_MMC_DATADIR_NONE 0 |
| 104 | #define OMAP_MMC_DATADIR_READ 1 |
| 105 | #define OMAP_MMC_DATADIR_WRITE 2 |
| 106 | #define MMC_TIMEOUT_MS 20 |
| 107 | #define OMAP_MMC_MASTER_CLOCK 96000000 |
| 108 | #define DRIVER_NAME "mmci-omap-hs" |
| 109 | |
| 110 | /* |
| 111 | * One controller can have multiple slots, like on some omap boards using |
| 112 | * omap.c controller driver. Luckily this is not currently done on any known |
| 113 | * omap_hsmmc.c device. |
| 114 | */ |
| 115 | #define mmc_slot(host) (host->pdata->slots[host->slot_id]) |
| 116 | |
| 117 | /* |
| 118 | * MMC Host controller read/write API's |
| 119 | */ |
| 120 | #define OMAP_HSMMC_READ(base, reg) \ |
| 121 | __raw_readl((base) + OMAP_HSMMC_##reg) |
| 122 | |
| 123 | #define OMAP_HSMMC_WRITE(base, reg, val) \ |
| 124 | __raw_writel((val), (base) + OMAP_HSMMC_##reg) |
| 125 | |
| 126 | struct mmc_omap_host { |
| 127 | struct device *dev; |
| 128 | struct mmc_host *mmc; |
| 129 | struct mmc_request *mrq; |
| 130 | struct mmc_command *cmd; |
| 131 | struct mmc_data *data; |
| 132 | struct clk *fclk; |
| 133 | struct clk *iclk; |
| 134 | struct clk *dbclk; |
| 135 | struct semaphore sem; |
| 136 | struct work_struct mmc_carddetect_work; |
| 137 | void __iomem *base; |
| 138 | resource_size_t mapbase; |
| 139 | unsigned int id; |
| 140 | unsigned int dma_len; |
| 141 | unsigned int dma_dir; |
| 142 | unsigned char bus_mode; |
| 143 | unsigned char datadir; |
| 144 | u32 *buffer; |
| 145 | u32 bytesleft; |
| 146 | int suspended; |
| 147 | int irq; |
| 148 | int carddetect; |
| 149 | int use_dma, dma_ch; |
| 150 | int initstr; |
| 151 | int slot_id; |
| 152 | int dbclk_enabled; |
| 153 | struct omap_mmc_platform_data *pdata; |
| 154 | }; |
| 155 | |
| 156 | /* |
| 157 | * Stop clock to the card |
| 158 | */ |
| 159 | static void omap_mmc_stop_clock(struct mmc_omap_host *host) |
| 160 | { |
| 161 | OMAP_HSMMC_WRITE(host->base, SYSCTL, |
| 162 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); |
| 163 | if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) |
| 164 | dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); |
| 165 | } |
| 166 | |
| 167 | /* |
| 168 | * Send init stream sequence to card |
| 169 | * before sending IDLE command |
| 170 | */ |
| 171 | static void send_init_stream(struct mmc_omap_host *host) |
| 172 | { |
| 173 | int reg = 0; |
| 174 | unsigned long timeout; |
| 175 | |
| 176 | disable_irq(host->irq); |
| 177 | OMAP_HSMMC_WRITE(host->base, CON, |
| 178 | OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); |
| 179 | OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); |
| 180 | |
| 181 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); |
| 182 | while ((reg != CC) && time_before(jiffies, timeout)) |
| 183 | reg = OMAP_HSMMC_READ(host->base, STAT) & CC; |
| 184 | |
| 185 | OMAP_HSMMC_WRITE(host->base, CON, |
| 186 | OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); |
| 187 | enable_irq(host->irq); |
| 188 | } |
| 189 | |
| 190 | static inline |
| 191 | int mmc_omap_cover_is_closed(struct mmc_omap_host *host) |
| 192 | { |
| 193 | int r = 1; |
| 194 | |
| 195 | if (host->pdata->slots[host->slot_id].get_cover_state) |
| 196 | r = host->pdata->slots[host->slot_id].get_cover_state(host->dev, |
| 197 | host->slot_id); |
| 198 | return r; |
| 199 | } |
| 200 | |
| 201 | static ssize_t |
| 202 | mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr, |
| 203 | char *buf) |
| 204 | { |
| 205 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); |
| 206 | struct mmc_omap_host *host = mmc_priv(mmc); |
| 207 | |
| 208 | return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" : |
| 209 | "open"); |
| 210 | } |
| 211 | |
| 212 | static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL); |
| 213 | |
| 214 | static ssize_t |
| 215 | mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr, |
| 216 | char *buf) |
| 217 | { |
| 218 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); |
| 219 | struct mmc_omap_host *host = mmc_priv(mmc); |
| 220 | struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id]; |
| 221 | |
| 222 | return sprintf(buf, "slot:%s\n", slot.name); |
| 223 | } |
| 224 | |
| 225 | static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL); |
| 226 | |
| 227 | /* |
| 228 | * Configure the response type and send the cmd. |
| 229 | */ |
| 230 | static void |
| 231 | mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd, |
| 232 | struct mmc_data *data) |
| 233 | { |
| 234 | int cmdreg = 0, resptype = 0, cmdtype = 0; |
| 235 | |
| 236 | dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", |
| 237 | mmc_hostname(host->mmc), cmd->opcode, cmd->arg); |
| 238 | host->cmd = cmd; |
| 239 | |
| 240 | /* |
| 241 | * Clear status bits and enable interrupts |
| 242 | */ |
| 243 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
| 244 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); |
| 245 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); |
| 246 | |
| 247 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 248 | if (cmd->flags & MMC_RSP_136) |
| 249 | resptype = 1; |
| 250 | else |
| 251 | resptype = 2; |
| 252 | } |
| 253 | |
| 254 | /* |
| 255 | * Unlike OMAP1 controller, the cmdtype does not seem to be based on |
| 256 | * ac, bc, adtc, bcr. Only commands ending an open ended transfer need |
| 257 | * a val of 0x3, rest 0x0. |
| 258 | */ |
| 259 | if (cmd == host->mrq->stop) |
| 260 | cmdtype = 0x3; |
| 261 | |
| 262 | cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); |
| 263 | |
| 264 | if (data) { |
| 265 | cmdreg |= DP_SELECT | MSBS | BCE; |
| 266 | if (data->flags & MMC_DATA_READ) |
| 267 | cmdreg |= DDIR; |
| 268 | else |
| 269 | cmdreg &= ~(DDIR); |
| 270 | } |
| 271 | |
| 272 | if (host->use_dma) |
| 273 | cmdreg |= DMA_EN; |
| 274 | |
| 275 | OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); |
| 276 | OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); |
| 277 | } |
| 278 | |
| 279 | /* |
| 280 | * Notify the transfer complete to MMC core |
| 281 | */ |
| 282 | static void |
| 283 | mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data) |
| 284 | { |
| 285 | host->data = NULL; |
| 286 | |
| 287 | if (host->use_dma && host->dma_ch != -1) |
| 288 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, |
| 289 | host->dma_dir); |
| 290 | |
| 291 | host->datadir = OMAP_MMC_DATADIR_NONE; |
| 292 | |
| 293 | if (!data->error) |
| 294 | data->bytes_xfered += data->blocks * (data->blksz); |
| 295 | else |
| 296 | data->bytes_xfered = 0; |
| 297 | |
| 298 | if (!data->stop) { |
| 299 | host->mrq = NULL; |
| 300 | mmc_request_done(host->mmc, data->mrq); |
| 301 | return; |
| 302 | } |
| 303 | mmc_omap_start_command(host, data->stop, NULL); |
| 304 | } |
| 305 | |
| 306 | /* |
| 307 | * Notify the core about command completion |
| 308 | */ |
| 309 | static void |
| 310 | mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) |
| 311 | { |
| 312 | host->cmd = NULL; |
| 313 | |
| 314 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 315 | if (cmd->flags & MMC_RSP_136) { |
| 316 | /* response type 2 */ |
| 317 | cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); |
| 318 | cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); |
| 319 | cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); |
| 320 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); |
| 321 | } else { |
| 322 | /* response types 1, 1b, 3, 4, 5, 6 */ |
| 323 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); |
| 324 | } |
| 325 | } |
| 326 | if (host->data == NULL || cmd->error) { |
| 327 | host->mrq = NULL; |
| 328 | mmc_request_done(host->mmc, cmd->mrq); |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | /* |
| 333 | * DMA clean up for command errors |
| 334 | */ |
| 335 | static void mmc_dma_cleanup(struct mmc_omap_host *host) |
| 336 | { |
| 337 | host->data->error = -ETIMEDOUT; |
| 338 | |
| 339 | if (host->use_dma && host->dma_ch != -1) { |
| 340 | dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, |
| 341 | host->dma_dir); |
| 342 | omap_free_dma(host->dma_ch); |
| 343 | host->dma_ch = -1; |
| 344 | up(&host->sem); |
| 345 | } |
| 346 | host->data = NULL; |
| 347 | host->datadir = OMAP_MMC_DATADIR_NONE; |
| 348 | } |
| 349 | |
| 350 | /* |
| 351 | * Readable error output |
| 352 | */ |
| 353 | #ifdef CONFIG_MMC_DEBUG |
| 354 | static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status) |
| 355 | { |
| 356 | /* --- means reserved bit without definition at documentation */ |
| 357 | static const char *mmc_omap_status_bits[] = { |
| 358 | "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", |
| 359 | "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", |
| 360 | "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", |
| 361 | "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" |
| 362 | }; |
| 363 | char res[256]; |
| 364 | char *buf = res; |
| 365 | int len, i; |
| 366 | |
| 367 | len = sprintf(buf, "MMC IRQ 0x%x :", status); |
| 368 | buf += len; |
| 369 | |
| 370 | for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++) |
| 371 | if (status & (1 << i)) { |
| 372 | len = sprintf(buf, " %s", mmc_omap_status_bits[i]); |
| 373 | buf += len; |
| 374 | } |
| 375 | |
| 376 | dev_dbg(mmc_dev(host->mmc), "%s\n", res); |
| 377 | } |
| 378 | #endif /* CONFIG_MMC_DEBUG */ |
| 379 | |
Jean Pihet | 3ebf74b | 2009-02-06 16:42:51 +0100 | [diff] [blame] | 380 | /* |
| 381 | * MMC controller internal state machines reset |
| 382 | * |
| 383 | * Used to reset command or data internal state machines, using respectively |
| 384 | * SRC or SRD bit of SYSCTL register |
| 385 | * Can be called from interrupt context |
| 386 | */ |
| 387 | static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host, |
| 388 | unsigned long bit) |
| 389 | { |
| 390 | unsigned long i = 0; |
| 391 | unsigned long limit = (loops_per_jiffy * |
| 392 | msecs_to_jiffies(MMC_TIMEOUT_MS)); |
| 393 | |
| 394 | OMAP_HSMMC_WRITE(host->base, SYSCTL, |
| 395 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); |
| 396 | |
| 397 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && |
| 398 | (i++ < limit)) |
| 399 | cpu_relax(); |
| 400 | |
| 401 | if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) |
| 402 | dev_err(mmc_dev(host->mmc), |
| 403 | "Timeout waiting on controller reset in %s\n", |
| 404 | __func__); |
| 405 | } |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 406 | |
| 407 | /* |
| 408 | * MMC controller IRQ handler |
| 409 | */ |
| 410 | static irqreturn_t mmc_omap_irq(int irq, void *dev_id) |
| 411 | { |
| 412 | struct mmc_omap_host *host = dev_id; |
| 413 | struct mmc_data *data; |
| 414 | int end_cmd = 0, end_trans = 0, status; |
| 415 | |
| 416 | if (host->cmd == NULL && host->data == NULL) { |
| 417 | OMAP_HSMMC_WRITE(host->base, STAT, |
| 418 | OMAP_HSMMC_READ(host->base, STAT)); |
| 419 | return IRQ_HANDLED; |
| 420 | } |
| 421 | |
| 422 | data = host->data; |
| 423 | status = OMAP_HSMMC_READ(host->base, STAT); |
| 424 | dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); |
| 425 | |
| 426 | if (status & ERR) { |
| 427 | #ifdef CONFIG_MMC_DEBUG |
| 428 | mmc_omap_report_irq(host, status); |
| 429 | #endif |
| 430 | if ((status & CMD_TIMEOUT) || |
| 431 | (status & CMD_CRC)) { |
| 432 | if (host->cmd) { |
| 433 | if (status & CMD_TIMEOUT) { |
Jean Pihet | 3ebf74b | 2009-02-06 16:42:51 +0100 | [diff] [blame] | 434 | mmc_omap_reset_controller_fsm(host, SRC); |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 435 | host->cmd->error = -ETIMEDOUT; |
| 436 | } else { |
| 437 | host->cmd->error = -EILSEQ; |
| 438 | } |
| 439 | end_cmd = 1; |
| 440 | } |
Jean Pihet | c232f45 | 2009-02-11 13:11:39 -0800 | [diff] [blame] | 441 | if (host->data) { |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 442 | mmc_dma_cleanup(host); |
Jean Pihet | 3ebf74b | 2009-02-06 16:42:51 +0100 | [diff] [blame] | 443 | mmc_omap_reset_controller_fsm(host, SRD); |
Jean Pihet | c232f45 | 2009-02-11 13:11:39 -0800 | [diff] [blame] | 444 | } |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 445 | } |
| 446 | if ((status & DATA_TIMEOUT) || |
| 447 | (status & DATA_CRC)) { |
| 448 | if (host->data) { |
| 449 | if (status & DATA_TIMEOUT) |
| 450 | mmc_dma_cleanup(host); |
| 451 | else |
| 452 | host->data->error = -EILSEQ; |
Jean Pihet | 3ebf74b | 2009-02-06 16:42:51 +0100 | [diff] [blame] | 453 | mmc_omap_reset_controller_fsm(host, SRD); |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 454 | end_trans = 1; |
| 455 | } |
| 456 | } |
| 457 | if (status & CARD_ERR) { |
| 458 | dev_dbg(mmc_dev(host->mmc), |
| 459 | "Ignoring card err CMD%d\n", host->cmd->opcode); |
| 460 | if (host->cmd) |
| 461 | end_cmd = 1; |
| 462 | if (host->data) |
| 463 | end_trans = 1; |
| 464 | } |
| 465 | } |
| 466 | |
| 467 | OMAP_HSMMC_WRITE(host->base, STAT, status); |
| 468 | |
| 469 | if (end_cmd || (status & CC)) |
| 470 | mmc_omap_cmd_done(host, host->cmd); |
| 471 | if (end_trans || (status & TC)) |
| 472 | mmc_omap_xfer_done(host, data); |
| 473 | |
| 474 | return IRQ_HANDLED; |
| 475 | } |
| 476 | |
| 477 | /* |
David Brownell | eb25082 | 2009-02-17 14:49:01 -0800 | [diff] [blame] | 478 | * Switch MMC interface voltage ... only relevant for MMC1. |
| 479 | * |
| 480 | * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. |
| 481 | * The MMC2 transceiver controls are used instead of DAT4..DAT7. |
| 482 | * Some chips, like eMMC ones, use internal transceivers. |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 483 | */ |
| 484 | static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd) |
| 485 | { |
| 486 | u32 reg_val = 0; |
| 487 | int ret; |
| 488 | |
| 489 | /* Disable the clocks */ |
| 490 | clk_disable(host->fclk); |
| 491 | clk_disable(host->iclk); |
| 492 | clk_disable(host->dbclk); |
| 493 | |
| 494 | /* Turn the power off */ |
| 495 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); |
| 496 | if (ret != 0) |
| 497 | goto err; |
| 498 | |
| 499 | /* Turn the power ON with given VDD 1.8 or 3.0v */ |
| 500 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); |
| 501 | if (ret != 0) |
| 502 | goto err; |
| 503 | |
| 504 | clk_enable(host->fclk); |
| 505 | clk_enable(host->iclk); |
| 506 | clk_enable(host->dbclk); |
| 507 | |
| 508 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 509 | OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); |
| 510 | reg_val = OMAP_HSMMC_READ(host->base, HCTL); |
David Brownell | eb25082 | 2009-02-17 14:49:01 -0800 | [diff] [blame] | 511 | |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 512 | /* |
| 513 | * If a MMC dual voltage card is detected, the set_ios fn calls |
| 514 | * this fn with VDD bit set for 1.8V. Upon card removal from the |
| 515 | * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. |
| 516 | * |
David Brownell | eb25082 | 2009-02-17 14:49:01 -0800 | [diff] [blame] | 517 | * Cope with a bit of slop in the range ... per data sheets: |
| 518 | * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, |
| 519 | * but recommended values are 1.71V to 1.89V |
| 520 | * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, |
| 521 | * but recommended values are 2.7V to 3.3V |
| 522 | * |
| 523 | * Board setup code shouldn't permit anything very out-of-range. |
| 524 | * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the |
| 525 | * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 526 | */ |
David Brownell | eb25082 | 2009-02-17 14:49:01 -0800 | [diff] [blame] | 527 | if ((1 << vdd) <= MMC_VDD_23_24) |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 528 | reg_val |= SDVS18; |
David Brownell | eb25082 | 2009-02-17 14:49:01 -0800 | [diff] [blame] | 529 | else |
| 530 | reg_val |= SDVS30; |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 531 | |
| 532 | OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); |
| 533 | |
| 534 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 535 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); |
| 536 | |
| 537 | return 0; |
| 538 | err: |
| 539 | dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); |
| 540 | return ret; |
| 541 | } |
| 542 | |
| 543 | /* |
| 544 | * Work Item to notify the core about card insertion/removal |
| 545 | */ |
| 546 | static void mmc_omap_detect(struct work_struct *work) |
| 547 | { |
| 548 | struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, |
| 549 | mmc_carddetect_work); |
David Brownell | 249d0fa | 2009-02-04 14:42:03 -0800 | [diff] [blame] | 550 | struct omap_mmc_slot_data *slot = &mmc_slot(host); |
| 551 | |
| 552 | host->carddetect = slot->card_detect(slot->card_detect_irq); |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 553 | |
| 554 | sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); |
| 555 | if (host->carddetect) { |
| 556 | mmc_detect_change(host->mmc, (HZ * 200) / 1000); |
| 557 | } else { |
Jean Pihet | 3ebf74b | 2009-02-06 16:42:51 +0100 | [diff] [blame] | 558 | mmc_omap_reset_controller_fsm(host, SRD); |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 559 | mmc_detect_change(host->mmc, (HZ * 50) / 1000); |
| 560 | } |
| 561 | } |
| 562 | |
| 563 | /* |
| 564 | * ISR for handling card insertion and removal |
| 565 | */ |
| 566 | static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id) |
| 567 | { |
| 568 | struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id; |
| 569 | |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 570 | schedule_work(&host->mmc_carddetect_work); |
| 571 | |
| 572 | return IRQ_HANDLED; |
| 573 | } |
| 574 | |
| 575 | /* |
| 576 | * DMA call back function |
| 577 | */ |
| 578 | static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data) |
| 579 | { |
| 580 | struct mmc_omap_host *host = data; |
| 581 | |
| 582 | if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ) |
| 583 | dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n"); |
| 584 | |
| 585 | if (host->dma_ch < 0) |
| 586 | return; |
| 587 | |
| 588 | omap_free_dma(host->dma_ch); |
| 589 | host->dma_ch = -1; |
| 590 | /* |
| 591 | * DMA Callback: run in interrupt context. |
| 592 | * mutex_unlock will through a kernel warning if used. |
| 593 | */ |
| 594 | up(&host->sem); |
| 595 | } |
| 596 | |
| 597 | /* |
| 598 | * Configure dma src and destination parameters |
| 599 | */ |
| 600 | static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host, |
| 601 | struct mmc_data *data) |
| 602 | { |
| 603 | if (sync_dir == 0) { |
| 604 | omap_set_dma_dest_params(host->dma_ch, 0, |
| 605 | OMAP_DMA_AMODE_CONSTANT, |
| 606 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); |
| 607 | omap_set_dma_src_params(host->dma_ch, 0, |
| 608 | OMAP_DMA_AMODE_POST_INC, |
| 609 | sg_dma_address(&data->sg[0]), 0, 0); |
| 610 | } else { |
| 611 | omap_set_dma_src_params(host->dma_ch, 0, |
| 612 | OMAP_DMA_AMODE_CONSTANT, |
| 613 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); |
| 614 | omap_set_dma_dest_params(host->dma_ch, 0, |
| 615 | OMAP_DMA_AMODE_POST_INC, |
| 616 | sg_dma_address(&data->sg[0]), 0, 0); |
| 617 | } |
| 618 | return 0; |
| 619 | } |
| 620 | /* |
| 621 | * Routine to configure and start DMA for the MMC card |
| 622 | */ |
| 623 | static int |
| 624 | mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req) |
| 625 | { |
| 626 | int sync_dev, sync_dir = 0; |
| 627 | int dma_ch = 0, ret = 0, err = 1; |
| 628 | struct mmc_data *data = req->data; |
| 629 | |
| 630 | /* |
| 631 | * If for some reason the DMA transfer is still active, |
| 632 | * we wait for timeout period and free the dma |
| 633 | */ |
| 634 | if (host->dma_ch != -1) { |
| 635 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 636 | schedule_timeout(100); |
| 637 | if (down_trylock(&host->sem)) { |
| 638 | omap_free_dma(host->dma_ch); |
| 639 | host->dma_ch = -1; |
| 640 | up(&host->sem); |
| 641 | return err; |
| 642 | } |
| 643 | } else { |
| 644 | if (down_trylock(&host->sem)) |
| 645 | return err; |
| 646 | } |
| 647 | |
| 648 | if (!(data->flags & MMC_DATA_WRITE)) { |
| 649 | host->dma_dir = DMA_FROM_DEVICE; |
| 650 | if (host->id == OMAP_MMC1_DEVID) |
| 651 | sync_dev = OMAP24XX_DMA_MMC1_RX; |
| 652 | else |
| 653 | sync_dev = OMAP24XX_DMA_MMC2_RX; |
| 654 | } else { |
| 655 | host->dma_dir = DMA_TO_DEVICE; |
| 656 | if (host->id == OMAP_MMC1_DEVID) |
| 657 | sync_dev = OMAP24XX_DMA_MMC1_TX; |
| 658 | else |
| 659 | sync_dev = OMAP24XX_DMA_MMC2_TX; |
| 660 | } |
| 661 | |
| 662 | ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb, |
| 663 | host, &dma_ch); |
| 664 | if (ret != 0) { |
| 665 | dev_dbg(mmc_dev(host->mmc), |
| 666 | "%s: omap_request_dma() failed with %d\n", |
| 667 | mmc_hostname(host->mmc), ret); |
| 668 | return ret; |
| 669 | } |
| 670 | |
| 671 | host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, |
| 672 | data->sg_len, host->dma_dir); |
| 673 | host->dma_ch = dma_ch; |
| 674 | |
| 675 | if (!(data->flags & MMC_DATA_WRITE)) |
| 676 | mmc_omap_config_dma_param(1, host, data); |
| 677 | else |
| 678 | mmc_omap_config_dma_param(0, host, data); |
| 679 | |
| 680 | if ((data->blksz % 4) == 0) |
| 681 | omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, |
| 682 | (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME, |
| 683 | sync_dev, sync_dir); |
| 684 | else |
| 685 | /* REVISIT: The MMC buffer increments only when MSB is written. |
| 686 | * Return error for blksz which is non multiple of four. |
| 687 | */ |
| 688 | return -EINVAL; |
| 689 | |
| 690 | omap_start_dma(dma_ch); |
| 691 | return 0; |
| 692 | } |
| 693 | |
| 694 | static void set_data_timeout(struct mmc_omap_host *host, |
| 695 | struct mmc_request *req) |
| 696 | { |
| 697 | unsigned int timeout, cycle_ns; |
| 698 | uint32_t reg, clkd, dto = 0; |
| 699 | |
| 700 | reg = OMAP_HSMMC_READ(host->base, SYSCTL); |
| 701 | clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; |
| 702 | if (clkd == 0) |
| 703 | clkd = 1; |
| 704 | |
| 705 | cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); |
| 706 | timeout = req->data->timeout_ns / cycle_ns; |
| 707 | timeout += req->data->timeout_clks; |
| 708 | if (timeout) { |
| 709 | while ((timeout & 0x80000000) == 0) { |
| 710 | dto += 1; |
| 711 | timeout <<= 1; |
| 712 | } |
| 713 | dto = 31 - dto; |
| 714 | timeout <<= 1; |
| 715 | if (timeout && dto) |
| 716 | dto += 1; |
| 717 | if (dto >= 13) |
| 718 | dto -= 13; |
| 719 | else |
| 720 | dto = 0; |
| 721 | if (dto > 14) |
| 722 | dto = 14; |
| 723 | } |
| 724 | |
| 725 | reg &= ~DTO_MASK; |
| 726 | reg |= dto << DTO_SHIFT; |
| 727 | OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); |
| 728 | } |
| 729 | |
| 730 | /* |
| 731 | * Configure block length for MMC/SD cards and initiate the transfer. |
| 732 | */ |
| 733 | static int |
| 734 | mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) |
| 735 | { |
| 736 | int ret; |
| 737 | host->data = req->data; |
| 738 | |
| 739 | if (req->data == NULL) { |
| 740 | host->datadir = OMAP_MMC_DATADIR_NONE; |
| 741 | OMAP_HSMMC_WRITE(host->base, BLK, 0); |
| 742 | return 0; |
| 743 | } |
| 744 | |
| 745 | OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) |
| 746 | | (req->data->blocks << 16)); |
| 747 | set_data_timeout(host, req); |
| 748 | |
| 749 | host->datadir = (req->data->flags & MMC_DATA_WRITE) ? |
| 750 | OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ; |
| 751 | |
| 752 | if (host->use_dma) { |
| 753 | ret = mmc_omap_start_dma_transfer(host, req); |
| 754 | if (ret != 0) { |
| 755 | dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); |
| 756 | return ret; |
| 757 | } |
| 758 | } |
| 759 | return 0; |
| 760 | } |
| 761 | |
| 762 | /* |
| 763 | * Request function. for read/write operation |
| 764 | */ |
| 765 | static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req) |
| 766 | { |
| 767 | struct mmc_omap_host *host = mmc_priv(mmc); |
| 768 | |
| 769 | WARN_ON(host->mrq != NULL); |
| 770 | host->mrq = req; |
| 771 | mmc_omap_prepare_data(host, req); |
| 772 | mmc_omap_start_command(host, req->cmd, req->data); |
| 773 | } |
| 774 | |
| 775 | |
| 776 | /* Routine to configure clock values. Exposed API to core */ |
| 777 | static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 778 | { |
| 779 | struct mmc_omap_host *host = mmc_priv(mmc); |
| 780 | u16 dsor = 0; |
| 781 | unsigned long regval; |
| 782 | unsigned long timeout; |
| 783 | |
| 784 | switch (ios->power_mode) { |
| 785 | case MMC_POWER_OFF: |
| 786 | mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 787 | break; |
| 788 | case MMC_POWER_UP: |
| 789 | mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd); |
| 790 | break; |
| 791 | } |
| 792 | |
| 793 | switch (mmc->ios.bus_width) { |
| 794 | case MMC_BUS_WIDTH_4: |
| 795 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 796 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); |
| 797 | break; |
| 798 | case MMC_BUS_WIDTH_1: |
| 799 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 800 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); |
| 801 | break; |
| 802 | } |
| 803 | |
| 804 | if (host->id == OMAP_MMC1_DEVID) { |
David Brownell | eb25082 | 2009-02-17 14:49:01 -0800 | [diff] [blame] | 805 | /* Only MMC1 can interface at 3V without some flavor |
| 806 | * of external transceiver; but they all handle 1.8V. |
| 807 | */ |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 808 | if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && |
| 809 | (ios->vdd == DUAL_VOLT_OCR_BIT)) { |
| 810 | /* |
| 811 | * The mmc_select_voltage fn of the core does |
| 812 | * not seem to set the power_mode to |
| 813 | * MMC_POWER_UP upon recalculating the voltage. |
| 814 | * vdd 1.8v. |
| 815 | */ |
| 816 | if (omap_mmc_switch_opcond(host, ios->vdd) != 0) |
| 817 | dev_dbg(mmc_dev(host->mmc), |
| 818 | "Switch operation failed\n"); |
| 819 | } |
| 820 | } |
| 821 | |
| 822 | if (ios->clock) { |
| 823 | dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; |
| 824 | if (dsor < 1) |
| 825 | dsor = 1; |
| 826 | |
| 827 | if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) |
| 828 | dsor++; |
| 829 | |
| 830 | if (dsor > 250) |
| 831 | dsor = 250; |
| 832 | } |
| 833 | omap_mmc_stop_clock(host); |
| 834 | regval = OMAP_HSMMC_READ(host->base, SYSCTL); |
| 835 | regval = regval & ~(CLKD_MASK); |
| 836 | regval = regval | (dsor << 6) | (DTO << 16); |
| 837 | OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); |
| 838 | OMAP_HSMMC_WRITE(host->base, SYSCTL, |
| 839 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); |
| 840 | |
| 841 | /* Wait till the ICS bit is set */ |
| 842 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); |
| 843 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2 |
| 844 | && time_before(jiffies, timeout)) |
| 845 | msleep(1); |
| 846 | |
| 847 | OMAP_HSMMC_WRITE(host->base, SYSCTL, |
| 848 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); |
| 849 | |
| 850 | if (ios->power_mode == MMC_POWER_ON) |
| 851 | send_init_stream(host); |
| 852 | |
| 853 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) |
| 854 | OMAP_HSMMC_WRITE(host->base, CON, |
| 855 | OMAP_HSMMC_READ(host->base, CON) | OD); |
| 856 | } |
| 857 | |
| 858 | static int omap_hsmmc_get_cd(struct mmc_host *mmc) |
| 859 | { |
| 860 | struct mmc_omap_host *host = mmc_priv(mmc); |
| 861 | struct omap_mmc_platform_data *pdata = host->pdata; |
| 862 | |
| 863 | if (!pdata->slots[0].card_detect) |
| 864 | return -ENOSYS; |
| 865 | return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq); |
| 866 | } |
| 867 | |
| 868 | static int omap_hsmmc_get_ro(struct mmc_host *mmc) |
| 869 | { |
| 870 | struct mmc_omap_host *host = mmc_priv(mmc); |
| 871 | struct omap_mmc_platform_data *pdata = host->pdata; |
| 872 | |
| 873 | if (!pdata->slots[0].get_ro) |
| 874 | return -ENOSYS; |
| 875 | return pdata->slots[0].get_ro(host->dev, 0); |
| 876 | } |
| 877 | |
Kim Kyuwon | 1b331e6 | 2009-02-20 13:10:08 +0100 | [diff] [blame^] | 878 | static void omap_hsmmc_init(struct mmc_omap_host *host) |
| 879 | { |
| 880 | u32 hctl, capa, value; |
| 881 | |
| 882 | /* Only MMC1 supports 3.0V */ |
| 883 | if (host->id == OMAP_MMC1_DEVID) { |
| 884 | hctl = SDVS30; |
| 885 | capa = VS30 | VS18; |
| 886 | } else { |
| 887 | hctl = SDVS18; |
| 888 | capa = VS18; |
| 889 | } |
| 890 | |
| 891 | value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; |
| 892 | OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); |
| 893 | |
| 894 | value = OMAP_HSMMC_READ(host->base, CAPA); |
| 895 | OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); |
| 896 | |
| 897 | /* Set the controller to AUTO IDLE mode */ |
| 898 | value = OMAP_HSMMC_READ(host->base, SYSCONFIG); |
| 899 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); |
| 900 | |
| 901 | /* Set SD bus power bit */ |
| 902 | value = OMAP_HSMMC_READ(host->base, HCTL); |
| 903 | OMAP_HSMMC_WRITE(host->base, HCTL, value | SDBP); |
| 904 | } |
| 905 | |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 906 | static struct mmc_host_ops mmc_omap_ops = { |
| 907 | .request = omap_mmc_request, |
| 908 | .set_ios = omap_mmc_set_ios, |
| 909 | .get_cd = omap_hsmmc_get_cd, |
| 910 | .get_ro = omap_hsmmc_get_ro, |
| 911 | /* NYET -- enable_sdio_irq */ |
| 912 | }; |
| 913 | |
| 914 | static int __init omap_mmc_probe(struct platform_device *pdev) |
| 915 | { |
| 916 | struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; |
| 917 | struct mmc_host *mmc; |
| 918 | struct mmc_omap_host *host = NULL; |
| 919 | struct resource *res; |
| 920 | int ret = 0, irq; |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 921 | |
| 922 | if (pdata == NULL) { |
| 923 | dev_err(&pdev->dev, "Platform Data is missing\n"); |
| 924 | return -ENXIO; |
| 925 | } |
| 926 | |
| 927 | if (pdata->nr_slots == 0) { |
| 928 | dev_err(&pdev->dev, "No Slots\n"); |
| 929 | return -ENXIO; |
| 930 | } |
| 931 | |
| 932 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 933 | irq = platform_get_irq(pdev, 0); |
| 934 | if (res == NULL || irq < 0) |
| 935 | return -ENXIO; |
| 936 | |
| 937 | res = request_mem_region(res->start, res->end - res->start + 1, |
| 938 | pdev->name); |
| 939 | if (res == NULL) |
| 940 | return -EBUSY; |
| 941 | |
| 942 | mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev); |
| 943 | if (!mmc) { |
| 944 | ret = -ENOMEM; |
| 945 | goto err; |
| 946 | } |
| 947 | |
| 948 | host = mmc_priv(mmc); |
| 949 | host->mmc = mmc; |
| 950 | host->pdata = pdata; |
| 951 | host->dev = &pdev->dev; |
| 952 | host->use_dma = 1; |
| 953 | host->dev->dma_mask = &pdata->dma_mask; |
| 954 | host->dma_ch = -1; |
| 955 | host->irq = irq; |
| 956 | host->id = pdev->id; |
| 957 | host->slot_id = 0; |
| 958 | host->mapbase = res->start; |
| 959 | host->base = ioremap(host->mapbase, SZ_4K); |
| 960 | |
| 961 | platform_set_drvdata(pdev, host); |
| 962 | INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect); |
| 963 | |
| 964 | mmc->ops = &mmc_omap_ops; |
| 965 | mmc->f_min = 400000; |
| 966 | mmc->f_max = 52000000; |
| 967 | |
| 968 | sema_init(&host->sem, 1); |
| 969 | |
| 970 | host->iclk = clk_get(&pdev->dev, "mmchs_ick"); |
| 971 | if (IS_ERR(host->iclk)) { |
| 972 | ret = PTR_ERR(host->iclk); |
| 973 | host->iclk = NULL; |
| 974 | goto err1; |
| 975 | } |
| 976 | host->fclk = clk_get(&pdev->dev, "mmchs_fck"); |
| 977 | if (IS_ERR(host->fclk)) { |
| 978 | ret = PTR_ERR(host->fclk); |
| 979 | host->fclk = NULL; |
| 980 | clk_put(host->iclk); |
| 981 | goto err1; |
| 982 | } |
| 983 | |
| 984 | if (clk_enable(host->fclk) != 0) { |
| 985 | clk_put(host->iclk); |
| 986 | clk_put(host->fclk); |
| 987 | goto err1; |
| 988 | } |
| 989 | |
| 990 | if (clk_enable(host->iclk) != 0) { |
| 991 | clk_disable(host->fclk); |
| 992 | clk_put(host->iclk); |
| 993 | clk_put(host->fclk); |
| 994 | goto err1; |
| 995 | } |
| 996 | |
| 997 | host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); |
| 998 | /* |
| 999 | * MMC can still work without debounce clock. |
| 1000 | */ |
| 1001 | if (IS_ERR(host->dbclk)) |
| 1002 | dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n"); |
| 1003 | else |
| 1004 | if (clk_enable(host->dbclk) != 0) |
| 1005 | dev_dbg(mmc_dev(host->mmc), "Enabling debounce" |
| 1006 | " clk failed\n"); |
| 1007 | else |
| 1008 | host->dbclk_enabled = 1; |
| 1009 | |
| 1010 | #ifdef CONFIG_MMC_BLOCK_BOUNCE |
| 1011 | mmc->max_phys_segs = 1; |
| 1012 | mmc->max_hw_segs = 1; |
| 1013 | #endif |
| 1014 | mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ |
| 1015 | mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ |
| 1016 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; |
| 1017 | mmc->max_seg_size = mmc->max_req_size; |
| 1018 | |
| 1019 | mmc->ocr_avail = mmc_slot(host).ocr_mask; |
| 1020 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED; |
| 1021 | |
| 1022 | if (pdata->slots[host->slot_id].wires >= 4) |
| 1023 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
| 1024 | |
Kim Kyuwon | 1b331e6 | 2009-02-20 13:10:08 +0100 | [diff] [blame^] | 1025 | omap_hsmmc_init(host); |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 1026 | |
| 1027 | /* Request IRQ for MMC operations */ |
| 1028 | ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, |
| 1029 | mmc_hostname(mmc), host); |
| 1030 | if (ret) { |
| 1031 | dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); |
| 1032 | goto err_irq; |
| 1033 | } |
| 1034 | |
| 1035 | if (pdata->init != NULL) { |
| 1036 | if (pdata->init(&pdev->dev) != 0) { |
| 1037 | dev_dbg(mmc_dev(host->mmc), |
| 1038 | "Unable to configure MMC IRQs\n"); |
| 1039 | goto err_irq_cd_init; |
| 1040 | } |
| 1041 | } |
| 1042 | |
| 1043 | /* Request IRQ for card detect */ |
| 1044 | if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) { |
| 1045 | ret = request_irq(mmc_slot(host).card_detect_irq, |
| 1046 | omap_mmc_cd_handler, |
| 1047 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
| 1048 | | IRQF_DISABLED, |
| 1049 | mmc_hostname(mmc), host); |
| 1050 | if (ret) { |
| 1051 | dev_dbg(mmc_dev(host->mmc), |
| 1052 | "Unable to grab MMC CD IRQ\n"); |
| 1053 | goto err_irq_cd; |
| 1054 | } |
| 1055 | } |
| 1056 | |
| 1057 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); |
| 1058 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); |
| 1059 | |
| 1060 | mmc_add_host(mmc); |
| 1061 | |
| 1062 | if (host->pdata->slots[host->slot_id].name != NULL) { |
| 1063 | ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); |
| 1064 | if (ret < 0) |
| 1065 | goto err_slot_name; |
| 1066 | } |
| 1067 | if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect && |
| 1068 | host->pdata->slots[host->slot_id].get_cover_state) { |
| 1069 | ret = device_create_file(&mmc->class_dev, |
| 1070 | &dev_attr_cover_switch); |
| 1071 | if (ret < 0) |
| 1072 | goto err_cover_switch; |
| 1073 | } |
| 1074 | |
| 1075 | return 0; |
| 1076 | |
| 1077 | err_cover_switch: |
| 1078 | device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); |
| 1079 | err_slot_name: |
| 1080 | mmc_remove_host(mmc); |
| 1081 | err_irq_cd: |
| 1082 | free_irq(mmc_slot(host).card_detect_irq, host); |
| 1083 | err_irq_cd_init: |
| 1084 | free_irq(host->irq, host); |
| 1085 | err_irq: |
| 1086 | clk_disable(host->fclk); |
| 1087 | clk_disable(host->iclk); |
| 1088 | clk_put(host->fclk); |
| 1089 | clk_put(host->iclk); |
| 1090 | if (host->dbclk_enabled) { |
| 1091 | clk_disable(host->dbclk); |
| 1092 | clk_put(host->dbclk); |
| 1093 | } |
| 1094 | |
| 1095 | err1: |
| 1096 | iounmap(host->base); |
| 1097 | err: |
| 1098 | dev_dbg(mmc_dev(host->mmc), "Probe Failed\n"); |
| 1099 | release_mem_region(res->start, res->end - res->start + 1); |
| 1100 | if (host) |
| 1101 | mmc_free_host(mmc); |
| 1102 | return ret; |
| 1103 | } |
| 1104 | |
| 1105 | static int omap_mmc_remove(struct platform_device *pdev) |
| 1106 | { |
| 1107 | struct mmc_omap_host *host = platform_get_drvdata(pdev); |
| 1108 | struct resource *res; |
| 1109 | |
| 1110 | if (host) { |
| 1111 | mmc_remove_host(host->mmc); |
| 1112 | if (host->pdata->cleanup) |
| 1113 | host->pdata->cleanup(&pdev->dev); |
| 1114 | free_irq(host->irq, host); |
| 1115 | if (mmc_slot(host).card_detect_irq) |
| 1116 | free_irq(mmc_slot(host).card_detect_irq, host); |
| 1117 | flush_scheduled_work(); |
| 1118 | |
| 1119 | clk_disable(host->fclk); |
| 1120 | clk_disable(host->iclk); |
| 1121 | clk_put(host->fclk); |
| 1122 | clk_put(host->iclk); |
| 1123 | if (host->dbclk_enabled) { |
| 1124 | clk_disable(host->dbclk); |
| 1125 | clk_put(host->dbclk); |
| 1126 | } |
| 1127 | |
| 1128 | mmc_free_host(host->mmc); |
| 1129 | iounmap(host->base); |
| 1130 | } |
| 1131 | |
| 1132 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1133 | if (res) |
| 1134 | release_mem_region(res->start, res->end - res->start + 1); |
| 1135 | platform_set_drvdata(pdev, NULL); |
| 1136 | |
| 1137 | return 0; |
| 1138 | } |
| 1139 | |
| 1140 | #ifdef CONFIG_PM |
| 1141 | static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state) |
| 1142 | { |
| 1143 | int ret = 0; |
| 1144 | struct mmc_omap_host *host = platform_get_drvdata(pdev); |
| 1145 | |
| 1146 | if (host && host->suspended) |
| 1147 | return 0; |
| 1148 | |
| 1149 | if (host) { |
| 1150 | ret = mmc_suspend_host(host->mmc, state); |
| 1151 | if (ret == 0) { |
| 1152 | host->suspended = 1; |
| 1153 | |
| 1154 | OMAP_HSMMC_WRITE(host->base, ISE, 0); |
| 1155 | OMAP_HSMMC_WRITE(host->base, IE, 0); |
| 1156 | |
| 1157 | if (host->pdata->suspend) { |
| 1158 | ret = host->pdata->suspend(&pdev->dev, |
| 1159 | host->slot_id); |
| 1160 | if (ret) |
| 1161 | dev_dbg(mmc_dev(host->mmc), |
| 1162 | "Unable to handle MMC board" |
| 1163 | " level suspend\n"); |
| 1164 | } |
| 1165 | |
David Brownell | eb25082 | 2009-02-17 14:49:01 -0800 | [diff] [blame] | 1166 | if (host->id == OMAP_MMC1_DEVID |
| 1167 | && !(OMAP_HSMMC_READ(host->base, HCTL) |
| 1168 | & SDVSDET)) { |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 1169 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 1170 | OMAP_HSMMC_READ(host->base, HCTL) |
| 1171 | & SDVSCLR); |
| 1172 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 1173 | OMAP_HSMMC_READ(host->base, HCTL) |
| 1174 | | SDVS30); |
| 1175 | OMAP_HSMMC_WRITE(host->base, HCTL, |
| 1176 | OMAP_HSMMC_READ(host->base, HCTL) |
| 1177 | | SDBP); |
| 1178 | } |
| 1179 | |
| 1180 | clk_disable(host->fclk); |
| 1181 | clk_disable(host->iclk); |
| 1182 | clk_disable(host->dbclk); |
| 1183 | } |
| 1184 | |
| 1185 | } |
| 1186 | return ret; |
| 1187 | } |
| 1188 | |
| 1189 | /* Routine to resume the MMC device */ |
| 1190 | static int omap_mmc_resume(struct platform_device *pdev) |
| 1191 | { |
| 1192 | int ret = 0; |
| 1193 | struct mmc_omap_host *host = platform_get_drvdata(pdev); |
| 1194 | |
| 1195 | if (host && !host->suspended) |
| 1196 | return 0; |
| 1197 | |
| 1198 | if (host) { |
| 1199 | |
| 1200 | ret = clk_enable(host->fclk); |
| 1201 | if (ret) |
| 1202 | goto clk_en_err; |
| 1203 | |
| 1204 | ret = clk_enable(host->iclk); |
| 1205 | if (ret) { |
| 1206 | clk_disable(host->fclk); |
| 1207 | clk_put(host->fclk); |
| 1208 | goto clk_en_err; |
| 1209 | } |
| 1210 | |
| 1211 | if (clk_enable(host->dbclk) != 0) |
| 1212 | dev_dbg(mmc_dev(host->mmc), |
| 1213 | "Enabling debounce clk failed\n"); |
| 1214 | |
Kim Kyuwon | 1b331e6 | 2009-02-20 13:10:08 +0100 | [diff] [blame^] | 1215 | omap_hsmmc_init(host); |
| 1216 | |
Madhusudhan Chikkature | a45c6cb | 2009-01-23 01:05:23 +0100 | [diff] [blame] | 1217 | if (host->pdata->resume) { |
| 1218 | ret = host->pdata->resume(&pdev->dev, host->slot_id); |
| 1219 | if (ret) |
| 1220 | dev_dbg(mmc_dev(host->mmc), |
| 1221 | "Unmask interrupt failed\n"); |
| 1222 | } |
| 1223 | |
| 1224 | /* Notify the core to resume the host */ |
| 1225 | ret = mmc_resume_host(host->mmc); |
| 1226 | if (ret == 0) |
| 1227 | host->suspended = 0; |
| 1228 | } |
| 1229 | |
| 1230 | return ret; |
| 1231 | |
| 1232 | clk_en_err: |
| 1233 | dev_dbg(mmc_dev(host->mmc), |
| 1234 | "Failed to enable MMC clocks during resume\n"); |
| 1235 | return ret; |
| 1236 | } |
| 1237 | |
| 1238 | #else |
| 1239 | #define omap_mmc_suspend NULL |
| 1240 | #define omap_mmc_resume NULL |
| 1241 | #endif |
| 1242 | |
| 1243 | static struct platform_driver omap_mmc_driver = { |
| 1244 | .probe = omap_mmc_probe, |
| 1245 | .remove = omap_mmc_remove, |
| 1246 | .suspend = omap_mmc_suspend, |
| 1247 | .resume = omap_mmc_resume, |
| 1248 | .driver = { |
| 1249 | .name = DRIVER_NAME, |
| 1250 | .owner = THIS_MODULE, |
| 1251 | }, |
| 1252 | }; |
| 1253 | |
| 1254 | static int __init omap_mmc_init(void) |
| 1255 | { |
| 1256 | /* Register the MMC driver */ |
| 1257 | return platform_driver_register(&omap_mmc_driver); |
| 1258 | } |
| 1259 | |
| 1260 | static void __exit omap_mmc_cleanup(void) |
| 1261 | { |
| 1262 | /* Unregister MMC driver */ |
| 1263 | platform_driver_unregister(&omap_mmc_driver); |
| 1264 | } |
| 1265 | |
| 1266 | module_init(omap_mmc_init); |
| 1267 | module_exit(omap_mmc_cleanup); |
| 1268 | |
| 1269 | MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); |
| 1270 | MODULE_LICENSE("GPL"); |
| 1271 | MODULE_ALIAS("platform:" DRIVER_NAME); |
| 1272 | MODULE_AUTHOR("Texas Instruments Inc"); |