Tomas Winkler | df48c32 | 2008-03-06 10:40:19 -0800 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
Tomas Winkler | df48c32 | 2008-03-06 10:40:19 -0800 | [diff] [blame] | 3 | * GPL LICENSE SUMMARY |
| 4 | * |
| 5 | * Copyright(c) 2008 Intel Corporation. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of version 2 of the GNU General Public License as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but |
| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, |
| 19 | * USA |
| 20 | * |
| 21 | * The full GNU General Public License is included in this distribution |
| 22 | * in the file called LICENSE.GPL. |
| 23 | * |
| 24 | * Contact Information: |
| 25 | * Tomas Winkler <tomas.winkler@intel.com> |
| 26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 27 | *****************************************************************************/ |
| 28 | |
| 29 | #include <linux/kernel.h> |
| 30 | #include <linux/module.h> |
| 31 | #include <linux/version.h> |
Assaf Krauss | 1d0a082 | 2008-03-14 10:38:48 -0700 | [diff] [blame] | 32 | #include <net/mac80211.h> |
Tomas Winkler | df48c32 | 2008-03-06 10:40:19 -0800 | [diff] [blame] | 33 | |
Tomas Winkler | 712b6cf | 2008-03-12 16:58:52 -0700 | [diff] [blame] | 34 | struct iwl_priv; /* FIXME: remove */ |
Tomas Winkler | 0a6857e | 2008-03-12 16:58:49 -0700 | [diff] [blame] | 35 | #include "iwl-debug.h" |
Assaf Krauss | 6bc913b | 2008-03-11 16:17:18 -0700 | [diff] [blame] | 36 | #include "iwl-eeprom.h" |
Tomas Winkler | 3e0d4cb | 2008-04-24 11:55:38 -0700 | [diff] [blame] | 37 | #include "iwl-dev.h" /* FIXME: remove */ |
Tomas Winkler | df48c32 | 2008-03-06 10:40:19 -0800 | [diff] [blame] | 38 | #include "iwl-core.h" |
Tomas Winkler | b661c81 | 2008-04-23 17:14:54 -0700 | [diff] [blame] | 39 | #include "iwl-io.h" |
Mohamed Abbas | ad97edd | 2008-03-28 16:21:06 -0700 | [diff] [blame] | 40 | #include "iwl-rfkill.h" |
Mohamed Abbas | 5da4b55 | 2008-04-21 15:41:51 -0700 | [diff] [blame] | 41 | #include "iwl-power.h" |
Tomas Winkler | df48c32 | 2008-03-06 10:40:19 -0800 | [diff] [blame] | 42 | |
Assaf Krauss | 1d0a082 | 2008-03-14 10:38:48 -0700 | [diff] [blame] | 43 | |
Tomas Winkler | df48c32 | 2008-03-06 10:40:19 -0800 | [diff] [blame] | 44 | MODULE_DESCRIPTION("iwl core"); |
| 45 | MODULE_VERSION(IWLWIFI_VERSION); |
| 46 | MODULE_AUTHOR(DRV_COPYRIGHT); |
Tomas Winkler | 712b6cf | 2008-03-12 16:58:52 -0700 | [diff] [blame] | 47 | MODULE_LICENSE("GPL"); |
Tomas Winkler | df48c32 | 2008-03-06 10:40:19 -0800 | [diff] [blame] | 48 | |
Tomas Winkler | 0a6857e | 2008-03-12 16:58:49 -0700 | [diff] [blame] | 49 | #ifdef CONFIG_IWLWIFI_DEBUG |
| 50 | u32 iwl_debug_level; |
| 51 | EXPORT_SYMBOL(iwl_debug_level); |
Tomas Winkler | df48c32 | 2008-03-06 10:40:19 -0800 | [diff] [blame] | 52 | #endif |
Assaf Krauss | 1d0a082 | 2008-03-14 10:38:48 -0700 | [diff] [blame] | 53 | |
Ron Rindjunsky | c7de35c | 2008-04-23 17:15:05 -0700 | [diff] [blame] | 54 | #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \ |
| 55 | [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \ |
| 56 | IWL_RATE_SISO_##s##M_PLCP, \ |
| 57 | IWL_RATE_MIMO2_##s##M_PLCP,\ |
| 58 | IWL_RATE_MIMO3_##s##M_PLCP,\ |
| 59 | IWL_RATE_##r##M_IEEE, \ |
| 60 | IWL_RATE_##ip##M_INDEX, \ |
| 61 | IWL_RATE_##in##M_INDEX, \ |
| 62 | IWL_RATE_##rp##M_INDEX, \ |
| 63 | IWL_RATE_##rn##M_INDEX, \ |
| 64 | IWL_RATE_##pp##M_INDEX, \ |
| 65 | IWL_RATE_##np##M_INDEX } |
| 66 | |
| 67 | /* |
| 68 | * Parameter order: |
| 69 | * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate |
| 70 | * |
| 71 | * If there isn't a valid next or previous rate then INV is used which |
| 72 | * maps to IWL_RATE_INVALID |
| 73 | * |
| 74 | */ |
| 75 | const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = { |
| 76 | IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */ |
| 77 | IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */ |
| 78 | IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */ |
| 79 | IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */ |
| 80 | IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */ |
| 81 | IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */ |
| 82 | IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */ |
| 83 | IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */ |
| 84 | IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */ |
| 85 | IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */ |
| 86 | IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */ |
| 87 | IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */ |
| 88 | IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */ |
| 89 | /* FIXME:RS: ^^ should be INV (legacy) */ |
| 90 | }; |
| 91 | EXPORT_SYMBOL(iwl4965_rates); |
| 92 | |
Assaf Krauss | 1d0a082 | 2008-03-14 10:38:48 -0700 | [diff] [blame] | 93 | /* This function both allocates and initializes hw and priv. */ |
| 94 | struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg, |
| 95 | struct ieee80211_ops *hw_ops) |
| 96 | { |
| 97 | struct iwl_priv *priv; |
| 98 | |
| 99 | /* mac80211 allocates memory for this device instance, including |
| 100 | * space for this driver's private structure */ |
| 101 | struct ieee80211_hw *hw = |
| 102 | ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops); |
| 103 | if (hw == NULL) { |
| 104 | IWL_ERROR("Can not allocate network device\n"); |
| 105 | goto out; |
| 106 | } |
| 107 | |
| 108 | priv = hw->priv; |
| 109 | priv->hw = hw; |
| 110 | |
| 111 | out: |
| 112 | return hw; |
| 113 | } |
| 114 | EXPORT_SYMBOL(iwl_alloc_all); |
| 115 | |
Tomas Winkler | b661c81 | 2008-04-23 17:14:54 -0700 | [diff] [blame] | 116 | void iwl_hw_detect(struct iwl_priv *priv) |
| 117 | { |
| 118 | priv->hw_rev = _iwl_read32(priv, CSR_HW_REV); |
| 119 | priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG); |
| 120 | pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id); |
| 121 | } |
| 122 | EXPORT_SYMBOL(iwl_hw_detect); |
| 123 | |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 124 | /* Tell nic where to find the "keep warm" buffer */ |
| 125 | int iwl_kw_init(struct iwl_priv *priv) |
| 126 | { |
| 127 | unsigned long flags; |
| 128 | int ret; |
| 129 | |
| 130 | spin_lock_irqsave(&priv->lock, flags); |
| 131 | ret = iwl_grab_nic_access(priv); |
| 132 | if (ret) |
| 133 | goto out; |
| 134 | |
| 135 | iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, |
| 136 | priv->kw.dma_addr >> 4); |
| 137 | iwl_release_nic_access(priv); |
| 138 | out: |
| 139 | spin_unlock_irqrestore(&priv->lock, flags); |
| 140 | return ret; |
| 141 | } |
| 142 | |
| 143 | int iwl_kw_alloc(struct iwl_priv *priv) |
| 144 | { |
| 145 | struct pci_dev *dev = priv->pci_dev; |
Ron Rindjunsky | 1646690 | 2008-05-05 10:22:50 +0800 | [diff] [blame] | 146 | struct iwl_kw *kw = &priv->kw; |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 147 | |
Ron Rindjunsky | 1646690 | 2008-05-05 10:22:50 +0800 | [diff] [blame] | 148 | kw->size = IWL_KW_SIZE; |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 149 | kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr); |
| 150 | if (!kw->v_addr) |
| 151 | return -ENOMEM; |
| 152 | |
| 153 | return 0; |
| 154 | } |
| 155 | |
| 156 | /** |
| 157 | * iwl_kw_free - Free the "keep warm" buffer |
| 158 | */ |
| 159 | void iwl_kw_free(struct iwl_priv *priv) |
| 160 | { |
| 161 | struct pci_dev *dev = priv->pci_dev; |
Ron Rindjunsky | 1646690 | 2008-05-05 10:22:50 +0800 | [diff] [blame] | 162 | struct iwl_kw *kw = &priv->kw; |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 163 | |
| 164 | if (kw->v_addr) { |
| 165 | pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr); |
| 166 | memset(kw, 0, sizeof(*kw)); |
| 167 | } |
| 168 | } |
| 169 | |
| 170 | int iwl_hw_nic_init(struct iwl_priv *priv) |
| 171 | { |
| 172 | unsigned long flags; |
| 173 | struct iwl_rx_queue *rxq = &priv->rxq; |
| 174 | int ret; |
| 175 | |
| 176 | /* nic_init */ |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 177 | spin_lock_irqsave(&priv->lock, flags); |
Ron Rindjunsky | 1b73af8 | 2008-05-05 10:22:51 +0800 | [diff] [blame^] | 178 | priv->cfg->ops->lib->apm_ops.init(priv); |
Ron Rindjunsky | 1053d35 | 2008-05-05 10:22:43 +0800 | [diff] [blame] | 179 | iwl_write32(priv, CSR_INT_COALESCING, 512 / 32); |
| 180 | spin_unlock_irqrestore(&priv->lock, flags); |
| 181 | |
| 182 | ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN); |
| 183 | |
| 184 | priv->cfg->ops->lib->apm_ops.config(priv); |
| 185 | |
| 186 | /* Allocate the RX queue, or reset if it is already allocated */ |
| 187 | if (!rxq->bd) { |
| 188 | ret = iwl_rx_queue_alloc(priv); |
| 189 | if (ret) { |
| 190 | IWL_ERROR("Unable to initialize Rx queue\n"); |
| 191 | return -ENOMEM; |
| 192 | } |
| 193 | } else |
| 194 | iwl_rx_queue_reset(priv, rxq); |
| 195 | |
| 196 | iwl_rx_replenish(priv); |
| 197 | |
| 198 | iwl_rx_init(priv, rxq); |
| 199 | |
| 200 | spin_lock_irqsave(&priv->lock, flags); |
| 201 | |
| 202 | rxq->need_update = 1; |
| 203 | iwl_rx_queue_update_write_ptr(priv, rxq); |
| 204 | |
| 205 | spin_unlock_irqrestore(&priv->lock, flags); |
| 206 | |
| 207 | /* Allocate and init all Tx and Command queues */ |
| 208 | ret = iwl_txq_ctx_reset(priv); |
| 209 | if (ret) |
| 210 | return ret; |
| 211 | |
| 212 | set_bit(STATUS_INIT, &priv->status); |
| 213 | |
| 214 | return 0; |
| 215 | } |
| 216 | EXPORT_SYMBOL(iwl_hw_nic_init); |
| 217 | |
Assaf Krauss | bf85ea4 | 2008-03-14 10:38:49 -0700 | [diff] [blame] | 218 | /** |
| 219 | * iwlcore_clear_stations_table - Clear the driver's station table |
| 220 | * |
| 221 | * NOTE: This does not clear or otherwise alter the device's station table. |
| 222 | */ |
| 223 | void iwlcore_clear_stations_table(struct iwl_priv *priv) |
| 224 | { |
| 225 | unsigned long flags; |
| 226 | |
| 227 | spin_lock_irqsave(&priv->sta_lock, flags); |
| 228 | |
| 229 | priv->num_stations = 0; |
| 230 | memset(priv->stations, 0, sizeof(priv->stations)); |
| 231 | |
| 232 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
| 233 | } |
| 234 | EXPORT_SYMBOL(iwlcore_clear_stations_table); |
| 235 | |
Ron Rindjunsky | c7de35c | 2008-04-23 17:15:05 -0700 | [diff] [blame] | 236 | void iwl_reset_qos(struct iwl_priv *priv) |
Assaf Krauss | bf85ea4 | 2008-03-14 10:38:49 -0700 | [diff] [blame] | 237 | { |
| 238 | u16 cw_min = 15; |
| 239 | u16 cw_max = 1023; |
| 240 | u8 aifs = 2; |
| 241 | u8 is_legacy = 0; |
| 242 | unsigned long flags; |
| 243 | int i; |
| 244 | |
| 245 | spin_lock_irqsave(&priv->lock, flags); |
| 246 | priv->qos_data.qos_active = 0; |
| 247 | |
| 248 | if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) { |
| 249 | if (priv->qos_data.qos_enable) |
| 250 | priv->qos_data.qos_active = 1; |
| 251 | if (!(priv->active_rate & 0xfff0)) { |
| 252 | cw_min = 31; |
| 253 | is_legacy = 1; |
| 254 | } |
| 255 | } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { |
| 256 | if (priv->qos_data.qos_enable) |
| 257 | priv->qos_data.qos_active = 1; |
| 258 | } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) { |
| 259 | cw_min = 31; |
| 260 | is_legacy = 1; |
| 261 | } |
| 262 | |
| 263 | if (priv->qos_data.qos_active) |
| 264 | aifs = 3; |
| 265 | |
| 266 | priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min); |
| 267 | priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max); |
| 268 | priv->qos_data.def_qos_parm.ac[0].aifsn = aifs; |
| 269 | priv->qos_data.def_qos_parm.ac[0].edca_txop = 0; |
| 270 | priv->qos_data.def_qos_parm.ac[0].reserved1 = 0; |
| 271 | |
| 272 | if (priv->qos_data.qos_active) { |
| 273 | i = 1; |
| 274 | priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min); |
| 275 | priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max); |
| 276 | priv->qos_data.def_qos_parm.ac[i].aifsn = 7; |
| 277 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; |
| 278 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; |
| 279 | |
| 280 | i = 2; |
| 281 | priv->qos_data.def_qos_parm.ac[i].cw_min = |
| 282 | cpu_to_le16((cw_min + 1) / 2 - 1); |
| 283 | priv->qos_data.def_qos_parm.ac[i].cw_max = |
| 284 | cpu_to_le16(cw_max); |
| 285 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; |
| 286 | if (is_legacy) |
| 287 | priv->qos_data.def_qos_parm.ac[i].edca_txop = |
| 288 | cpu_to_le16(6016); |
| 289 | else |
| 290 | priv->qos_data.def_qos_parm.ac[i].edca_txop = |
| 291 | cpu_to_le16(3008); |
| 292 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; |
| 293 | |
| 294 | i = 3; |
| 295 | priv->qos_data.def_qos_parm.ac[i].cw_min = |
| 296 | cpu_to_le16((cw_min + 1) / 4 - 1); |
| 297 | priv->qos_data.def_qos_parm.ac[i].cw_max = |
| 298 | cpu_to_le16((cw_max + 1) / 2 - 1); |
| 299 | priv->qos_data.def_qos_parm.ac[i].aifsn = 2; |
| 300 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; |
| 301 | if (is_legacy) |
| 302 | priv->qos_data.def_qos_parm.ac[i].edca_txop = |
| 303 | cpu_to_le16(3264); |
| 304 | else |
| 305 | priv->qos_data.def_qos_parm.ac[i].edca_txop = |
| 306 | cpu_to_le16(1504); |
| 307 | } else { |
| 308 | for (i = 1; i < 4; i++) { |
| 309 | priv->qos_data.def_qos_parm.ac[i].cw_min = |
| 310 | cpu_to_le16(cw_min); |
| 311 | priv->qos_data.def_qos_parm.ac[i].cw_max = |
| 312 | cpu_to_le16(cw_max); |
| 313 | priv->qos_data.def_qos_parm.ac[i].aifsn = aifs; |
| 314 | priv->qos_data.def_qos_parm.ac[i].edca_txop = 0; |
| 315 | priv->qos_data.def_qos_parm.ac[i].reserved1 = 0; |
| 316 | } |
| 317 | } |
| 318 | IWL_DEBUG_QOS("set QoS to default \n"); |
| 319 | |
| 320 | spin_unlock_irqrestore(&priv->lock, flags); |
| 321 | } |
Ron Rindjunsky | c7de35c | 2008-04-23 17:15:05 -0700 | [diff] [blame] | 322 | EXPORT_SYMBOL(iwl_reset_qos); |
| 323 | |
| 324 | #ifdef CONFIG_IWL4965_HT |
| 325 | static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, |
| 326 | struct ieee80211_ht_info *ht_info, |
| 327 | enum ieee80211_band band) |
| 328 | { |
| 329 | ht_info->cap = 0; |
| 330 | memset(ht_info->supp_mcs_set, 0, 16); |
| 331 | |
| 332 | ht_info->ht_supported = 1; |
| 333 | |
| 334 | if (priv->hw_params.fat_channel & BIT(band)) { |
| 335 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH; |
| 336 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40; |
| 337 | ht_info->supp_mcs_set[4] = 0x01; |
| 338 | } |
| 339 | ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD; |
| 340 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20; |
| 341 | ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS & |
| 342 | (IWL_MIMO_PS_NONE << 2)); |
| 343 | |
| 344 | if (priv->cfg->mod_params->amsdu_size_8K) |
| 345 | ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU; |
| 346 | |
| 347 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; |
| 348 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; |
| 349 | |
| 350 | ht_info->supp_mcs_set[0] = 0xFF; |
| 351 | if (priv->hw_params.tx_chains_num >= 2) |
| 352 | ht_info->supp_mcs_set[1] = 0xFF; |
| 353 | if (priv->hw_params.tx_chains_num >= 3) |
| 354 | ht_info->supp_mcs_set[2] = 0xFF; |
| 355 | } |
Andrew Morton | 88787d2 | 2008-05-13 21:05:50 -0700 | [diff] [blame] | 356 | #else |
| 357 | static inline void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, |
| 358 | struct ieee80211_ht_info *ht_info, |
| 359 | enum ieee80211_band band) |
| 360 | { |
| 361 | } |
Ron Rindjunsky | c7de35c | 2008-04-23 17:15:05 -0700 | [diff] [blame] | 362 | #endif /* CONFIG_IWL4965_HT */ |
| 363 | |
| 364 | static void iwlcore_init_hw_rates(struct iwl_priv *priv, |
| 365 | struct ieee80211_rate *rates) |
| 366 | { |
| 367 | int i; |
| 368 | |
| 369 | for (i = 0; i < IWL_RATE_COUNT; i++) { |
| 370 | rates[i].bitrate = iwl4965_rates[i].ieee * 5; |
| 371 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ |
| 372 | rates[i].hw_value_short = i; |
| 373 | rates[i].flags = 0; |
| 374 | if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { |
| 375 | /* |
| 376 | * If CCK != 1M then set short preamble rate flag. |
| 377 | */ |
| 378 | rates[i].flags |= |
| 379 | (iwl4965_rates[i].plcp == IWL_RATE_1M_PLCP) ? |
| 380 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
| 381 | } |
| 382 | } |
| 383 | } |
| 384 | |
| 385 | /** |
| 386 | * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom |
| 387 | */ |
| 388 | static int iwlcore_init_geos(struct iwl_priv *priv) |
| 389 | { |
| 390 | struct iwl_channel_info *ch; |
| 391 | struct ieee80211_supported_band *sband; |
| 392 | struct ieee80211_channel *channels; |
| 393 | struct ieee80211_channel *geo_ch; |
| 394 | struct ieee80211_rate *rates; |
| 395 | int i = 0; |
| 396 | |
| 397 | if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
| 398 | priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) { |
| 399 | IWL_DEBUG_INFO("Geography modes already initialized.\n"); |
| 400 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
| 401 | return 0; |
| 402 | } |
| 403 | |
| 404 | channels = kzalloc(sizeof(struct ieee80211_channel) * |
| 405 | priv->channel_count, GFP_KERNEL); |
| 406 | if (!channels) |
| 407 | return -ENOMEM; |
| 408 | |
| 409 | rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)), |
| 410 | GFP_KERNEL); |
| 411 | if (!rates) { |
| 412 | kfree(channels); |
| 413 | return -ENOMEM; |
| 414 | } |
| 415 | |
| 416 | /* 5.2GHz channels start after the 2.4GHz channels */ |
| 417 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
| 418 | sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)]; |
| 419 | /* just OFDM */ |
| 420 | sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; |
| 421 | sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE; |
| 422 | |
| 423 | iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ); |
| 424 | |
| 425 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
| 426 | sband->channels = channels; |
| 427 | /* OFDM & CCK */ |
| 428 | sband->bitrates = rates; |
| 429 | sband->n_bitrates = IWL_RATE_COUNT; |
| 430 | |
| 431 | iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ); |
| 432 | |
| 433 | priv->ieee_channels = channels; |
| 434 | priv->ieee_rates = rates; |
| 435 | |
| 436 | iwlcore_init_hw_rates(priv, rates); |
| 437 | |
| 438 | for (i = 0; i < priv->channel_count; i++) { |
| 439 | ch = &priv->channel_info[i]; |
| 440 | |
| 441 | /* FIXME: might be removed if scan is OK */ |
| 442 | if (!is_channel_valid(ch)) |
| 443 | continue; |
| 444 | |
| 445 | if (is_channel_a_band(ch)) |
| 446 | sband = &priv->bands[IEEE80211_BAND_5GHZ]; |
| 447 | else |
| 448 | sband = &priv->bands[IEEE80211_BAND_2GHZ]; |
| 449 | |
| 450 | geo_ch = &sband->channels[sband->n_channels++]; |
| 451 | |
| 452 | geo_ch->center_freq = |
| 453 | ieee80211_channel_to_frequency(ch->channel); |
| 454 | geo_ch->max_power = ch->max_power_avg; |
| 455 | geo_ch->max_antenna_gain = 0xff; |
| 456 | geo_ch->hw_value = ch->channel; |
| 457 | |
| 458 | if (is_channel_valid(ch)) { |
| 459 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
| 460 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; |
| 461 | |
| 462 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) |
| 463 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; |
| 464 | |
| 465 | if (ch->flags & EEPROM_CHANNEL_RADAR) |
| 466 | geo_ch->flags |= IEEE80211_CHAN_RADAR; |
| 467 | |
| 468 | if (ch->max_power_avg > priv->max_channel_txpower_limit) |
| 469 | priv->max_channel_txpower_limit = |
| 470 | ch->max_power_avg; |
| 471 | } else { |
| 472 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; |
| 473 | } |
| 474 | |
| 475 | /* Save flags for reg domain usage */ |
| 476 | geo_ch->orig_flags = geo_ch->flags; |
| 477 | |
| 478 | IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n", |
| 479 | ch->channel, geo_ch->center_freq, |
| 480 | is_channel_a_band(ch) ? "5.2" : "2.4", |
| 481 | geo_ch->flags & IEEE80211_CHAN_DISABLED ? |
| 482 | "restricted" : "valid", |
| 483 | geo_ch->flags); |
| 484 | } |
| 485 | |
| 486 | if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && |
| 487 | priv->cfg->sku & IWL_SKU_A) { |
| 488 | printk(KERN_INFO DRV_NAME |
| 489 | ": Incorrectly detected BG card as ABG. Please send " |
| 490 | "your PCI ID 0x%04X:0x%04X to maintainer.\n", |
| 491 | priv->pci_dev->device, priv->pci_dev->subsystem_device); |
| 492 | priv->cfg->sku &= ~IWL_SKU_A; |
| 493 | } |
| 494 | |
| 495 | printk(KERN_INFO DRV_NAME |
| 496 | ": Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
| 497 | priv->bands[IEEE80211_BAND_2GHZ].n_channels, |
| 498 | priv->bands[IEEE80211_BAND_5GHZ].n_channels); |
| 499 | |
| 500 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
| 501 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
| 502 | &priv->bands[IEEE80211_BAND_2GHZ]; |
| 503 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) |
| 504 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
| 505 | &priv->bands[IEEE80211_BAND_5GHZ]; |
| 506 | |
| 507 | set_bit(STATUS_GEO_CONFIGURED, &priv->status); |
| 508 | |
| 509 | return 0; |
| 510 | } |
| 511 | |
| 512 | /* |
| 513 | * iwlcore_free_geos - undo allocations in iwlcore_init_geos |
| 514 | */ |
| 515 | void iwlcore_free_geos(struct iwl_priv *priv) |
| 516 | { |
| 517 | kfree(priv->ieee_channels); |
| 518 | kfree(priv->ieee_rates); |
| 519 | clear_bit(STATUS_GEO_CONFIGURED, &priv->status); |
| 520 | } |
| 521 | EXPORT_SYMBOL(iwlcore_free_geos); |
| 522 | |
| 523 | #ifdef CONFIG_IWL4965_HT |
| 524 | static u8 is_single_rx_stream(struct iwl_priv *priv) |
| 525 | { |
| 526 | return !priv->current_ht_config.is_ht || |
| 527 | ((priv->current_ht_config.supp_mcs_set[1] == 0) && |
| 528 | (priv->current_ht_config.supp_mcs_set[2] == 0)) || |
| 529 | priv->ps_mode == IWL_MIMO_PS_STATIC; |
| 530 | } |
Tomas Winkler | 47c5196 | 2008-05-05 10:22:41 +0800 | [diff] [blame] | 531 | static u8 iwl_is_channel_extension(struct iwl_priv *priv, |
| 532 | enum ieee80211_band band, |
| 533 | u16 channel, u8 extension_chan_offset) |
| 534 | { |
| 535 | const struct iwl_channel_info *ch_info; |
| 536 | |
| 537 | ch_info = iwl_get_channel_info(priv, band, channel); |
| 538 | if (!is_channel_valid(ch_info)) |
| 539 | return 0; |
| 540 | |
| 541 | if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE) |
| 542 | return 0; |
| 543 | |
| 544 | if ((ch_info->fat_extension_channel == extension_chan_offset) || |
| 545 | (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX)) |
| 546 | return 1; |
| 547 | |
| 548 | return 0; |
| 549 | } |
| 550 | |
| 551 | u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv, |
| 552 | struct ieee80211_ht_info *sta_ht_inf) |
| 553 | { |
| 554 | struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config; |
| 555 | |
| 556 | if ((!iwl_ht_conf->is_ht) || |
| 557 | (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) || |
| 558 | (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)) |
| 559 | return 0; |
| 560 | |
| 561 | if (sta_ht_inf) { |
| 562 | if ((!sta_ht_inf->ht_supported) || |
| 563 | (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH))) |
| 564 | return 0; |
| 565 | } |
| 566 | |
| 567 | return iwl_is_channel_extension(priv, priv->band, |
| 568 | iwl_ht_conf->control_channel, |
| 569 | iwl_ht_conf->extension_chan_offset); |
| 570 | } |
| 571 | EXPORT_SYMBOL(iwl_is_fat_tx_allowed); |
| 572 | |
| 573 | void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info) |
| 574 | { |
| 575 | struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon; |
| 576 | u32 val; |
| 577 | |
| 578 | if (!ht_info->is_ht) |
| 579 | return; |
| 580 | |
| 581 | /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */ |
| 582 | if (iwl_is_fat_tx_allowed(priv, NULL)) |
| 583 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK; |
| 584 | else |
| 585 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK | |
| 586 | RXON_FLG_CHANNEL_MODE_PURE_40_MSK); |
| 587 | |
| 588 | if (le16_to_cpu(rxon->channel) != ht_info->control_channel) { |
| 589 | IWL_DEBUG_ASSOC("control diff than current %d %d\n", |
| 590 | le16_to_cpu(rxon->channel), |
| 591 | ht_info->control_channel); |
| 592 | rxon->channel = cpu_to_le16(ht_info->control_channel); |
| 593 | return; |
| 594 | } |
| 595 | |
| 596 | /* Note: control channel is opposite of extension channel */ |
| 597 | switch (ht_info->extension_chan_offset) { |
| 598 | case IWL_EXT_CHANNEL_OFFSET_ABOVE: |
| 599 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); |
| 600 | break; |
| 601 | case IWL_EXT_CHANNEL_OFFSET_BELOW: |
| 602 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; |
| 603 | break; |
| 604 | case IWL_EXT_CHANNEL_OFFSET_NONE: |
| 605 | default: |
| 606 | rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK; |
| 607 | break; |
| 608 | } |
| 609 | |
| 610 | val = ht_info->ht_protection; |
| 611 | |
| 612 | rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS); |
| 613 | |
| 614 | iwl_set_rxon_chain(priv); |
| 615 | |
| 616 | IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X " |
| 617 | "rxon flags 0x%X operation mode :0x%X " |
| 618 | "extension channel offset 0x%x " |
| 619 | "control chan %d\n", |
| 620 | ht_info->supp_mcs_set[0], |
| 621 | ht_info->supp_mcs_set[1], |
| 622 | ht_info->supp_mcs_set[2], |
| 623 | le32_to_cpu(rxon->flags), ht_info->ht_protection, |
| 624 | ht_info->extension_chan_offset, |
| 625 | ht_info->control_channel); |
| 626 | return; |
| 627 | } |
| 628 | EXPORT_SYMBOL(iwl_set_rxon_ht); |
| 629 | |
Ron Rindjunsky | c7de35c | 2008-04-23 17:15:05 -0700 | [diff] [blame] | 630 | #else |
| 631 | static inline u8 is_single_rx_stream(struct iwl_priv *priv) |
| 632 | { |
| 633 | return 1; |
| 634 | } |
| 635 | #endif /*CONFIG_IWL4965_HT */ |
| 636 | |
| 637 | /* |
| 638 | * Determine how many receiver/antenna chains to use. |
| 639 | * More provides better reception via diversity. Fewer saves power. |
| 640 | * MIMO (dual stream) requires at least 2, but works better with 3. |
| 641 | * This does not determine *which* chains to use, just how many. |
| 642 | */ |
| 643 | static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv, |
| 644 | u8 *idle_state, u8 *rx_state) |
| 645 | { |
| 646 | u8 is_single = is_single_rx_stream(priv); |
| 647 | u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1; |
| 648 | |
| 649 | /* # of Rx chains to use when expecting MIMO. */ |
| 650 | if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC))) |
| 651 | *rx_state = 2; |
| 652 | else |
| 653 | *rx_state = 3; |
| 654 | |
| 655 | /* # Rx chains when idling and maybe trying to save power */ |
| 656 | switch (priv->ps_mode) { |
| 657 | case IWL_MIMO_PS_STATIC: |
| 658 | case IWL_MIMO_PS_DYNAMIC: |
| 659 | *idle_state = (is_cam) ? 2 : 1; |
| 660 | break; |
| 661 | case IWL_MIMO_PS_NONE: |
| 662 | *idle_state = (is_cam) ? *rx_state : 1; |
| 663 | break; |
| 664 | default: |
| 665 | *idle_state = 1; |
| 666 | break; |
| 667 | } |
| 668 | |
| 669 | return 0; |
| 670 | } |
| 671 | |
| 672 | /** |
| 673 | * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image |
| 674 | * |
| 675 | * Selects how many and which Rx receivers/antennas/chains to use. |
| 676 | * This should not be used for scan command ... it puts data in wrong place. |
| 677 | */ |
| 678 | void iwl_set_rxon_chain(struct iwl_priv *priv) |
| 679 | { |
| 680 | u8 is_single = is_single_rx_stream(priv); |
| 681 | u8 idle_state, rx_state; |
| 682 | |
| 683 | priv->staging_rxon.rx_chain = 0; |
| 684 | rx_state = idle_state = 3; |
| 685 | |
| 686 | /* Tell uCode which antennas are actually connected. |
| 687 | * Before first association, we assume all antennas are connected. |
| 688 | * Just after first association, iwl_chain_noise_calibration() |
| 689 | * checks which antennas actually *are* connected. */ |
| 690 | priv->staging_rxon.rx_chain |= |
| 691 | cpu_to_le16(priv->hw_params.valid_rx_ant << |
| 692 | RXON_RX_CHAIN_VALID_POS); |
| 693 | |
| 694 | /* How many receivers should we use? */ |
| 695 | iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state); |
| 696 | priv->staging_rxon.rx_chain |= |
| 697 | cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS); |
| 698 | priv->staging_rxon.rx_chain |= |
| 699 | cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS); |
| 700 | |
| 701 | if (!is_single && (rx_state >= 2) && |
| 702 | !test_bit(STATUS_POWER_PMI, &priv->status)) |
| 703 | priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK; |
| 704 | else |
| 705 | priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK; |
| 706 | |
| 707 | IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain); |
| 708 | } |
| 709 | EXPORT_SYMBOL(iwl_set_rxon_chain); |
Assaf Krauss | bf85ea4 | 2008-03-14 10:38:49 -0700 | [diff] [blame] | 710 | |
| 711 | /** |
| 712 | * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON |
| 713 | * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz |
| 714 | * @channel: Any channel valid for the requested phymode |
| 715 | |
| 716 | * In addition to setting the staging RXON, priv->phymode is also set. |
| 717 | * |
| 718 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields |
| 719 | * in the staging RXON flag structure based on the phymode |
| 720 | */ |
Ron Rindjunsky | c7de35c | 2008-04-23 17:15:05 -0700 | [diff] [blame] | 721 | int iwl_set_rxon_channel(struct iwl_priv *priv, |
Assaf Krauss | bf85ea4 | 2008-03-14 10:38:49 -0700 | [diff] [blame] | 722 | enum ieee80211_band band, |
| 723 | u16 channel) |
| 724 | { |
Assaf Krauss | 8622e70 | 2008-03-21 13:53:43 -0700 | [diff] [blame] | 725 | if (!iwl_get_channel_info(priv, band, channel)) { |
Assaf Krauss | bf85ea4 | 2008-03-14 10:38:49 -0700 | [diff] [blame] | 726 | IWL_DEBUG_INFO("Could not set channel to %d [%d]\n", |
| 727 | channel, band); |
| 728 | return -EINVAL; |
| 729 | } |
| 730 | |
| 731 | if ((le16_to_cpu(priv->staging_rxon.channel) == channel) && |
| 732 | (priv->band == band)) |
| 733 | return 0; |
| 734 | |
| 735 | priv->staging_rxon.channel = cpu_to_le16(channel); |
| 736 | if (band == IEEE80211_BAND_5GHZ) |
| 737 | priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK; |
| 738 | else |
| 739 | priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK; |
| 740 | |
| 741 | priv->band = band; |
| 742 | |
| 743 | IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band); |
| 744 | |
| 745 | return 0; |
| 746 | } |
Ron Rindjunsky | c7de35c | 2008-04-23 17:15:05 -0700 | [diff] [blame] | 747 | EXPORT_SYMBOL(iwl_set_rxon_channel); |
Assaf Krauss | bf85ea4 | 2008-03-14 10:38:49 -0700 | [diff] [blame] | 748 | |
| 749 | static void iwlcore_init_hw(struct iwl_priv *priv) |
| 750 | { |
| 751 | struct ieee80211_hw *hw = priv->hw; |
| 752 | hw->rate_control_algorithm = "iwl-4965-rs"; |
| 753 | |
| 754 | /* Tell mac80211 and its clients (e.g. Wireless Extensions) |
| 755 | * the range of signal quality values that we'll provide. |
| 756 | * Negative values for level/noise indicate that we'll provide dBm. |
| 757 | * For WE, at least, non-0 values here *enable* display of values |
| 758 | * in app (iwconfig). */ |
| 759 | hw->max_rssi = -20; /* signal level, negative indicates dBm */ |
| 760 | hw->max_noise = -20; /* noise level, negative indicates dBm */ |
| 761 | hw->max_signal = 100; /* link quality indication (%) */ |
| 762 | |
| 763 | /* Tell mac80211 our Tx characteristics */ |
| 764 | hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE; |
| 765 | |
| 766 | /* Default value; 4 EDCA QOS priorities */ |
| 767 | hw->queues = 4; |
| 768 | #ifdef CONFIG_IWL4965_HT |
| 769 | /* Enhanced value; more queues, to support 11n aggregation */ |
Johannes Berg | e100bb6 | 2008-04-30 18:51:21 +0200 | [diff] [blame] | 770 | hw->ampdu_queues = 12; |
Assaf Krauss | bf85ea4 | 2008-03-14 10:38:49 -0700 | [diff] [blame] | 771 | #endif /* CONFIG_IWL4965_HT */ |
| 772 | } |
| 773 | |
Ron Rindjunsky | c7de35c | 2008-04-23 17:15:05 -0700 | [diff] [blame] | 774 | static int iwlcore_init_drv(struct iwl_priv *priv) |
| 775 | { |
| 776 | int ret; |
| 777 | int i; |
| 778 | |
| 779 | priv->retry_rate = 1; |
| 780 | priv->ibss_beacon = NULL; |
| 781 | |
| 782 | spin_lock_init(&priv->lock); |
| 783 | spin_lock_init(&priv->power_data.lock); |
| 784 | spin_lock_init(&priv->sta_lock); |
| 785 | spin_lock_init(&priv->hcmd_lock); |
| 786 | spin_lock_init(&priv->lq_mngr.lock); |
| 787 | |
| 788 | for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) |
| 789 | INIT_LIST_HEAD(&priv->ibss_mac_hash[i]); |
| 790 | |
| 791 | INIT_LIST_HEAD(&priv->free_frames); |
| 792 | |
| 793 | mutex_init(&priv->mutex); |
| 794 | |
| 795 | /* Clear the driver's (not device's) station table */ |
| 796 | iwlcore_clear_stations_table(priv); |
| 797 | |
| 798 | priv->data_retry_limit = -1; |
| 799 | priv->ieee_channels = NULL; |
| 800 | priv->ieee_rates = NULL; |
| 801 | priv->band = IEEE80211_BAND_2GHZ; |
| 802 | |
| 803 | priv->iw_mode = IEEE80211_IF_TYPE_STA; |
| 804 | |
| 805 | priv->use_ant_b_for_management_frame = 1; /* start with ant B */ |
| 806 | priv->ps_mode = IWL_MIMO_PS_NONE; |
| 807 | |
| 808 | /* Choose which receivers/antennas to use */ |
| 809 | iwl_set_rxon_chain(priv); |
| 810 | |
| 811 | iwl_reset_qos(priv); |
| 812 | |
| 813 | priv->qos_data.qos_active = 0; |
| 814 | priv->qos_data.qos_cap.val = 0; |
| 815 | |
| 816 | iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6); |
| 817 | |
| 818 | priv->rates_mask = IWL_RATES_MASK; |
| 819 | /* If power management is turned on, default to AC mode */ |
| 820 | priv->power_mode = IWL_POWER_AC; |
| 821 | priv->user_txpower_limit = IWL_DEFAULT_TX_POWER; |
| 822 | |
| 823 | ret = iwl_init_channel_map(priv); |
| 824 | if (ret) { |
| 825 | IWL_ERROR("initializing regulatory failed: %d\n", ret); |
| 826 | goto err; |
| 827 | } |
| 828 | |
| 829 | ret = iwlcore_init_geos(priv); |
| 830 | if (ret) { |
| 831 | IWL_ERROR("initializing geos failed: %d\n", ret); |
| 832 | goto err_free_channel_map; |
| 833 | } |
| 834 | |
| 835 | ret = ieee80211_register_hw(priv->hw); |
| 836 | if (ret) { |
| 837 | IWL_ERROR("Failed to register network device (error %d)\n", |
| 838 | ret); |
| 839 | goto err_free_geos; |
| 840 | } |
| 841 | |
| 842 | priv->hw->conf.beacon_int = 100; |
| 843 | priv->mac80211_registered = 1; |
| 844 | |
| 845 | return 0; |
| 846 | |
| 847 | err_free_geos: |
| 848 | iwlcore_free_geos(priv); |
| 849 | err_free_channel_map: |
| 850 | iwl_free_channel_map(priv); |
| 851 | err: |
| 852 | return ret; |
| 853 | } |
| 854 | |
Assaf Krauss | bf85ea4 | 2008-03-14 10:38:49 -0700 | [diff] [blame] | 855 | int iwl_setup(struct iwl_priv *priv) |
| 856 | { |
| 857 | int ret = 0; |
| 858 | iwlcore_init_hw(priv); |
Ron Rindjunsky | c7de35c | 2008-04-23 17:15:05 -0700 | [diff] [blame] | 859 | ret = iwlcore_init_drv(priv); |
Assaf Krauss | bf85ea4 | 2008-03-14 10:38:49 -0700 | [diff] [blame] | 860 | return ret; |
| 861 | } |
| 862 | EXPORT_SYMBOL(iwl_setup); |
| 863 | |
Mohamed Abbas | c8381fd | 2008-03-28 16:21:05 -0700 | [diff] [blame] | 864 | /* Low level driver call this function to update iwlcore with |
| 865 | * driver status. |
| 866 | */ |
| 867 | int iwlcore_low_level_notify(struct iwl_priv *priv, |
| 868 | enum iwlcore_card_notify notify) |
| 869 | { |
Mohamed Abbas | 03d29c6 | 2008-04-03 16:05:24 -0700 | [diff] [blame] | 870 | int ret; |
Mohamed Abbas | c8381fd | 2008-03-28 16:21:05 -0700 | [diff] [blame] | 871 | switch (notify) { |
| 872 | case IWLCORE_INIT_EVT: |
Mohamed Abbas | 03d29c6 | 2008-04-03 16:05:24 -0700 | [diff] [blame] | 873 | ret = iwl_rfkill_init(priv); |
| 874 | if (ret) |
| 875 | IWL_ERROR("Unable to initialize RFKILL system. " |
| 876 | "Ignoring error: %d\n", ret); |
Mohamed Abbas | 5da4b55 | 2008-04-21 15:41:51 -0700 | [diff] [blame] | 877 | iwl_power_initialize(priv); |
Mohamed Abbas | c8381fd | 2008-03-28 16:21:05 -0700 | [diff] [blame] | 878 | break; |
| 879 | case IWLCORE_START_EVT: |
Mohamed Abbas | 5da4b55 | 2008-04-21 15:41:51 -0700 | [diff] [blame] | 880 | iwl_power_update_mode(priv, 1); |
Mohamed Abbas | c8381fd | 2008-03-28 16:21:05 -0700 | [diff] [blame] | 881 | break; |
| 882 | case IWLCORE_STOP_EVT: |
| 883 | break; |
| 884 | case IWLCORE_REMOVE_EVT: |
Mohamed Abbas | ad97edd | 2008-03-28 16:21:06 -0700 | [diff] [blame] | 885 | iwl_rfkill_unregister(priv); |
Mohamed Abbas | c8381fd | 2008-03-28 16:21:05 -0700 | [diff] [blame] | 886 | break; |
| 887 | } |
| 888 | |
| 889 | return 0; |
| 890 | } |
| 891 | EXPORT_SYMBOL(iwlcore_low_level_notify); |
| 892 | |
Emmanuel Grumbach | 49ea859 | 2008-04-15 16:01:37 -0700 | [diff] [blame] | 893 | int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags) |
| 894 | { |
| 895 | u32 stat_flags = 0; |
| 896 | struct iwl_host_cmd cmd = { |
| 897 | .id = REPLY_STATISTICS_CMD, |
| 898 | .meta.flags = flags, |
| 899 | .len = sizeof(stat_flags), |
| 900 | .data = (u8 *) &stat_flags, |
| 901 | }; |
| 902 | return iwl_send_cmd(priv, &cmd); |
| 903 | } |
| 904 | EXPORT_SYMBOL(iwl_send_statistics_request); |
Tomas Winkler | 7e8c519 | 2008-04-15 16:01:43 -0700 | [diff] [blame] | 905 | |
Emmanuel Grumbach | b0692f2 | 2008-04-24 11:55:18 -0700 | [diff] [blame] | 906 | /** |
| 907 | * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host, |
| 908 | * using sample data 100 bytes apart. If these sample points are good, |
| 909 | * it's a pretty good bet that everything between them is good, too. |
| 910 | */ |
| 911 | static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
| 912 | { |
| 913 | u32 val; |
| 914 | int ret = 0; |
| 915 | u32 errcnt = 0; |
| 916 | u32 i; |
| 917 | |
| 918 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); |
| 919 | |
| 920 | ret = iwl_grab_nic_access(priv); |
| 921 | if (ret) |
| 922 | return ret; |
| 923 | |
| 924 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { |
| 925 | /* read data comes through single port, auto-incr addr */ |
| 926 | /* NOTE: Use the debugless read so we don't flood kernel log |
| 927 | * if IWL_DL_IO is set */ |
| 928 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
| 929 | i + RTC_INST_LOWER_BOUND); |
| 930 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
| 931 | if (val != le32_to_cpu(*image)) { |
| 932 | ret = -EIO; |
| 933 | errcnt++; |
| 934 | if (errcnt >= 3) |
| 935 | break; |
| 936 | } |
| 937 | } |
| 938 | |
| 939 | iwl_release_nic_access(priv); |
| 940 | |
| 941 | return ret; |
| 942 | } |
| 943 | |
| 944 | /** |
| 945 | * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host, |
| 946 | * looking at all data. |
| 947 | */ |
| 948 | static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image, |
| 949 | u32 len) |
| 950 | { |
| 951 | u32 val; |
| 952 | u32 save_len = len; |
| 953 | int ret = 0; |
| 954 | u32 errcnt; |
| 955 | |
| 956 | IWL_DEBUG_INFO("ucode inst image size is %u\n", len); |
| 957 | |
| 958 | ret = iwl_grab_nic_access(priv); |
| 959 | if (ret) |
| 960 | return ret; |
| 961 | |
| 962 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND); |
| 963 | |
| 964 | errcnt = 0; |
| 965 | for (; len > 0; len -= sizeof(u32), image++) { |
| 966 | /* read data comes through single port, auto-incr addr */ |
| 967 | /* NOTE: Use the debugless read so we don't flood kernel log |
| 968 | * if IWL_DL_IO is set */ |
| 969 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
| 970 | if (val != le32_to_cpu(*image)) { |
| 971 | IWL_ERROR("uCode INST section is invalid at " |
| 972 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
| 973 | save_len - len, val, le32_to_cpu(*image)); |
| 974 | ret = -EIO; |
| 975 | errcnt++; |
| 976 | if (errcnt >= 20) |
| 977 | break; |
| 978 | } |
| 979 | } |
| 980 | |
| 981 | iwl_release_nic_access(priv); |
| 982 | |
| 983 | if (!errcnt) |
| 984 | IWL_DEBUG_INFO |
| 985 | ("ucode image in INSTRUCTION memory is good\n"); |
| 986 | |
| 987 | return ret; |
| 988 | } |
| 989 | |
| 990 | /** |
| 991 | * iwl_verify_ucode - determine which instruction image is in SRAM, |
| 992 | * and verify its contents |
| 993 | */ |
| 994 | int iwl_verify_ucode(struct iwl_priv *priv) |
| 995 | { |
| 996 | __le32 *image; |
| 997 | u32 len; |
| 998 | int ret; |
| 999 | |
| 1000 | /* Try bootstrap */ |
| 1001 | image = (__le32 *)priv->ucode_boot.v_addr; |
| 1002 | len = priv->ucode_boot.len; |
| 1003 | ret = iwlcore_verify_inst_sparse(priv, image, len); |
| 1004 | if (!ret) { |
| 1005 | IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n"); |
| 1006 | return 0; |
| 1007 | } |
| 1008 | |
| 1009 | /* Try initialize */ |
| 1010 | image = (__le32 *)priv->ucode_init.v_addr; |
| 1011 | len = priv->ucode_init.len; |
| 1012 | ret = iwlcore_verify_inst_sparse(priv, image, len); |
| 1013 | if (!ret) { |
| 1014 | IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n"); |
| 1015 | return 0; |
| 1016 | } |
| 1017 | |
| 1018 | /* Try runtime/protocol */ |
| 1019 | image = (__le32 *)priv->ucode_code.v_addr; |
| 1020 | len = priv->ucode_code.len; |
| 1021 | ret = iwlcore_verify_inst_sparse(priv, image, len); |
| 1022 | if (!ret) { |
| 1023 | IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n"); |
| 1024 | return 0; |
| 1025 | } |
| 1026 | |
| 1027 | IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
| 1028 | |
| 1029 | /* Since nothing seems to match, show first several data entries in |
| 1030 | * instruction SRAM, so maybe visual inspection will give a clue. |
| 1031 | * Selection of bootstrap image (vs. other images) is arbitrary. */ |
| 1032 | image = (__le32 *)priv->ucode_boot.v_addr; |
| 1033 | len = priv->ucode_boot.len; |
| 1034 | ret = iwl_verify_inst_full(priv, image, len); |
| 1035 | |
| 1036 | return ret; |
| 1037 | } |
| 1038 | EXPORT_SYMBOL(iwl_verify_ucode); |
| 1039 | |