blob: 59340ff13a6486ccf7b06f75136a6fc89ca27cca [file] [log] [blame]
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +03001/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
Wey-Yi Guy4e318262011-12-27 11:21:32 -08008 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +03009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
Wey-Yi Guy4e318262011-12-27 11:21:32 -080033 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030034 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -080063#include <linux/pci.h>
64#include <linux/pci-aspm.h>
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -070065#include <linux/interrupt.h>
Emmanuel Grumbach87e56662011-08-25 23:10:50 -070066#include <linux/debugfs.h>
Emmanuel Grumbachcf614292012-01-08 16:33:58 +020067#include <linux/sched.h>
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -070068#include <linux/bitops.h>
69#include <linux/gfp.h>
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -070070
Johannes Berg82575102012-04-03 16:44:37 -070071#include "iwl-drv.h"
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +030072#include "iwl-trans.h"
Emmanuel Grumbach522376d2011-09-06 09:31:19 -070073#include "iwl-csr.h"
74#include "iwl-prph.h"
Emmanuel Grumbach7a10e3e42011-09-06 09:31:21 -070075#include "iwl-agn-hw.h"
Johannes Berg6468a012012-05-16 19:13:54 +020076#include "internal.h"
Johannes Berg0439bb62012-03-05 11:24:45 -080077
Johannes Bergddaf5a52013-01-08 11:25:44 +010078static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +030079{
Johannes Bergddaf5a52013-01-08 11:25:44 +010080 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
81 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
82 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
83 ~APMG_PS_CTRL_MSK_PWR_SRC);
84 else
85 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
86 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
87 ~APMG_PS_CTRL_MSK_PWR_SRC);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +030088}
89
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +020090/* PCI registers */
91#define PCI_CFG_RETRY_TIMEOUT 0x041
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +020092
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +020093static void iwl_pcie_apm_config(struct iwl_trans *trans)
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +020094{
Johannes Berg20d3b642012-05-16 22:54:29 +020095 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +020096 u16 lctl;
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +020097
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +020098 /*
99 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
100 * Check if BIOS (or OS) enabled L1-ASPM on this device.
101 * If so (likely), disable L0S, so device moves directly L0->L1;
102 * costs negligible amount of power savings.
103 * If not (unlikely), enable L0S, so there is at least some
104 * power savings, even without L1.
105 */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200106 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
Bjorn Helgaas438a0f02012-12-05 13:51:21 -0700107 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200108 /* L1-ASPM enabled; disable(!) L0S */
109 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
Joe Perches6a4b09f2012-10-28 01:05:47 -0700110 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200111 } else {
112 /* L1-ASPM disabled; enable(!) L0S */
113 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
Joe Perches6a4b09f2012-10-28 01:05:47 -0700114 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200115 }
Bjorn Helgaas438a0f02012-12-05 13:51:21 -0700116 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
Emmanuel Grumbachaf634be2012-01-08 21:12:22 +0200117}
118
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200119/*
120 * Start up NIC's basic functionality after it has been reset
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200121 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200122 * NOTE: This does not load uCode nor start the embedded processor
123 */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200124static int iwl_pcie_apm_init(struct iwl_trans *trans)
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200125{
Don Fry83626402012-03-07 09:52:37 -0800126 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200127 int ret = 0;
128 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
129
130 /*
131 * Use "set_bit" below rather than "write", to preserve any hardware
132 * bits already set by default after reset.
133 */
134
135 /* Disable L0S exit timer (platform NMI Work/Around) */
136 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
Johannes Berg20d3b642012-05-16 22:54:29 +0200137 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200138
139 /*
140 * Disable L0s without affecting L1;
141 * don't wait for ICH L0s (ICH bug W/A)
142 */
143 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
Johannes Berg20d3b642012-05-16 22:54:29 +0200144 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200145
146 /* Set FH wait threshold to maximum (HW error during stress W/A) */
147 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
148
149 /*
150 * Enable HAP INTA (interrupt from management bus) to
151 * wake device's PCI Express link L1a -> L0s
152 */
153 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
Johannes Berg20d3b642012-05-16 22:54:29 +0200154 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200155
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200156 iwl_pcie_apm_config(trans);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200157
158 /* Configure analog phase-lock-loop before activating to D0A */
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700159 if (trans->cfg->base_params->pll_cfg_val)
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200160 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700161 trans->cfg->base_params->pll_cfg_val);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200162
163 /*
164 * Set "initialization complete" bit to move adapter from
165 * D0U* --> D0A* (powered-up active) state.
166 */
167 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
168
169 /*
170 * Wait for clock stabilization; once stabilized, access to
171 * device-internal resources is supported, e.g. iwl_write_prph()
172 * and accesses to uCode SRAM.
173 */
174 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
Johannes Berg20d3b642012-05-16 22:54:29 +0200175 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
176 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200177 if (ret < 0) {
178 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
179 goto out;
180 }
181
182 /*
183 * Enable DMA clock and wait for it to stabilize.
184 *
185 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
186 * do not disable clocks. This preserves any hardware bits already
187 * set by default in "CLK_CTRL_REG" after reset.
188 */
189 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
190 udelay(20);
191
192 /* Disable L1-Active */
193 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
194 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
195
Don Fry83626402012-03-07 09:52:37 -0800196 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200197
198out:
199 return ret;
200}
201
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200202static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200203{
204 int ret = 0;
205
206 /* stop device's busmaster DMA activity */
207 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
208
209 ret = iwl_poll_bit(trans, CSR_RESET,
Johannes Berg20d3b642012-05-16 22:54:29 +0200210 CSR_RESET_REG_FLAG_MASTER_DISABLED,
211 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200212 if (ret)
213 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
214
215 IWL_DEBUG_INFO(trans, "stop master\n");
216
217 return ret;
218}
219
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200220static void iwl_pcie_apm_stop(struct iwl_trans *trans)
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200221{
Don Fry83626402012-03-07 09:52:37 -0800222 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200223 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
224
Don Fry83626402012-03-07 09:52:37 -0800225 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200226
227 /* Stop device's DMA activity */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200228 iwl_pcie_apm_stop_master(trans);
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200229
230 /* Reset the entire device */
231 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
232
233 udelay(10);
234
235 /*
236 * Clear "initialization complete" bit to move adapter from
237 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
238 */
239 iwl_clear_bit(trans, CSR_GP_CNTRL,
240 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
241}
242
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200243static int iwl_pcie_nic_init(struct iwl_trans *trans)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300244{
Johannes Berg7b114882012-02-05 13:55:11 -0800245 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300246 unsigned long flags;
247
248 /* nic_init */
Johannes Berg7b114882012-02-05 13:55:11 -0800249 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200250 iwl_pcie_apm_init(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300251
252 /* Set interrupt coalescing calibration timer to default (512 usecs) */
Johannes Berg20d3b642012-05-16 22:54:29 +0200253 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300254
Johannes Berg7b114882012-02-05 13:55:11 -0800255 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300256
Johannes Bergddaf5a52013-01-08 11:25:44 +0100257 iwl_pcie_set_pwr(trans, false);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300258
Johannes Bergecdb9752012-03-06 13:31:03 -0800259 iwl_op_mode_nic_config(trans->op_mode);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300260
261 /* Allocate the RX queue, or reset if it is already allocated */
Emmanuel Grumbach9805c4462012-11-14 14:44:18 +0200262 iwl_pcie_rx_init(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300263
264 /* Allocate or reset and init all Tx and Command queues */
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200265 if (iwl_pcie_tx_init(trans))
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300266 return -ENOMEM;
267
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700268 if (trans->cfg->base_params->shadow_reg_enable) {
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300269 /* enable shadow regs in HW */
Johannes Berg20d3b642012-05-16 22:54:29 +0200270 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
Meenakshi Venkataramand38069d2012-05-16 22:54:30 +0200271 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300272 }
273
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300274 return 0;
275}
276
277#define HW_READY_TIMEOUT (50)
278
279/* Note: returns poll_bit return value, which is >= 0 if success */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200280static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300281{
282 int ret;
283
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200284 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
Johannes Berg20d3b642012-05-16 22:54:29 +0200285 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300286
287 /* See if we got it */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200288 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
Johannes Berg20d3b642012-05-16 22:54:29 +0200289 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
290 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
291 HW_READY_TIMEOUT);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300292
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700293 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300294 return ret;
295}
296
297/* Note: returns standard 0/-ERROR code */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200298static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300299{
300 int ret;
Emmanuel Grumbach289e5502012-08-05 16:55:06 +0300301 int t = 0;
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300302
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700303 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300304
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200305 ret = iwl_pcie_set_hw_ready(trans);
Emmanuel Grumbachebb76782012-01-08 13:24:57 +0200306 /* If the card is ready, exit 0 */
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300307 if (ret >= 0)
308 return 0;
309
310 /* If HW is not ready, prepare the conditions to check again */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200311 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
Johannes Berg20d3b642012-05-16 22:54:29 +0200312 CSR_HW_IF_CONFIG_REG_PREPARE);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300313
Emmanuel Grumbach289e5502012-08-05 16:55:06 +0300314 do {
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200315 ret = iwl_pcie_set_hw_ready(trans);
Emmanuel Grumbach289e5502012-08-05 16:55:06 +0300316 if (ret >= 0)
317 return 0;
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300318
Emmanuel Grumbach289e5502012-08-05 16:55:06 +0300319 usleep_range(200, 1000);
320 t += 200;
321 } while (t < 150000);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300322
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300323 return ret;
324}
325
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200326/*
327 * ucode
328 */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200329static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
Johannes Berg83f84d72012-09-10 11:50:18 +0200330 dma_addr_t phy_addr, u32 byte_cnt)
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200331{
Johannes Berg13df1aa2012-03-06 13:31:00 -0800332 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200333 int ret;
334
Johannes Berg13df1aa2012-03-06 13:31:00 -0800335 trans_pcie->ucode_write_complete = false;
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200336
337 iwl_write_direct32(trans,
Johannes Berg20d3b642012-05-16 22:54:29 +0200338 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
339 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200340
341 iwl_write_direct32(trans,
Johannes Berg20d3b642012-05-16 22:54:29 +0200342 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
343 dst_addr);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200344
345 iwl_write_direct32(trans,
Johannes Berg83f84d72012-09-10 11:50:18 +0200346 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
347 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200348
349 iwl_write_direct32(trans,
Johannes Berg20d3b642012-05-16 22:54:29 +0200350 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
351 (iwl_get_dma_hi_addr(phy_addr)
352 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200353
354 iwl_write_direct32(trans,
Johannes Berg20d3b642012-05-16 22:54:29 +0200355 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
356 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
357 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
358 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200359
360 iwl_write_direct32(trans,
Johannes Berg20d3b642012-05-16 22:54:29 +0200361 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
362 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
363 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
364 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200365
Johannes Berg13df1aa2012-03-06 13:31:00 -0800366 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
367 trans_pcie->ucode_write_complete, 5 * HZ);
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200368 if (!ret) {
Johannes Berg83f84d72012-09-10 11:50:18 +0200369 IWL_ERR(trans, "Failed to load firmware chunk!\n");
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200370 return -ETIMEDOUT;
371 }
372
373 return 0;
374}
375
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200376static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
Johannes Berg83f84d72012-09-10 11:50:18 +0200377 const struct fw_desc *section)
378{
379 u8 *v_addr;
380 dma_addr_t p_addr;
381 u32 offset;
382 int ret = 0;
383
384 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
385 section_num);
386
387 v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
388 if (!v_addr)
389 return -ENOMEM;
390
391 for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
392 u32 copy_size;
393
394 copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
395
396 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200397 ret = iwl_pcie_load_firmware_chunk(trans,
398 section->offset + offset,
399 p_addr, copy_size);
Johannes Berg83f84d72012-09-10 11:50:18 +0200400 if (ret) {
401 IWL_ERR(trans,
402 "Could not load the [%d] uCode section\n",
403 section_num);
404 break;
405 }
406 }
407
408 dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
409 return ret;
410}
411
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200412static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
Johannes Berg0692fe42012-03-06 13:30:37 -0800413 const struct fw_img *image)
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200414{
Johannes Berg2d1c0042012-09-09 20:59:17 +0200415 int i, ret = 0;
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200416
Johannes Berg2d1c0042012-09-09 20:59:17 +0200417 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
Johannes Berg83f84d72012-09-10 11:50:18 +0200418 if (!image->sec[i].data)
Johannes Berg2d1c0042012-09-09 20:59:17 +0200419 break;
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200420
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200421 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
Johannes Berg2d1c0042012-09-09 20:59:17 +0200422 if (ret)
423 return ret;
424 }
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200425
426 /* Remove all resets to allow NIC to operate */
427 iwl_write32(trans, CSR_RESET, 0);
428
429 return 0;
430}
431
Johannes Berg0692fe42012-03-06 13:30:37 -0800432static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
Emmanuel Grumbach6ae02f32012-12-24 11:10:43 +0200433 const struct fw_img *fw, bool run_in_rfkill)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300434{
Johannes Bergd18aa872012-11-06 16:36:21 +0100435 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300436 int ret;
Johannes Bergc9eec952012-03-06 13:30:43 -0800437 bool hw_rfkill;
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300438
Johannes Berg496bab32012-03-06 13:30:45 -0800439 /* This may fail if AMT took ownership of the device */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200440 if (iwl_pcie_prepare_card_hw(trans)) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700441 IWL_WARN(trans, "Exit HW not ready\n");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300442 return -EIO;
443 }
444
Johannes Bergd18aa872012-11-06 16:36:21 +0100445 clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
446
Emmanuel Grumbach8c46bb72012-03-28 09:57:46 +0200447 iwl_enable_rfkill_int(trans);
448
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300449 /* If platform's RF_KILL switch is NOT set to KILL */
Emmanuel Grumbach8d425512012-03-28 11:00:58 +0200450 hw_rfkill = iwl_is_rfkill_set(trans);
Johannes Bergc9eec952012-03-06 13:30:43 -0800451 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
Emmanuel Grumbach6ae02f32012-12-24 11:10:43 +0200452 if (hw_rfkill && !run_in_rfkill)
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300453 return -ERFKILL;
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300454
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200455 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300456
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200457 ret = iwl_pcie_nic_init(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300458 if (ret) {
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700459 IWL_ERR(trans, "Unable to init nic\n");
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300460 return ret;
461 }
462
463 /* make sure rfkill handshake bits are cleared */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200464 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
465 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300466 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
467
468 /* clear (again), then enable host interrupts */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200469 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700470 iwl_enable_interrupts(trans);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300471
472 /* really make sure rfkill handshake bits are cleared */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200473 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
474 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
Emmanuel Grumbach392f8b72011-07-10 15:30:15 +0300475
Emmanuel Grumbachcf614292012-01-08 16:33:58 +0200476 /* Load the given image to the HW */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200477 return iwl_pcie_load_given_ucode(trans, fw);
Emmanuel Grumbachb3c2ce12011-07-07 15:50:10 +0300478}
479
Emmanuel Grumbachadca1232012-10-25 23:08:27 +0200480static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
Emmanuel Grumbached6a3802012-01-02 16:10:08 +0200481{
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200482 iwl_pcie_reset_ict(trans);
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200483 iwl_pcie_tx_start(trans, scd_addr);
Emmanuel Grumbachc170b862011-07-08 08:46:12 -0700484}
485
Emmanuel Grumbach43e58852011-11-09 16:50:50 -0800486static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -0700487{
Emmanuel Grumbach43e58852011-11-09 16:50:50 -0800488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Johannes Berg20d3b642012-05-16 22:54:29 +0200489 unsigned long flags;
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -0700490
Emmanuel Grumbach43e58852011-11-09 16:50:50 -0800491 /* tell the device to stop sending interrupts */
Johannes Berg7b114882012-02-05 13:55:11 -0800492 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -0700493 iwl_disable_interrupts(trans);
Johannes Berg7b114882012-02-05 13:55:11 -0800494 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
Emmanuel Grumbachae2c30b2011-08-25 23:11:20 -0700495
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +0300496 /* device going down, Stop using ICT table */
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200497 iwl_pcie_disable_ict(trans);
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +0300498
499 /*
500 * If a HW restart happens during firmware loading,
501 * then the firmware loading might call this function
502 * and later it might be called again due to the
503 * restart. So don't process again if the device is
504 * already dead.
505 */
Don Fry83626402012-03-07 09:52:37 -0800506 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200507 iwl_pcie_tx_stop(trans);
Emmanuel Grumbach9805c4462012-11-14 14:44:18 +0200508 iwl_pcie_rx_stop(trans);
Johannes Berg63791032012-09-06 15:33:42 +0200509
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +0300510 /* Power-down device's busmaster DMA clocks */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200511 iwl_write_prph(trans, APMG_CLK_DIS_REG,
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +0300512 APMG_CLK_VAL_DMA_CLK_RQT);
513 udelay(5);
514 }
515
516 /* Make sure (redundant) we've released our request to stay awake */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200517 iwl_clear_bit(trans, CSR_GP_CNTRL,
Johannes Berg20d3b642012-05-16 22:54:29 +0200518 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +0300519
520 /* Stop the device, and put it in low power state */
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200521 iwl_pcie_apm_stop(trans);
Emmanuel Grumbach43e58852011-11-09 16:50:50 -0800522
523 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
524 * Clean again the interrupt here
525 */
Johannes Berg7b114882012-02-05 13:55:11 -0800526 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
Emmanuel Grumbach43e58852011-11-09 16:50:50 -0800527 iwl_disable_interrupts(trans);
Johannes Berg7b114882012-02-05 13:55:11 -0800528 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
Emmanuel Grumbach43e58852011-11-09 16:50:50 -0800529
Emmanuel Grumbach218733c2012-03-31 08:28:38 -0700530 iwl_enable_rfkill_int(trans);
531
Emmanuel Grumbach43e58852011-11-09 16:50:50 -0800532 /* stop and reset the on-board processor */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200533 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
Don Fry74fda972012-03-20 16:36:54 -0700534
535 /* clear all status bits */
536 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
537 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
538 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
Don Fry01d651d2012-03-23 08:34:31 -0700539 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
Emmanuel Grumbachf946b522012-10-25 17:25:52 +0200540 clear_bit(STATUS_RFKILL, &trans_pcie->status);
Emmanuel Grumbachab6cf8e2011-07-07 14:37:26 +0300541}
542
Johannes Bergddaf5a52013-01-08 11:25:44 +0100543static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans)
Johannes Berg2dd4f9f2012-03-05 11:24:35 -0800544{
545 /* let the ucode operate on its own */
546 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
547 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
548
549 iwl_disable_interrupts(trans);
Johannes Bergddaf5a52013-01-08 11:25:44 +0100550 iwl_pcie_disable_ict(trans);
551
Johannes Berg2dd4f9f2012-03-05 11:24:35 -0800552 iwl_clear_bit(trans, CSR_GP_CNTRL,
553 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
Johannes Bergddaf5a52013-01-08 11:25:44 +0100554 iwl_clear_bit(trans, CSR_GP_CNTRL,
555 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
556
557 /*
558 * reset TX queues -- some of their registers reset during S3
559 * so if we don't reset everything here the D3 image would try
560 * to execute some invalid memory upon resume
561 */
562 iwl_trans_pcie_tx_reset(trans);
563
564 iwl_pcie_set_pwr(trans, true);
565}
566
567static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
568 enum iwl_d3_status *status)
569{
570 u32 val;
571 int ret;
572
573 iwl_pcie_set_pwr(trans, false);
574
575 val = iwl_read32(trans, CSR_RESET);
576 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
577 *status = IWL_D3_STATUS_RESET;
578 return 0;
579 }
580
581 /*
582 * Also enables interrupts - none will happen as the device doesn't
583 * know we're waking it up, only when the opmode actually tells it
584 * after this call.
585 */
586 iwl_pcie_reset_ict(trans);
587
588 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
589 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
590
591 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
592 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
593 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
594 25000);
595 if (ret) {
596 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
597 return ret;
598 }
599
600 iwl_trans_pcie_tx_reset(trans);
601
602 ret = iwl_pcie_rx_init(trans);
603 if (ret) {
604 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
605 return ret;
606 }
607
608 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
609 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
610
611 *status = IWL_D3_STATUS_ALIVE;
612 return 0;
Johannes Berg2dd4f9f2012-03-05 11:24:35 -0800613}
614
Emmanuel Grumbach57a1dc82012-01-08 13:22:16 +0200615static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
Emmanuel Grumbacha27367d2011-07-04 09:06:44 +0300616{
Johannes Bergc9eec952012-03-06 13:30:43 -0800617 bool hw_rfkill;
Johannes Berga8b691e2012-12-27 23:08:06 +0100618 int err;
Emmanuel Grumbach34c1b7b2011-07-04 08:58:19 +0300619
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200620 err = iwl_pcie_prepare_card_hw(trans);
Emmanuel Grumbachebb76782012-01-08 13:24:57 +0200621 if (err) {
Johannes Bergd6f1c312012-06-28 16:49:29 +0200622 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
Johannes Berga8b691e2012-12-27 23:08:06 +0100623 return err;
Emmanuel Grumbachebb76782012-01-08 13:24:57 +0200624 }
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200625
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200626 iwl_pcie_apm_init(trans);
Emmanuel Grumbacha6c684e2012-01-08 13:24:57 +0200627
Emmanuel Grumbach226c02c2012-03-28 10:33:09 +0200628 /* From now on, the op_mode will be kept updated about RF kill state */
629 iwl_enable_rfkill_int(trans);
630
Emmanuel Grumbach8d425512012-03-28 11:00:58 +0200631 hw_rfkill = iwl_is_rfkill_set(trans);
Johannes Bergc9eec952012-03-06 13:30:43 -0800632 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
Emmanuel Grumbachd48e2072012-01-08 13:48:21 +0200633
Johannes Berga8b691e2012-12-27 23:08:06 +0100634 return 0;
Emmanuel Grumbachc85eb612011-06-14 10:13:24 +0300635}
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -0700636
Emmanuel Grumbach218733c2012-03-31 08:28:38 -0700637static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
638 bool op_mode_leaving)
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200639{
Johannes Berg20d3b642012-05-16 22:54:29 +0200640 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbachd23f78e2012-03-28 10:34:02 +0200641 bool hw_rfkill;
Emmanuel Grumbach218733c2012-03-31 08:28:38 -0700642 unsigned long flags;
Emmanuel Grumbachd23f78e2012-03-28 10:34:02 +0200643
David Spinadelee7d7372012-08-12 08:14:04 +0300644 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
645 iwl_disable_interrupts(trans);
646 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
647
Emmanuel Grumbach7afe3702012-11-14 14:44:18 +0200648 iwl_pcie_apm_stop(trans);
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200649
Emmanuel Grumbach218733c2012-03-31 08:28:38 -0700650 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
651 iwl_disable_interrupts(trans);
652 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
653
Emmanuel Grumbach8d96bb62012-12-04 22:53:30 +0200654 iwl_pcie_disable_ict(trans);
655
Emmanuel Grumbach218733c2012-03-31 08:28:38 -0700656 if (!op_mode_leaving) {
657 /*
658 * Even if we stop the HW, we still want the RF kill
659 * interrupt
660 */
661 iwl_enable_rfkill_int(trans);
Emmanuel Grumbachd23f78e2012-03-28 10:34:02 +0200662
Emmanuel Grumbach218733c2012-03-31 08:28:38 -0700663 /*
664 * Check again since the RF kill state may have changed while
665 * all the interrupts were disabled, in this case we couldn't
666 * receive the RF kill interrupt and update the state in the
667 * op_mode.
668 */
669 hw_rfkill = iwl_is_rfkill_set(trans);
670 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
671 }
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +0200672}
673
Emmanuel Grumbach03905492012-01-03 13:48:07 +0200674static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
675{
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -0800676 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
Emmanuel Grumbach03905492012-01-03 13:48:07 +0200677}
678
679static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
680{
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -0800681 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
Emmanuel Grumbach03905492012-01-03 13:48:07 +0200682}
683
684static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
685{
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -0800686 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
Emmanuel Grumbach03905492012-01-03 13:48:07 +0200687}
688
Emmanuel Grumbach6a06b6c2012-12-02 13:07:30 +0200689static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
690{
691 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
692 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
693}
694
695static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
696 u32 val)
697{
698 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
699 ((addr & 0x0000FFFF) | (3 << 24)));
700 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
701}
702
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -0800703static void iwl_trans_pcie_configure(struct iwl_trans *trans,
Johannes Berg9eae88f2012-03-15 13:26:52 -0700704 const struct iwl_trans_config *trans_cfg)
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -0800705{
706 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
707
708 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
Emmanuel Grumbachb04db9a2012-06-21 11:53:44 +0300709 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
Johannes Bergd663ee72012-03-10 13:00:07 -0800710 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
711 trans_pcie->n_no_reclaim_cmds = 0;
712 else
713 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
714 if (trans_pcie->n_no_reclaim_cmds)
715 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
716 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
Johannes Berg9eae88f2012-03-15 13:26:52 -0700717
Johannes Bergb2cf4102012-04-09 17:46:51 -0700718 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
719 if (trans_pcie->rx_buf_size_8k)
720 trans_pcie->rx_page_order = get_order(8 * 1024);
721 else
722 trans_pcie->rx_page_order = get_order(4 * 1024);
Johannes Berg7c5ba4a2012-04-09 17:46:54 -0700723
724 trans_pcie->wd_timeout =
725 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
Johannes Bergd9fb6462012-03-26 08:23:39 -0700726
727 trans_pcie->command_names = trans_cfg->command_names;
Emmanuel Grumbach046db342012-12-05 15:07:54 +0200728 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -0800729}
730
Johannes Bergd1ff5252012-04-12 06:24:30 -0700731void iwl_trans_pcie_free(struct iwl_trans *trans)
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -0700732{
Johannes Berg20d3b642012-05-16 22:54:29 +0200733 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -0800734
Johannes Berg0aa86df2012-12-27 22:58:21 +0100735 synchronize_irq(trans_pcie->pci_dev->irq);
736 tasklet_kill(&trans_pcie->irq_tasklet);
737
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +0200738 iwl_pcie_tx_free(trans);
Emmanuel Grumbach9805c4462012-11-14 14:44:18 +0200739 iwl_pcie_rx_free(trans);
Johannes Berg63791032012-09-06 15:33:42 +0200740
Johannes Berga8b691e2012-12-27 23:08:06 +0100741 free_irq(trans_pcie->pci_dev->irq, trans);
742 iwl_pcie_free_ict(trans);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -0800743
744 pci_disable_msi(trans_pcie->pci_dev);
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -0800745 iounmap(trans_pcie->hw_base);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -0800746 pci_release_regions(trans_pcie->pci_dev);
747 pci_disable_device(trans_pcie->pci_dev);
Emmanuel Grumbach59c647b2012-05-24 19:24:34 +0300748 kmem_cache_destroy(trans->dev_cmd_pool);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -0800749
Emmanuel Grumbach6d8f6ee2011-08-25 23:11:06 -0700750 kfree(trans);
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -0700751}
752
Don Fry47107e82012-03-15 13:27:06 -0700753static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
754{
755 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
756
757 if (state)
Don Fry01d651d2012-03-23 08:34:31 -0700758 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
Don Fry47107e82012-03-15 13:27:06 -0700759 else
Don Fry01d651d2012-03-23 08:34:31 -0700760 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
Don Fry47107e82012-03-15 13:27:06 -0700761}
762
Johannes Bergc01a4042011-09-15 11:46:45 -0700763#ifdef CONFIG_PM_SLEEP
Emmanuel Grumbach57210f72011-08-25 23:10:52 -0700764static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
765{
Emmanuel Grumbach57210f72011-08-25 23:10:52 -0700766 return 0;
767}
768
769static int iwl_trans_pcie_resume(struct iwl_trans *trans)
770{
Johannes Bergc9eec952012-03-06 13:30:43 -0800771 bool hw_rfkill;
Emmanuel Grumbach57210f72011-08-25 23:10:52 -0700772
Emmanuel Grumbach8c46bb72012-03-28 09:57:46 +0200773 iwl_enable_rfkill_int(trans);
774
Emmanuel Grumbach8d425512012-03-28 11:00:58 +0200775 hw_rfkill = iwl_is_rfkill_set(trans);
Emmanuel Grumbach7120d982012-02-09 16:08:15 +0200776 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
Emmanuel Grumbach57210f72011-08-25 23:10:52 -0700777
778 return 0;
779}
Johannes Bergc01a4042011-09-15 11:46:45 -0700780#endif /* CONFIG_PM_SLEEP */
Emmanuel Grumbach57210f72011-08-25 23:10:52 -0700781
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +0200782static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)
783{
784 int ret;
785
786 lockdep_assert_held(&trans->reg_lock);
787
788 /* this bit wakes up the NIC */
789 __iwl_set_bit(trans, CSR_GP_CNTRL,
790 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
791
792 /*
793 * These bits say the device is running, and should keep running for
794 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
795 * but they do not indicate that embedded SRAM is restored yet;
796 * 3945 and 4965 have volatile SRAM, and must save/restore contents
797 * to/from host DRAM when sleeping/waking for power-saving.
798 * Each direction takes approximately 1/4 millisecond; with this
799 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
800 * series of register accesses are expected (e.g. reading Event Log),
801 * to keep device from sleeping.
802 *
803 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
804 * SRAM is okay/restored. We don't check that here because this call
805 * is just for hardware register access; but GP1 MAC_SLEEP check is a
806 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
807 *
808 * 5000 series and later (including 1000 series) have non-volatile SRAM,
809 * and do not save/restore SRAM when power cycling.
810 */
811 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
812 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
813 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
814 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
815 if (unlikely(ret < 0)) {
816 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
817 if (!silent) {
818 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
819 WARN_ONCE(1,
820 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
821 val);
822 return false;
823 }
824 }
825
826 return true;
827}
828
829static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
830{
831 lockdep_assert_held(&trans->reg_lock);
832 __iwl_clear_bit(trans, CSR_GP_CNTRL,
833 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
834 /*
835 * Above we read the CSR_GP_CNTRL register, which will flush
836 * any previous writes, but we need the write that clears the
837 * MAC_ACCESS_REQ bit to be performed before any other writes
838 * scheduled on different CPUs (after we drop reg_lock).
839 */
840 mmiowb();
841}
842
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +0200843static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
844 void *buf, int dwords)
845{
846 unsigned long flags;
847 int offs, ret = 0;
848 u32 *vals = buf;
849
850 spin_lock_irqsave(&trans->reg_lock, flags);
Emmanuel Grumbachabae2382012-12-31 13:46:42 +0200851 if (iwl_trans_grab_nic_access(trans, false)) {
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +0200852 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
853 for (offs = 0; offs < dwords; offs++)
854 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
855 iwl_trans_release_nic_access(trans);
856 } else {
857 ret = -EBUSY;
858 }
859 spin_unlock_irqrestore(&trans->reg_lock, flags);
860 return ret;
861}
862
863static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
864 void *buf, int dwords)
865{
866 unsigned long flags;
867 int offs, ret = 0;
868 u32 *vals = buf;
869
870 spin_lock_irqsave(&trans->reg_lock, flags);
Emmanuel Grumbachabae2382012-12-31 13:46:42 +0200871 if (iwl_trans_grab_nic_access(trans, false)) {
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +0200872 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
873 for (offs = 0; offs < dwords; offs++)
Emmanuel Grumbach01387ff2013-01-09 11:37:59 +0200874 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
875 vals ? vals[offs] : 0);
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +0200876 iwl_trans_release_nic_access(trans);
877 } else {
878 ret = -EBUSY;
879 }
880 spin_unlock_irqrestore(&trans->reg_lock, flags);
881 return ret;
882}
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +0200883
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -0700884#define IWL_FLUSH_WAIT_MS 2000
885
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200886static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -0700887{
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700888 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200889 struct iwl_txq *txq;
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -0700890 struct iwl_queue *q;
891 int cnt;
892 unsigned long now = jiffies;
893 int ret = 0;
894
895 /* waiting for all the tx frames complete might take a while */
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -0700896 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
Wey-Yi Guy9ba19472012-03-09 10:12:42 -0800897 if (cnt == trans_pcie->cmd_queue)
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -0700898 continue;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -0700899 txq = &trans_pcie->txq[cnt];
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -0700900 q = &txq->q;
901 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
902 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
903 msleep(1);
904
905 if (q->read_ptr != q->write_ptr) {
906 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
907 ret = -ETIMEDOUT;
908 break;
909 }
910 }
911 return ret;
912}
913
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700914static const char *get_fh_string(int cmd)
915{
Johannes Bergd9fb6462012-03-26 08:23:39 -0700916#define IWL_CMD(x) case x: return #x
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700917 switch (cmd) {
918 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
919 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
920 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
921 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
922 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
923 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
924 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
925 IWL_CMD(FH_TSSR_TX_STATUS_REG);
926 IWL_CMD(FH_TSSR_TX_ERROR_REG);
927 default:
928 return "UNKNOWN";
929 }
Johannes Bergd9fb6462012-03-26 08:23:39 -0700930#undef IWL_CMD
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700931}
932
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +0200933int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf)
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700934{
935 int i;
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700936 static const u32 fh_tbl[] = {
937 FH_RSCSR_CHNL0_STTS_WPTR_REG,
938 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
939 FH_RSCSR_CHNL0_WPTR,
940 FH_MEM_RCSR_CHNL0_CONFIG_REG,
941 FH_MEM_RSSR_SHARED_CTRL_REG,
942 FH_MEM_RSSR_RX_STATUS_REG,
943 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
944 FH_TSSR_TX_STATUS_REG,
945 FH_TSSR_TX_ERROR_REG
946 };
Johannes Berg94543a82012-08-21 18:57:10 +0200947
948#ifdef CONFIG_IWLWIFI_DEBUGFS
949 if (buf) {
950 int pos = 0;
951 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
952
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700953 *buf = kmalloc(bufsz, GFP_KERNEL);
954 if (!*buf)
955 return -ENOMEM;
Johannes Berg94543a82012-08-21 18:57:10 +0200956
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700957 pos += scnprintf(*buf + pos, bufsz - pos,
958 "FH register values:\n");
Johannes Berg94543a82012-08-21 18:57:10 +0200959
960 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700961 pos += scnprintf(*buf + pos, bufsz - pos,
962 " %34s: 0X%08x\n",
963 get_fh_string(fh_tbl[i]),
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200964 iwl_read_direct32(trans, fh_tbl[i]));
Johannes Berg94543a82012-08-21 18:57:10 +0200965
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700966 return pos;
967 }
968#endif
Johannes Berg94543a82012-08-21 18:57:10 +0200969
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700970 IWL_ERR(trans, "FH register values:\n");
Johannes Berg94543a82012-08-21 18:57:10 +0200971 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700972 IWL_ERR(trans, " %34s: 0X%08x\n",
973 get_fh_string(fh_tbl[i]),
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200974 iwl_read_direct32(trans, fh_tbl[i]));
Johannes Berg94543a82012-08-21 18:57:10 +0200975
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700976 return 0;
977}
978
979static const char *get_csr_string(int cmd)
980{
Johannes Bergd9fb6462012-03-26 08:23:39 -0700981#define IWL_CMD(x) case x: return #x
Emmanuel Grumbachff620842011-09-06 09:31:25 -0700982 switch (cmd) {
983 IWL_CMD(CSR_HW_IF_CONFIG_REG);
984 IWL_CMD(CSR_INT_COALESCING);
985 IWL_CMD(CSR_INT);
986 IWL_CMD(CSR_INT_MASK);
987 IWL_CMD(CSR_FH_INT_STATUS);
988 IWL_CMD(CSR_GPIO_IN);
989 IWL_CMD(CSR_RESET);
990 IWL_CMD(CSR_GP_CNTRL);
991 IWL_CMD(CSR_HW_REV);
992 IWL_CMD(CSR_EEPROM_REG);
993 IWL_CMD(CSR_EEPROM_GP);
994 IWL_CMD(CSR_OTP_GP_REG);
995 IWL_CMD(CSR_GIO_REG);
996 IWL_CMD(CSR_GP_UCODE_REG);
997 IWL_CMD(CSR_GP_DRIVER_REG);
998 IWL_CMD(CSR_UCODE_DRV_GP1);
999 IWL_CMD(CSR_UCODE_DRV_GP2);
1000 IWL_CMD(CSR_LED_REG);
1001 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1002 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1003 IWL_CMD(CSR_ANA_PLL_CFG);
1004 IWL_CMD(CSR_HW_REV_WA_REG);
1005 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1006 default:
1007 return "UNKNOWN";
1008 }
Johannes Bergd9fb6462012-03-26 08:23:39 -07001009#undef IWL_CMD
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001010}
1011
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001012void iwl_pcie_dump_csr(struct iwl_trans *trans)
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001013{
1014 int i;
1015 static const u32 csr_tbl[] = {
1016 CSR_HW_IF_CONFIG_REG,
1017 CSR_INT_COALESCING,
1018 CSR_INT,
1019 CSR_INT_MASK,
1020 CSR_FH_INT_STATUS,
1021 CSR_GPIO_IN,
1022 CSR_RESET,
1023 CSR_GP_CNTRL,
1024 CSR_HW_REV,
1025 CSR_EEPROM_REG,
1026 CSR_EEPROM_GP,
1027 CSR_OTP_GP_REG,
1028 CSR_GIO_REG,
1029 CSR_GP_UCODE_REG,
1030 CSR_GP_DRIVER_REG,
1031 CSR_UCODE_DRV_GP1,
1032 CSR_UCODE_DRV_GP2,
1033 CSR_LED_REG,
1034 CSR_DRAM_INT_TBL_REG,
1035 CSR_GIO_CHICKEN_BITS,
1036 CSR_ANA_PLL_CFG,
1037 CSR_HW_REV_WA_REG,
1038 CSR_DBG_HPET_MEM_REG
1039 };
1040 IWL_ERR(trans, "CSR values:\n");
1041 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1042 "CSR_INT_PERIODIC_REG)\n");
1043 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1044 IWL_ERR(trans, " %25s: 0X%08x\n",
1045 get_csr_string(csr_tbl[i]),
Emmanuel Grumbach1042db22012-01-03 16:56:15 +02001046 iwl_read32(trans, csr_tbl[i]));
Emmanuel Grumbachff620842011-09-06 09:31:25 -07001047 }
1048}
1049
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001050#ifdef CONFIG_IWLWIFI_DEBUGFS
1051/* create and remove of files */
1052#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -07001053 if (!debugfs_create_file(#name, mode, parent, trans, \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001054 &iwl_dbgfs_##name##_ops)) \
Meenakshi Venkataraman9da987a2012-07-16 18:43:56 -07001055 goto err; \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001056} while (0)
1057
1058/* file operation */
1059#define DEBUGFS_READ_FUNC(name) \
1060static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1061 char __user *user_buf, \
1062 size_t count, loff_t *ppos);
1063
1064#define DEBUGFS_WRITE_FUNC(name) \
1065static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1066 const char __user *user_buf, \
1067 size_t count, loff_t *ppos);
1068
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001069#define DEBUGFS_READ_FILE_OPS(name) \
1070 DEBUGFS_READ_FUNC(name); \
1071static const struct file_operations iwl_dbgfs_##name##_ops = { \
1072 .read = iwl_dbgfs_##name##_read, \
Stephen Boyd234e3402012-04-05 14:25:11 -07001073 .open = simple_open, \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001074 .llseek = generic_file_llseek, \
1075};
1076
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001077#define DEBUGFS_WRITE_FILE_OPS(name) \
1078 DEBUGFS_WRITE_FUNC(name); \
1079static const struct file_operations iwl_dbgfs_##name##_ops = { \
1080 .write = iwl_dbgfs_##name##_write, \
Stephen Boyd234e3402012-04-05 14:25:11 -07001081 .open = simple_open, \
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001082 .llseek = generic_file_llseek, \
1083};
1084
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001085#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1086 DEBUGFS_READ_FUNC(name); \
1087 DEBUGFS_WRITE_FUNC(name); \
1088static const struct file_operations iwl_dbgfs_##name##_ops = { \
1089 .write = iwl_dbgfs_##name##_write, \
1090 .read = iwl_dbgfs_##name##_read, \
Stephen Boyd234e3402012-04-05 14:25:11 -07001091 .open = simple_open, \
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001092 .llseek = generic_file_llseek, \
1093};
1094
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001095static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
Johannes Berg20d3b642012-05-16 22:54:29 +02001096 char __user *user_buf,
1097 size_t count, loff_t *ppos)
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001098{
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -07001099 struct iwl_trans *trans = file->private_data;
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001101 struct iwl_txq *txq;
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001102 struct iwl_queue *q;
1103 char *buf;
1104 int pos = 0;
1105 int cnt;
1106 int ret;
Wey-Yi Guy1745e442012-03-09 11:13:40 -08001107 size_t bufsz;
1108
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001109 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001110
Johannes Bergf9e75442012-03-30 09:37:39 +02001111 if (!trans_pcie->txq)
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001112 return -EAGAIN;
Johannes Bergf9e75442012-03-30 09:37:39 +02001113
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001114 buf = kzalloc(bufsz, GFP_KERNEL);
1115 if (!buf)
1116 return -ENOMEM;
1117
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001118 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
Emmanuel Grumbach8ad71be2011-08-25 23:11:32 -07001119 txq = &trans_pcie->txq[cnt];
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001120 q = &txq->q;
1121 pos += scnprintf(buf + pos, bufsz - pos,
Johannes Berg9eae88f2012-03-15 13:26:52 -07001122 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001123 cnt, q->read_ptr, q->write_ptr,
Johannes Berg9eae88f2012-03-15 13:26:52 -07001124 !!test_bit(cnt, trans_pcie->queue_used),
1125 !!test_bit(cnt, trans_pcie->queue_stopped));
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001126 }
1127 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1128 kfree(buf);
1129 return ret;
1130}
1131
1132static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
Johannes Berg20d3b642012-05-16 22:54:29 +02001133 char __user *user_buf,
1134 size_t count, loff_t *ppos)
1135{
Emmanuel Grumbach5a878bf2011-08-25 23:10:51 -07001136 struct iwl_trans *trans = file->private_data;
Johannes Berg20d3b642012-05-16 22:54:29 +02001137 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001138 struct iwl_rxq *rxq = &trans_pcie->rxq;
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001139 char buf[256];
1140 int pos = 0;
1141 const size_t bufsz = sizeof(buf);
1142
1143 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1144 rxq->read);
1145 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1146 rxq->write);
1147 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1148 rxq->free_count);
1149 if (rxq->rb_stts) {
1150 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1151 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1152 } else {
1153 pos += scnprintf(buf + pos, bufsz - pos,
1154 "closed_rb_num: Not Allocated\n");
1155 }
1156 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1157}
1158
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001159static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1160 char __user *user_buf,
Johannes Berg20d3b642012-05-16 22:54:29 +02001161 size_t count, loff_t *ppos)
1162{
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001163 struct iwl_trans *trans = file->private_data;
Johannes Berg20d3b642012-05-16 22:54:29 +02001164 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001165 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1166
1167 int pos = 0;
1168 char *buf;
1169 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1170 ssize_t ret;
1171
1172 buf = kzalloc(bufsz, GFP_KERNEL);
Johannes Bergf9e75442012-03-30 09:37:39 +02001173 if (!buf)
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001174 return -ENOMEM;
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001175
1176 pos += scnprintf(buf + pos, bufsz - pos,
1177 "Interrupt Statistics Report:\n");
1178
1179 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1180 isr_stats->hw);
1181 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1182 isr_stats->sw);
1183 if (isr_stats->sw || isr_stats->hw) {
1184 pos += scnprintf(buf + pos, bufsz - pos,
1185 "\tLast Restarting Code: 0x%X\n",
1186 isr_stats->err_code);
1187 }
1188#ifdef CONFIG_IWLWIFI_DEBUG
1189 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1190 isr_stats->sch);
1191 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1192 isr_stats->alive);
1193#endif
1194 pos += scnprintf(buf + pos, bufsz - pos,
1195 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1196
1197 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1198 isr_stats->ctkill);
1199
1200 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1201 isr_stats->wakeup);
1202
1203 pos += scnprintf(buf + pos, bufsz - pos,
1204 "Rx command responses:\t\t %u\n", isr_stats->rx);
1205
1206 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1207 isr_stats->tx);
1208
1209 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1210 isr_stats->unhandled);
1211
1212 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1213 kfree(buf);
1214 return ret;
1215}
1216
1217static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1218 const char __user *user_buf,
1219 size_t count, loff_t *ppos)
1220{
1221 struct iwl_trans *trans = file->private_data;
Johannes Berg20d3b642012-05-16 22:54:29 +02001222 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001223 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1224
1225 char buf[8];
1226 int buf_size;
1227 u32 reset_flag;
1228
1229 memset(buf, 0, sizeof(buf));
1230 buf_size = min(count, sizeof(buf) - 1);
1231 if (copy_from_user(buf, user_buf, buf_size))
1232 return -EFAULT;
1233 if (sscanf(buf, "%x", &reset_flag) != 1)
1234 return -EFAULT;
1235 if (reset_flag == 0)
1236 memset(isr_stats, 0, sizeof(*isr_stats));
1237
1238 return count;
1239}
1240
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001241static ssize_t iwl_dbgfs_csr_write(struct file *file,
Johannes Berg20d3b642012-05-16 22:54:29 +02001242 const char __user *user_buf,
1243 size_t count, loff_t *ppos)
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001244{
1245 struct iwl_trans *trans = file->private_data;
1246 char buf[8];
1247 int buf_size;
1248 int csr;
1249
1250 memset(buf, 0, sizeof(buf));
1251 buf_size = min(count, sizeof(buf) - 1);
1252 if (copy_from_user(buf, user_buf, buf_size))
1253 return -EFAULT;
1254 if (sscanf(buf, "%d", &csr) != 1)
1255 return -EFAULT;
1256
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001257 iwl_pcie_dump_csr(trans);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001258
1259 return count;
1260}
1261
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001262static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
Johannes Berg20d3b642012-05-16 22:54:29 +02001263 char __user *user_buf,
1264 size_t count, loff_t *ppos)
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001265{
1266 struct iwl_trans *trans = file->private_data;
Johannes Berg94543a82012-08-21 18:57:10 +02001267 char *buf = NULL;
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001268 int pos = 0;
1269 ssize_t ret = -EFAULT;
1270
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001271 ret = pos = iwl_pcie_dump_fh(trans, &buf);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001272 if (buf) {
1273 ret = simple_read_from_buffer(user_buf,
1274 count, ppos, buf, pos);
1275 kfree(buf);
1276 }
1277
1278 return ret;
1279}
1280
Johannes Berg48dffd32012-04-09 17:46:57 -07001281static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
1282 const char __user *user_buf,
1283 size_t count, loff_t *ppos)
1284{
1285 struct iwl_trans *trans = file->private_data;
1286
1287 if (!trans->op_mode)
1288 return -EAGAIN;
1289
Emmanuel Grumbach24172f32012-06-17 16:04:25 +03001290 local_bh_disable();
Johannes Berg48dffd32012-04-09 17:46:57 -07001291 iwl_op_mode_nic_error(trans->op_mode);
Emmanuel Grumbach24172f32012-06-17 16:04:25 +03001292 local_bh_enable();
Johannes Berg48dffd32012-04-09 17:46:57 -07001293
1294 return count;
1295}
1296
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001297DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001298DEBUGFS_READ_FILE_OPS(fh_reg);
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001299DEBUGFS_READ_FILE_OPS(rx_queue);
1300DEBUGFS_READ_FILE_OPS(tx_queue);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001301DEBUGFS_WRITE_FILE_OPS(csr);
Johannes Berg48dffd32012-04-09 17:46:57 -07001302DEBUGFS_WRITE_FILE_OPS(fw_restart);
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001303
1304/*
1305 * Create the debugfs files and directories
1306 *
1307 */
1308static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
Johannes Berg20d3b642012-05-16 22:54:29 +02001309 struct dentry *dir)
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001310{
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001311 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1312 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
Emmanuel Grumbach1f7b6172011-08-25 23:10:59 -07001313 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
Emmanuel Grumbach16db88b2011-08-25 23:11:08 -07001314 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1315 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
Johannes Berg48dffd32012-04-09 17:46:57 -07001316 DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001317 return 0;
Meenakshi Venkataraman9da987a2012-07-16 18:43:56 -07001318
1319err:
1320 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1321 return -ENOMEM;
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001322}
1323#else
1324static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
Johannes Berg20d3b642012-05-16 22:54:29 +02001325 struct dentry *dir)
1326{
1327 return 0;
1328}
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001329#endif /*CONFIG_IWLWIFI_DEBUGFS */
1330
Johannes Bergd1ff5252012-04-12 06:24:30 -07001331static const struct iwl_trans_ops trans_ops_pcie = {
Emmanuel Grumbach57a1dc82012-01-08 13:22:16 +02001332 .start_hw = iwl_trans_pcie_start_hw,
Emmanuel Grumbachcc56feb2012-01-08 13:37:59 +02001333 .stop_hw = iwl_trans_pcie_stop_hw,
Emmanuel Grumbached6a3802012-01-02 16:10:08 +02001334 .fw_alive = iwl_trans_pcie_fw_alive,
Emmanuel Grumbachcf614292012-01-08 16:33:58 +02001335 .start_fw = iwl_trans_pcie_start_fw,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001336 .stop_device = iwl_trans_pcie_stop_device,
1337
Johannes Bergddaf5a52013-01-08 11:25:44 +01001338 .d3_suspend = iwl_trans_pcie_d3_suspend,
1339 .d3_resume = iwl_trans_pcie_d3_resume,
Johannes Berg2dd4f9f2012-03-05 11:24:35 -08001340
Emmanuel Grumbachf02831b2012-11-14 14:44:18 +02001341 .send_cmd = iwl_trans_pcie_send_hcmd,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001342
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001343 .tx = iwl_trans_pcie_tx,
Emmanuel Grumbacha0eaad72011-08-25 23:11:00 -07001344 .reclaim = iwl_trans_pcie_reclaim,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001345
Emmanuel Grumbachd0624be2012-05-29 13:07:30 +03001346 .txq_disable = iwl_trans_pcie_txq_disable,
Emmanuel Grumbach4beaf6c2012-05-29 11:29:10 +03001347 .txq_enable = iwl_trans_pcie_txq_enable,
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001348
Emmanuel Grumbach87e56662011-08-25 23:10:50 -07001349 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001350
Emmanuel Grumbach990aa6d2012-11-14 12:39:52 +02001351 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
Emmanuel Grumbach5f178cd2011-08-25 23:11:29 -07001352
Johannes Bergc01a4042011-09-15 11:46:45 -07001353#ifdef CONFIG_PM_SLEEP
Emmanuel Grumbach57210f72011-08-25 23:10:52 -07001354 .suspend = iwl_trans_pcie_suspend,
1355 .resume = iwl_trans_pcie_resume,
Johannes Bergc01a4042011-09-15 11:46:45 -07001356#endif
Emmanuel Grumbach03905492012-01-03 13:48:07 +02001357 .write8 = iwl_trans_pcie_write8,
1358 .write32 = iwl_trans_pcie_write32,
1359 .read32 = iwl_trans_pcie_read32,
Emmanuel Grumbach6a06b6c2012-12-02 13:07:30 +02001360 .read_prph = iwl_trans_pcie_read_prph,
1361 .write_prph = iwl_trans_pcie_write_prph,
Emmanuel Grumbach4fd442d2012-12-24 14:27:11 +02001362 .read_mem = iwl_trans_pcie_read_mem,
1363 .write_mem = iwl_trans_pcie_write_mem,
Meenakshi Venkataramanc6f600f2012-03-08 11:29:12 -08001364 .configure = iwl_trans_pcie_configure,
Don Fry47107e82012-03-15 13:27:06 -07001365 .set_pmi = iwl_trans_pcie_set_pmi,
Emmanuel Grumbach7a65d172012-12-24 15:01:24 +02001366 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1367 .release_nic_access = iwl_trans_pcie_release_nic_access
Emmanuel Grumbache6bb4c92011-08-25 23:10:48 -07001368};
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001369
Emmanuel Grumbach87ce05a2012-03-26 09:03:18 -07001370struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001371 const struct pci_device_id *ent,
1372 const struct iwl_cfg *cfg)
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001373{
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001374 struct iwl_trans_pcie *trans_pcie;
1375 struct iwl_trans *trans;
1376 u16 pci_cmd;
1377 int err;
1378
1379 trans = kzalloc(sizeof(struct iwl_trans) +
Johannes Berg20d3b642012-05-16 22:54:29 +02001380 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001381
Emmanuel Grumbachdbeca582012-11-13 13:19:33 +02001382 if (!trans)
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001383 return NULL;
1384
1385 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1386
1387 trans->ops = &trans_ops_pcie;
Emmanuel Grumbach035f7ff2012-03-26 08:57:01 -07001388 trans->cfg = cfg;
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001389 trans_pcie->trans = trans;
Johannes Berg7b114882012-02-05 13:55:11 -08001390 spin_lock_init(&trans_pcie->irq_lock);
Johannes Berg13df1aa2012-03-06 13:31:00 -08001391 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001392
1393 /* W/A - seems to solve weird behavior. We need to remove this if we
1394 * don't want to stay in L1 all the time. This wastes a lot of power */
1395 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
Johannes Berg20d3b642012-05-16 22:54:29 +02001396 PCIE_LINK_STATE_CLKPM);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001397
1398 if (pci_enable_device(pdev)) {
1399 err = -ENODEV;
1400 goto out_no_pci;
1401 }
1402
1403 pci_set_master(pdev);
1404
1405 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1406 if (!err)
1407 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1408 if (err) {
1409 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1410 if (!err)
1411 err = pci_set_consistent_dma_mask(pdev,
Johannes Berg20d3b642012-05-16 22:54:29 +02001412 DMA_BIT_MASK(32));
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001413 /* both attempts failed: */
1414 if (err) {
Joe Perches6a4b09f2012-10-28 01:05:47 -07001415 dev_err(&pdev->dev, "No suitable DMA available\n");
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001416 goto out_pci_disable_device;
1417 }
1418 }
1419
1420 err = pci_request_regions(pdev, DRV_NAME);
1421 if (err) {
Joe Perches6a4b09f2012-10-28 01:05:47 -07001422 dev_err(&pdev->dev, "pci_request_regions failed\n");
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001423 goto out_pci_disable_device;
1424 }
1425
Stanislaw Gruszka05f5b972012-03-07 09:52:26 -08001426 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001427 if (!trans_pcie->hw_base) {
Joe Perches6a4b09f2012-10-28 01:05:47 -07001428 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001429 err = -ENODEV;
1430 goto out_pci_release_regions;
1431 }
1432
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001433 /* We disable the RETRY_TIMEOUT register (0x41) to keep
1434 * PCI Tx retries from interfering with C3 CPU state */
1435 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1436
1437 err = pci_enable_msi(pdev);
Emmanuel Grumbach9f904b32012-11-13 13:35:43 +02001438 if (err) {
Joe Perches6a4b09f2012-10-28 01:05:47 -07001439 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
Emmanuel Grumbach9f904b32012-11-13 13:35:43 +02001440 /* enable rfkill interrupt: hw bug w/a */
1441 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1442 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1443 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1444 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1445 }
1446 }
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001447
1448 trans->dev = &pdev->dev;
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001449 trans_pcie->pci_dev = pdev;
Emmanuel Grumbach08079a492012-01-09 16:23:00 +02001450 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
Emmanuel Grumbach99673ee2012-01-08 21:19:45 +02001451 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
Emmanuel Grumbach9ca85962012-01-08 21:19:45 +02001452 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1453 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001454
Meenakshi Venkataraman69a10b22012-03-10 13:00:09 -08001455 /* Initialize the wait queue for commands */
Emmanuel Grumbachf946b522012-10-25 17:25:52 +02001456 init_waitqueue_head(&trans_pcie->wait_command_queue);
Emmanuel Grumbach8b5bed92012-04-23 15:03:06 -07001457 spin_lock_init(&trans->reg_lock);
Meenakshi Venkataraman69a10b22012-03-10 13:00:09 -08001458
Johannes Berg3ec45882012-07-12 13:56:28 +02001459 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1460 "iwl_cmd_pool:%s", dev_name(trans->dev));
Emmanuel Grumbach59c647b2012-05-24 19:24:34 +03001461
1462 trans->dev_cmd_headroom = 0;
1463 trans->dev_cmd_pool =
Johannes Berg3ec45882012-07-12 13:56:28 +02001464 kmem_cache_create(trans->dev_cmd_pool_name,
Emmanuel Grumbach59c647b2012-05-24 19:24:34 +03001465 sizeof(struct iwl_device_cmd)
1466 + trans->dev_cmd_headroom,
1467 sizeof(void *),
1468 SLAB_HWCACHE_ALIGN,
1469 NULL);
1470
1471 if (!trans->dev_cmd_pool)
1472 goto out_pci_disable_msi;
1473
Johannes Berga8b691e2012-12-27 23:08:06 +01001474 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1475
1476 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1477 iwl_pcie_tasklet, (unsigned long)trans);
1478
1479 if (iwl_pcie_alloc_ict(trans))
1480 goto out_free_cmd_pool;
1481
1482 err = request_irq(pdev->irq, iwl_pcie_isr_ict,
1483 IRQF_SHARED, DRV_NAME, trans);
1484 if (err) {
1485 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1486 goto out_free_ict;
1487 }
1488
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001489 return trans;
1490
Johannes Berga8b691e2012-12-27 23:08:06 +01001491out_free_ict:
1492 iwl_pcie_free_ict(trans);
1493out_free_cmd_pool:
1494 kmem_cache_destroy(trans->dev_cmd_pool);
Emmanuel Grumbach59c647b2012-05-24 19:24:34 +03001495out_pci_disable_msi:
1496 pci_disable_msi(pdev);
Emmanuel Grumbacha42a1842012-02-02 14:33:08 -08001497out_pci_release_regions:
1498 pci_release_regions(pdev);
1499out_pci_disable_device:
1500 pci_disable_device(pdev);
1501out_no_pci:
1502 kfree(trans);
1503 return NULL;
1504}