blob: 1e6e28df5d7b8030973c7a0c50d83466fb5b3b2e [file] [log] [blame]
Alejandro Cabrerae9659e62011-06-02 22:13:11 +01001/*
Michal Simek9419c072013-05-31 07:56:33 +02002 * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
3 *
Michal Simekd14fd962014-02-12 14:34:32 +01004 * (C) Copyright 2013 - 2014 Xilinx, Inc.
Michal Simek9419c072013-05-31 07:56:33 +02005 * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010012
Michal Simekf06cdfd2014-02-12 14:34:34 +010013#include <linux/err.h>
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010014#include <linux/module.h>
15#include <linux/types.h>
16#include <linux/kernel.h>
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010017#include <linux/ioport.h>
18#include <linux/watchdog.h>
19#include <linux/io.h>
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010020#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/of_address.h>
23
24/* Register offsets for the Wdt device */
25#define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */
26#define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */
27#define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */
28
29/* Control/Status Register Masks */
30#define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */
31#define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */
32#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
33
34/* Control/Status Register 0/1 bits */
35#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */
36
37/* SelfTest constants */
38#define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
39#define XWT_TIMER_FAILED 0xFFFFFFFF
40
41#define WATCHDOG_NAME "Xilinx Watchdog"
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010042
43struct xwdt_device {
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010044 void __iomem *base;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010045 u32 wdt_interval;
Michal Simek90663172014-02-12 14:41:19 +010046 spinlock_t spinlock;
47 struct watchdog_device xilinx_wdt_wdd;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010048};
49
Michal Simekd14fd962014-02-12 14:34:32 +010050static int xilinx_wdt_start(struct watchdog_device *wdd)
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010051{
Michal Simek5cf4e692014-02-12 14:34:33 +010052 u32 control_status_reg;
Michal Simek90663172014-02-12 14:41:19 +010053 struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
Michal Simek5cf4e692014-02-12 14:34:33 +010054
Michal Simek90663172014-02-12 14:41:19 +010055 spin_lock(&xdev->spinlock);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010056
57 /* Clean previous status and enable the watchdog timer */
Michal Simek90663172014-02-12 14:41:19 +010058 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010059 control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
60
61 iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
Michal Simek90663172014-02-12 14:41:19 +010062 xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010063
Michal Simek90663172014-02-12 14:41:19 +010064 iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010065
Michal Simek90663172014-02-12 14:41:19 +010066 spin_unlock(&xdev->spinlock);
Michal Simekd14fd962014-02-12 14:34:32 +010067
68 return 0;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010069}
70
Michal Simekd14fd962014-02-12 14:34:32 +010071static int xilinx_wdt_stop(struct watchdog_device *wdd)
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010072{
Michal Simek5cf4e692014-02-12 14:34:33 +010073 u32 control_status_reg;
Michal Simek90663172014-02-12 14:41:19 +010074 struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
Michal Simek5cf4e692014-02-12 14:34:33 +010075
Michal Simek90663172014-02-12 14:41:19 +010076 spin_lock(&xdev->spinlock);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010077
Michal Simek90663172014-02-12 14:41:19 +010078 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010079
80 iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
Michal Simek90663172014-02-12 14:41:19 +010081 xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010082
Michal Simek90663172014-02-12 14:41:19 +010083 iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010084
Michal Simek90663172014-02-12 14:41:19 +010085 spin_unlock(&xdev->spinlock);
Joe Perches27c766a2012-02-15 15:06:19 -080086 pr_info("Stopped!\n");
Michal Simekd14fd962014-02-12 14:34:32 +010087
88 return 0;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010089}
90
Michal Simekd14fd962014-02-12 14:34:32 +010091static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010092{
Michal Simek5cf4e692014-02-12 14:34:33 +010093 u32 control_status_reg;
Michal Simek90663172014-02-12 14:41:19 +010094 struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
Michal Simek5cf4e692014-02-12 14:34:33 +010095
Michal Simek90663172014-02-12 14:41:19 +010096 spin_lock(&xdev->spinlock);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010097
Michal Simek90663172014-02-12 14:41:19 +010098 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010099 control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
Michal Simek90663172014-02-12 14:41:19 +0100100 iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100101
Michal Simek90663172014-02-12 14:41:19 +0100102 spin_unlock(&xdev->spinlock);
Michal Simekd14fd962014-02-12 14:34:32 +0100103
104 return 0;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100105}
106
Michal Simekd14fd962014-02-12 14:34:32 +0100107static const struct watchdog_info xilinx_wdt_ident = {
108 .options = WDIOF_MAGICCLOSE |
109 WDIOF_KEEPALIVEPING,
110 .firmware_version = 1,
111 .identity = WATCHDOG_NAME,
112};
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100113
Michal Simekd14fd962014-02-12 14:34:32 +0100114static const struct watchdog_ops xilinx_wdt_ops = {
115 .owner = THIS_MODULE,
116 .start = xilinx_wdt_start,
117 .stop = xilinx_wdt_stop,
118 .ping = xilinx_wdt_keepalive,
119};
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100120
Michal Simek90663172014-02-12 14:41:19 +0100121static u32 xwdt_selftest(struct xwdt_device *xdev)
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100122{
123 int i;
124 u32 timer_value1;
125 u32 timer_value2;
126
Michal Simek90663172014-02-12 14:41:19 +0100127 spin_lock(&xdev->spinlock);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100128
Michal Simek90663172014-02-12 14:41:19 +0100129 timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
130 timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100131
132 for (i = 0;
133 ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
134 (timer_value2 == timer_value1)); i++) {
Michal Simek90663172014-02-12 14:41:19 +0100135 timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100136 }
137
Michal Simek90663172014-02-12 14:41:19 +0100138 spin_unlock(&xdev->spinlock);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100139
140 if (timer_value2 != timer_value1)
141 return ~XWT_TIMER_FAILED;
142 else
143 return XWT_TIMER_FAILED;
144}
145
Bill Pemberton2d991a12012-11-19 13:21:41 -0500146static int xwdt_probe(struct platform_device *pdev)
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100147{
148 int rc;
Michal Simek8d6a1402014-02-12 14:41:25 +0100149 u32 pfreq = 0, enable_once = 0;
Michal Simekf06cdfd2014-02-12 14:34:34 +0100150 struct resource *res;
Michal Simek90663172014-02-12 14:41:19 +0100151 struct xwdt_device *xdev;
Michal Simek90663172014-02-12 14:41:19 +0100152 struct watchdog_device *xilinx_wdt_wdd;
153
154 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
155 if (!xdev)
156 return -ENOMEM;
157
158 xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
159 xilinx_wdt_wdd->info = &xilinx_wdt_ident;
160 xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
161 xilinx_wdt_wdd->parent = &pdev->dev;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100162
Michal Simekf06cdfd2014-02-12 14:34:34 +0100163 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Michal Simek90663172014-02-12 14:41:19 +0100164 xdev->base = devm_ioremap_resource(&pdev->dev, res);
165 if (IS_ERR(xdev->base))
166 return PTR_ERR(xdev->base);
Michal Simekf06cdfd2014-02-12 14:34:34 +0100167
Michal Simek2e79a362014-02-12 14:41:21 +0100168 rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &pfreq);
Michal Simek8d6a1402014-02-12 14:41:25 +0100169 if (rc)
Michal Simek4c7fbbc2014-02-12 14:41:20 +0100170 dev_warn(&pdev->dev,
171 "The watchdog clock frequency cannot be obtained\n");
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100172
Michal Simek2e79a362014-02-12 14:41:21 +0100173 rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval",
174 &xdev->wdt_interval);
Michal Simek8d6a1402014-02-12 14:41:25 +0100175 if (rc)
Michal Simek4c7fbbc2014-02-12 14:41:20 +0100176 dev_warn(&pdev->dev,
177 "Parameter \"xlnx,wdt-interval\" not found\n");
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100178
Michal Simek2e79a362014-02-12 14:41:21 +0100179 rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-enable-once",
180 &enable_once);
181 if (rc)
Michal Simek4c7fbbc2014-02-12 14:41:20 +0100182 dev_warn(&pdev->dev,
183 "Parameter \"xlnx,wdt-enable-once\" not found\n");
Michal Simek2e79a362014-02-12 14:41:21 +0100184
185 watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100186
Michal Simek75b3c5a2014-02-12 14:41:22 +0100187 /*
188 * Twice of the 2^wdt_interval / freq because the first wdt overflow is
189 * ignored (interrupt), reset is only generated at second wdt overflow
190 */
Michal Simek8d6a1402014-02-12 14:41:25 +0100191 if (pfreq && xdev->wdt_interval)
Michal Simek90663172014-02-12 14:41:19 +0100192 xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
Michal Simek2e79a362014-02-12 14:41:21 +0100193 pfreq);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100194
Michal Simek90663172014-02-12 14:41:19 +0100195 spin_lock_init(&xdev->spinlock);
196 watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
197
198 rc = xwdt_selftest(xdev);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100199 if (rc == XWT_TIMER_FAILED) {
Michal Simek4c7fbbc2014-02-12 14:41:20 +0100200 dev_err(&pdev->dev, "SelfTest routine error\n");
Michal Simekf06cdfd2014-02-12 14:34:34 +0100201 return rc;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100202 }
203
Michal Simek90663172014-02-12 14:41:19 +0100204 rc = watchdog_register_device(xilinx_wdt_wdd);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100205 if (rc) {
Michal Simek4c7fbbc2014-02-12 14:41:20 +0100206 dev_err(&pdev->dev, "Cannot register watchdog (err=%d)\n", rc);
Michal Simekf06cdfd2014-02-12 14:34:34 +0100207 return rc;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100208 }
209
Michal Simekd14fd962014-02-12 14:34:32 +0100210 dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
Michal Simek90663172014-02-12 14:41:19 +0100211 xdev->base, xilinx_wdt_wdd->timeout);
212
213 platform_set_drvdata(pdev, xdev);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100214
215 return 0;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100216}
217
Michal Simek90663172014-02-12 14:41:19 +0100218static int xwdt_remove(struct platform_device *pdev)
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100219{
Michal Simek90663172014-02-12 14:41:19 +0100220 struct xwdt_device *xdev = platform_get_drvdata(pdev);
221
222 watchdog_unregister_device(&xdev->xilinx_wdt_wdd);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100223
224 return 0;
225}
226
227/* Match table for of_platform binding */
Jingoo Han9ebf1852014-05-07 17:42:22 +0900228static const struct of_device_id xwdt_of_match[] = {
Michal Simek8fce9b32013-05-31 07:56:34 +0200229 { .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100230 { .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
231 {},
232};
233MODULE_DEVICE_TABLE(of, xwdt_of_match);
234
235static struct platform_driver xwdt_driver = {
236 .probe = xwdt_probe,
Bill Pemberton82268712012-11-19 13:21:12 -0500237 .remove = xwdt_remove,
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100238 .driver = {
239 .owner = THIS_MODULE,
240 .name = WATCHDOG_NAME,
241 .of_match_table = xwdt_of_match,
242 },
243};
244
Axel Linb8ec6112011-11-29 13:56:27 +0800245module_platform_driver(xwdt_driver);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100246
247MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
248MODULE_DESCRIPTION("Xilinx Watchdog driver");
Michal Simek9419c072013-05-31 07:56:33 +0200249MODULE_LICENSE("GPL v2");