blob: 809d3385df7d5787a5dcb81f5ea38070c3bc66ad [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
Alan Cox28e21c82007-04-26 00:19:25 -070011 * Portions Copyright (C) 2005-2006 MontaVista Software, Inc.
Jeff Garzik669a5db2006-08-29 18:12:40 -040012 *
13 *
14 * TODO
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 * Work out best PLL policy
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt3x2n"
Jeff Garzika0fcdc02007-03-09 07:24:15 -050028#define DRV_VERSION "0.3.3"
Jeff Garzik669a5db2006-08-29 18:12:40 -040029
30enum {
31 HPT_PCI_FAST = (1 << 31),
32 PCI66 = (1 << 1),
33 USE_DPLL = (1 << 0)
34};
35
36struct hpt_clock {
37 u8 xfer_speed;
38 u32 timing;
39};
40
41struct hpt_chip {
42 const char *name;
43 struct hpt_clock *clocks[3];
44};
45
46/* key for bus clock timings
47 * bit
48 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
49 * DMA. cycles = value + 1
50 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
51 * DMA. cycles = value + 1
52 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
53 * register access.
54 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
55 * register access.
56 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
57 * during task file register access.
58 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
59 * xfer.
60 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
61 * register access.
62 * 28 UDMA enable
63 * 29 DMA enable
64 * 30 PIO_MST enable. if set, the chip is in bus master mode during
65 * PIO.
66 * 31 FIFO enable.
67 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040068
Jeff Garzik669a5db2006-08-29 18:12:40 -040069/* 66MHz DPLL clocks */
70
71static struct hpt_clock hpt3x2n_clocks[] = {
72 { XFER_UDMA_7, 0x1c869c62 },
73 { XFER_UDMA_6, 0x1c869c62 },
74 { XFER_UDMA_5, 0x1c8a9c62 },
75 { XFER_UDMA_4, 0x1c8a9c62 },
76 { XFER_UDMA_3, 0x1c8e9c62 },
77 { XFER_UDMA_2, 0x1c929c62 },
78 { XFER_UDMA_1, 0x1c9a9c62 },
79 { XFER_UDMA_0, 0x1c829c62 },
80
81 { XFER_MW_DMA_2, 0x2c829c62 },
82 { XFER_MW_DMA_1, 0x2c829c66 },
83 { XFER_MW_DMA_0, 0x2c829d2c },
84
85 { XFER_PIO_4, 0x0c829c62 },
86 { XFER_PIO_3, 0x0c829c84 },
87 { XFER_PIO_2, 0x0c829ca6 },
88 { XFER_PIO_1, 0x0d029d26 },
89 { XFER_PIO_0, 0x0d029d5e },
90 { 0, 0x0d029d5e }
91};
92
93/**
94 * hpt3x2n_find_mode - reset the hpt3x2n bus
95 * @ap: ATA port
96 * @speed: transfer mode
97 *
98 * Return the 32bit register programming information for this channel
99 * that matches the speed provided. For the moment the clocks table
100 * is hard coded but easy to change. This will be needed if we use
101 * different DPLLs
102 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400103
Jeff Garzik669a5db2006-08-29 18:12:40 -0400104static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
105{
106 struct hpt_clock *clocks = hpt3x2n_clocks;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400107
Jeff Garzik669a5db2006-08-29 18:12:40 -0400108 while(clocks->xfer_speed) {
109 if (clocks->xfer_speed == speed)
110 return clocks->timing;
111 clocks++;
112 }
113 BUG();
114 return 0xffffffffU; /* silence compiler warning */
115}
116
117/**
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500118 * hpt3x2n_cable_detect - Detect the cable type
119 * @ap: ATA port to detect on
Jeff Garzik669a5db2006-08-29 18:12:40 -0400120 *
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500121 * Return the cable type attached to this port
Jeff Garzik669a5db2006-08-29 18:12:40 -0400122 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400123
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500124static int hpt3x2n_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400125{
126 u8 scr2, ata66;
127 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400128
Jeff Garzik669a5db2006-08-29 18:12:40 -0400129 pci_read_config_byte(pdev, 0x5B, &scr2);
130 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
131 /* Cable register now active */
132 pci_read_config_byte(pdev, 0x5A, &ata66);
133 /* Restore state */
134 pci_write_config_byte(pdev, 0x5B, scr2);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400135
Jeff Garzik669a5db2006-08-29 18:12:40 -0400136 if (ata66 & (1 << ap->port_no))
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500137 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400138 else
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500139 return ATA_CBL_PATA80;
140}
Jeff Garzik669a5db2006-08-29 18:12:40 -0400141
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500142/**
143 * hpt3x2n_pre_reset - reset the hpt3x2n bus
144 * @ap: ATA port to reset
Alan Cox28e21c82007-04-26 00:19:25 -0700145 * @deadline: deadline jiffies for the operation
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500146 *
147 * Perform the initial reset handling for the 3x2n series controllers.
148 * Reset the hardware and state machine,
149 */
150
Tejun Heod4b2bab2007-02-02 16:50:52 +0900151static int hpt3xn_pre_reset(struct ata_port *ap, unsigned long deadline)
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500152{
153 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400154 /* Reset the state machine */
Alan Cox28e21c82007-04-26 00:19:25 -0700155 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400156 udelay(100);
Tejun Heod4b2bab2007-02-02 16:50:52 +0900157
158 return ata_std_prereset(ap, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400159}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400160
Jeff Garzik669a5db2006-08-29 18:12:40 -0400161/**
162 * hpt3x2n_error_handler - probe the hpt3x2n bus
163 * @ap: ATA port to reset
164 *
165 * Perform the probe reset handling for the 3x2N
166 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400167
Jeff Garzik669a5db2006-08-29 18:12:40 -0400168static void hpt3x2n_error_handler(struct ata_port *ap)
169{
170 ata_bmdma_drive_eh(ap, hpt3xn_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
171}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400172
Jeff Garzik669a5db2006-08-29 18:12:40 -0400173/**
174 * hpt3x2n_set_piomode - PIO setup
175 * @ap: ATA interface
176 * @adev: device on the interface
177 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400178 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400179 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400180
Jeff Garzik669a5db2006-08-29 18:12:40 -0400181static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
182{
183 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
184 u32 addr1, addr2;
185 u32 reg;
186 u32 mode;
187 u8 fast;
188
189 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
190 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400191
Jeff Garzik669a5db2006-08-29 18:12:40 -0400192 /* Fast interrupt prediction disable, hold off interrupt disable */
193 pci_read_config_byte(pdev, addr2, &fast);
194 fast &= ~0x07;
195 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400196
Jeff Garzik669a5db2006-08-29 18:12:40 -0400197 pci_read_config_dword(pdev, addr1, &reg);
198 mode = hpt3x2n_find_mode(ap, adev->pio_mode);
199 mode &= ~0x8000000; /* No FIFO in PIO */
200 mode &= ~0x30070000; /* Leave config bits alone */
201 reg &= 0x30070000; /* Strip timing bits */
202 pci_write_config_dword(pdev, addr1, reg | mode);
203}
204
205/**
206 * hpt3x2n_set_dmamode - DMA timing setup
207 * @ap: ATA interface
208 * @adev: Device being configured
209 *
210 * Set up the channel for MWDMA or UDMA modes. Much the same as with
211 * PIO, load the mode number and then set MWDMA or UDMA flag.
212 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400213
Jeff Garzik669a5db2006-08-29 18:12:40 -0400214static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
215{
216 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
217 u32 addr1, addr2;
218 u32 reg;
219 u32 mode;
220 u8 fast;
221
222 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
223 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400224
Jeff Garzik669a5db2006-08-29 18:12:40 -0400225 /* Fast interrupt prediction disable, hold off interrupt disable */
226 pci_read_config_byte(pdev, addr2, &fast);
227 fast &= ~0x07;
228 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400229
Jeff Garzik669a5db2006-08-29 18:12:40 -0400230 pci_read_config_dword(pdev, addr1, &reg);
231 mode = hpt3x2n_find_mode(ap, adev->dma_mode);
232 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
233 mode &= ~0xC0000000; /* Leave config bits alone */
234 reg &= 0xC0000000; /* Strip timing bits */
235 pci_write_config_dword(pdev, addr1, reg | mode);
236}
237
238/**
239 * hpt3x2n_bmdma_end - DMA engine stop
240 * @qc: ATA command
241 *
242 * Clean up after the HPT3x2n and later DMA engine
243 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400244
Jeff Garzik669a5db2006-08-29 18:12:40 -0400245static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
246{
247 struct ata_port *ap = qc->ap;
248 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
249 int mscreg = 0x50 + 2 * ap->port_no;
250 u8 bwsr_stat, msc_stat;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400251
Jeff Garzik669a5db2006-08-29 18:12:40 -0400252 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
253 pci_read_config_byte(pdev, mscreg, &msc_stat);
254 if (bwsr_stat & (1 << ap->port_no))
255 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
256 ata_bmdma_stop(qc);
257}
258
259/**
260 * hpt3x2n_set_clock - clock control
261 * @ap: ATA port
262 * @source: 0x21 or 0x23 for PLL or PCI sourced clock
263 *
264 * Switch the ATA bus clock between the PLL and PCI clock sources
265 * while correctly isolating the bus and resetting internal logic
266 *
267 * We must use the DPLL for
268 * - writing
269 * - second channel UDMA7 (SATA ports) or higher
270 * - 66MHz PCI
Jeff Garzik85cd7252006-08-31 00:03:49 -0400271 *
Jeff Garzik669a5db2006-08-29 18:12:40 -0400272 * or we will underclock the device and get reduced performance.
273 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400274
Jeff Garzik669a5db2006-08-29 18:12:40 -0400275static void hpt3x2n_set_clock(struct ata_port *ap, int source)
276{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900277 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400278
Jeff Garzik669a5db2006-08-29 18:12:40 -0400279 /* Tristate the bus */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900280 iowrite8(0x80, bmdma+0x73);
281 iowrite8(0x80, bmdma+0x77);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400282
Jeff Garzik669a5db2006-08-29 18:12:40 -0400283 /* Switch clock and reset channels */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900284 iowrite8(source, bmdma+0x7B);
285 iowrite8(0xC0, bmdma+0x79);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400286
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287 /* Reset state machines */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900288 iowrite8(0x37, bmdma+0x70);
289 iowrite8(0x37, bmdma+0x74);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400290
Jeff Garzik669a5db2006-08-29 18:12:40 -0400291 /* Complete reset */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900292 iowrite8(0x00, bmdma+0x79);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400293
Jeff Garzik669a5db2006-08-29 18:12:40 -0400294 /* Reconnect channels to bus */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900295 iowrite8(0x00, bmdma+0x73);
296 iowrite8(0x00, bmdma+0x77);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400297}
298
299/* Check if our partner interface is busy */
300
301static int hpt3x2n_pair_idle(struct ata_port *ap)
302{
303 struct ata_host *host = ap->host;
304 struct ata_port *pair = host->ports[ap->port_no ^ 1];
Jeff Garzik85cd7252006-08-31 00:03:49 -0400305
Jeff Garzik669a5db2006-08-29 18:12:40 -0400306 if (pair->hsm_task_state == HSM_ST_IDLE)
307 return 1;
308 return 0;
309}
310
Alana52865c2007-01-24 11:51:38 +0000311static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400312{
313 long flags = (long)ap->host->private_data;
314 /* See if we should use the DPLL */
Alana52865c2007-01-24 11:51:38 +0000315 if (writing)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400316 return USE_DPLL; /* Needed for write */
317 if (flags & PCI66)
318 return USE_DPLL; /* Needed at 66Mhz */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400319 return 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400320}
321
322static unsigned int hpt3x2n_qc_issue_prot(struct ata_queued_cmd *qc)
323{
324 struct ata_taskfile *tf = &qc->tf;
325 struct ata_port *ap = qc->ap;
326 int flags = (long)ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400327
Jeff Garzik669a5db2006-08-29 18:12:40 -0400328 if (hpt3x2n_pair_idle(ap)) {
329 int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
330 if ((flags & USE_DPLL) != dpll) {
331 if (dpll == 1)
332 hpt3x2n_set_clock(ap, 0x21);
333 else
334 hpt3x2n_set_clock(ap, 0x23);
335 }
336 }
337 return ata_qc_issue_prot(qc);
338}
339
340static struct scsi_host_template hpt3x2n_sht = {
341 .module = THIS_MODULE,
342 .name = DRV_NAME,
343 .ioctl = ata_scsi_ioctl,
344 .queuecommand = ata_scsi_queuecmd,
345 .can_queue = ATA_DEF_QUEUE,
346 .this_id = ATA_SHT_THIS_ID,
347 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400348 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
349 .emulated = ATA_SHT_EMULATED,
350 .use_clustering = ATA_SHT_USE_CLUSTERING,
351 .proc_name = DRV_NAME,
352 .dma_boundary = ATA_DMA_BOUNDARY,
353 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900354 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400355 .bios_param = ata_std_bios_param,
356};
357
358/*
359 * Configuration for HPT3x2n.
360 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400361
Jeff Garzik669a5db2006-08-29 18:12:40 -0400362static struct ata_port_operations hpt3x2n_port_ops = {
363 .port_disable = ata_port_disable,
364 .set_piomode = hpt3x2n_set_piomode,
365 .set_dmamode = hpt3x2n_set_dmamode,
366 .mode_filter = ata_pci_default_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400367
Jeff Garzik669a5db2006-08-29 18:12:40 -0400368 .tf_load = ata_tf_load,
369 .tf_read = ata_tf_read,
370 .check_status = ata_check_status,
371 .exec_command = ata_exec_command,
372 .dev_select = ata_std_dev_select,
373
374 .freeze = ata_bmdma_freeze,
375 .thaw = ata_bmdma_thaw,
376 .error_handler = hpt3x2n_error_handler,
377 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500378 .cable_detect = hpt3x2n_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400379
380 .bmdma_setup = ata_bmdma_setup,
381 .bmdma_start = ata_bmdma_start,
382 .bmdma_stop = hpt3x2n_bmdma_stop,
383 .bmdma_status = ata_bmdma_status,
384
385 .qc_prep = ata_qc_prep,
386 .qc_issue = hpt3x2n_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400387
Tejun Heo0d5ff562007-02-01 15:06:36 +0900388 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400389
390 .irq_handler = ata_interrupt,
391 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900392 .irq_on = ata_irq_on,
393 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400394
395 .port_start = ata_port_start,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400396};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400397
398/**
399 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400400 * @dev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400401 *
402 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
403 * succeeds
404 */
405
406static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
407{
408 u8 reg5b;
409 u32 reg5c;
410 int tries;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400411
Jeff Garzik669a5db2006-08-29 18:12:40 -0400412 for(tries = 0; tries < 0x5000; tries++) {
413 udelay(50);
414 pci_read_config_byte(dev, 0x5b, &reg5b);
415 if (reg5b & 0x80) {
416 /* See if it stays set */
417 for(tries = 0; tries < 0x1000; tries ++) {
418 pci_read_config_byte(dev, 0x5b, &reg5b);
419 /* Failed ? */
420 if ((reg5b & 0x80) == 0)
421 return 0;
422 }
423 /* Turn off tuning, we have the DPLL set */
424 pci_read_config_dword(dev, 0x5c, &reg5c);
425 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
426 return 1;
427 }
428 }
429 /* Never went stable */
430 return 0;
431}
432
433static int hpt3x2n_pci_clock(struct pci_dev *pdev)
434{
435 unsigned long freq;
436 u32 fcnt;
Alan Cox28e21c82007-04-26 00:19:25 -0700437 unsigned long iobase = pci_resource_start(pdev, 4);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400438
Alan Cox28e21c82007-04-26 00:19:25 -0700439 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400440 if ((fcnt >> 12) != 0xABCDE) {
441 printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
442 return 33; /* Not BIOS set */
443 }
444 fcnt &= 0x1FF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400445
Jeff Garzik669a5db2006-08-29 18:12:40 -0400446 freq = (fcnt * 77) / 192;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400447
Jeff Garzik669a5db2006-08-29 18:12:40 -0400448 /* Clamp to bands */
449 if (freq < 40)
450 return 33;
451 if (freq < 45)
452 return 40;
453 if (freq < 55)
454 return 50;
455 return 66;
456}
457
458/**
459 * hpt3x2n_init_one - Initialise an HPT37X/302
460 * @dev: PCI device
461 * @id: Entry in match table
462 *
463 * Initialise an HPT3x2n device. There are some interesting complications
464 * here. Firstly the chip may report 366 and be one of several variants.
465 * Secondly all the timings depend on the clock for the chip which we must
466 * detect and look up
467 *
468 * This is the known chip mappings. It may be missing a couple of later
469 * releases.
470 *
471 * Chip version PCI Rev Notes
472 * HPT372 4 (HPT366) 5 Other driver
473 * HPT372N 4 (HPT366) 6 UDMA133
474 * HPT372 5 (HPT372) 1 Other driver
475 * HPT372N 5 (HPT372) 2 UDMA133
476 * HPT302 6 (HPT302) * Other driver
477 * HPT302N 6 (HPT302) > 1 UDMA133
478 * HPT371 7 (HPT371) * Other driver
479 * HPT371N 7 (HPT371) > 1 UDMA133
480 * HPT374 8 (HPT374) * Other driver
481 * HPT372N 9 (HPT372N) * UDMA133
482 *
483 * (1) UDMA133 support depends on the bus clock
484 *
485 * To pin down HPT371N
486 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400487
Jeff Garzik669a5db2006-08-29 18:12:40 -0400488static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
489{
490 /* HPT372N and friends - UDMA133 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200491 static const struct ata_port_info info = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400492 .sht = &hpt3x2n_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400493 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400494 .pio_mask = 0x1f,
495 .mwdma_mask = 0x07,
496 .udma_mask = 0x7f,
497 .port_ops = &hpt3x2n_port_ops
498 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200499 struct ata_port_info port = info;
500 const struct ata_port_info *ppi[] = { &port, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400501
502 u8 irqmask;
503 u32 class_rev;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400504
Jeff Garzik669a5db2006-08-29 18:12:40 -0400505 unsigned int pci_mhz;
506 unsigned int f_low, f_high;
507 int adjust;
Alan Cox28e21c82007-04-26 00:19:25 -0700508 unsigned long iobase = pci_resource_start(dev, 4);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400509
Jeff Garzik669a5db2006-08-29 18:12:40 -0400510 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
511 class_rev &= 0xFF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400512
Jeff Garzik669a5db2006-08-29 18:12:40 -0400513 switch(dev->device) {
514 case PCI_DEVICE_ID_TTI_HPT366:
515 if (class_rev < 6)
516 return -ENODEV;
517 break;
Alan Cox28e21c82007-04-26 00:19:25 -0700518 case PCI_DEVICE_ID_TTI_HPT371:
519 if (class_rev < 2)
520 return -ENODEV;
521 /* 371N if rev > 1 */
522 break;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400523 case PCI_DEVICE_ID_TTI_HPT372:
Alan Cox824cf332007-05-21 14:57:01 +0100524 /* 372N if rev >= 2*/
525 if (class_rev < 2)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400526 return -ENODEV;
527 break;
528 case PCI_DEVICE_ID_TTI_HPT302:
529 if (class_rev < 2)
530 return -ENODEV;
531 break;
532 case PCI_DEVICE_ID_TTI_HPT372N:
533 break;
534 default:
535 printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
536 return -ENODEV;
537 }
538
539 /* Ok so this is a chip we support */
540
541 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
542 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
543 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
544 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
545
546 pci_read_config_byte(dev, 0x5A, &irqmask);
547 irqmask &= ~0x10;
548 pci_write_config_byte(dev, 0x5a, irqmask);
549
Alan Cox28e21c82007-04-26 00:19:25 -0700550 /*
551 * HPT371 chips physically have only one channel, the secondary one,
552 * but the primary channel registers do exist! Go figure...
553 * So, we manually disable the non-existing channel here
554 * (if the BIOS hasn't done this already).
555 */
556 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
557 u8 mcr1;
558 pci_read_config_byte(dev, 0x50, &mcr1);
559 mcr1 &= ~0x04;
560 pci_write_config_byte(dev, 0x50, mcr1);
561 }
562
Jeff Garzik669a5db2006-08-29 18:12:40 -0400563 /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
564 50 for UDMA100. Right now we always use 66 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400565
Jeff Garzik669a5db2006-08-29 18:12:40 -0400566 pci_mhz = hpt3x2n_pci_clock(dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400567
Jeff Garzik669a5db2006-08-29 18:12:40 -0400568 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
569 f_high = f_low + 2; /* Tolerance */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400570
Jeff Garzik669a5db2006-08-29 18:12:40 -0400571 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
572 /* PLL clock */
573 pci_write_config_byte(dev, 0x5B, 0x21);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400574
Jeff Garzik669a5db2006-08-29 18:12:40 -0400575 /* Unlike the 37x we don't try jiggling the frequency */
576 for(adjust = 0; adjust < 8; adjust++) {
577 if (hpt3xn_calibrate_dpll(dev))
578 break;
579 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
580 }
Alan Cox28e21c82007-04-26 00:19:25 -0700581 if (adjust == 8) {
582 printk(KERN_WARNING "hpt3x2n: DPLL did not stabilize.\n");
583 return -ENODEV;
584 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400585
586 /* Set our private data up. We only need a few flags so we use
587 it directly */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200588 port.private_data = NULL;
Alan Cox28e21c82007-04-26 00:19:25 -0700589 if (pci_mhz > 60) {
Tejun Heo1626aeb2007-05-04 12:43:58 +0200590 port.private_data = (void *)PCI66;
Alan Cox28e21c82007-04-26 00:19:25 -0700591 /*
592 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
593 * the MISC. register to stretch the UltraDMA Tss timing.
594 * NOTE: This register is only writeable via I/O space.
595 */
596 if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
597 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
598 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400599
Jeff Garzik669a5db2006-08-29 18:12:40 -0400600 /* Now kick off ATA set up */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200601 return ata_pci_init_one(dev, ppi);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400602}
603
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400604static const struct pci_device_id hpt3x2n[] = {
605 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
Alan Cox28e21c82007-04-26 00:19:25 -0700606 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400607 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
608 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
609 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
610
611 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400612};
613
614static struct pci_driver hpt3x2n_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400615 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400616 .id_table = hpt3x2n,
617 .probe = hpt3x2n_init_one,
618 .remove = ata_pci_remove_one
619};
620
621static int __init hpt3x2n_init(void)
622{
623 return pci_register_driver(&hpt3x2n_pci_driver);
624}
625
Jeff Garzik669a5db2006-08-29 18:12:40 -0400626static void __exit hpt3x2n_exit(void)
627{
628 pci_unregister_driver(&hpt3x2n_pci_driver);
629}
630
Jeff Garzik669a5db2006-08-29 18:12:40 -0400631MODULE_AUTHOR("Alan Cox");
632MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
633MODULE_LICENSE("GPL");
634MODULE_DEVICE_TABLE(pci, hpt3x2n);
635MODULE_VERSION(DRV_VERSION);
636
637module_init(hpt3x2n_init);
638module_exit(hpt3x2n_exit);