Jean-Christop PLAGNIOL-VILLARD | 6d803ba | 2010-11-17 10:04:33 +0100 | [diff] [blame] | 1 | |
| 2 | config CLKDEV_LOOKUP |
| 3 | bool |
| 4 | select HAVE_CLK |
Kyungmin Park | aa3831c | 2011-07-18 16:34:54 +0900 | [diff] [blame] | 5 | |
Shawn Guo | 5c77f56 | 2011-12-20 14:46:38 +0800 | [diff] [blame] | 6 | config HAVE_CLK_PREPARE |
| 7 | bool |
| 8 | |
Arnd Bergmann | 8fb61e3 | 2012-03-17 21:10:51 +0000 | [diff] [blame] | 9 | config COMMON_CLK |
| 10 | bool |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 11 | select HAVE_CLK_PREPARE |
Rob Herring | 01033be | 2012-04-09 15:24:58 -0500 | [diff] [blame] | 12 | select CLKDEV_LOOKUP |
Pranith Kumar | 83fe27e | 2014-12-05 11:24:45 -0500 | [diff] [blame] | 13 | select SRCU |
Andy Shevchenko | 0777591 | 2015-09-22 18:54:11 +0300 | [diff] [blame] | 14 | select RATIONAL |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 15 | ---help--- |
| 16 | The common clock framework is a single definition of struct |
| 17 | clk, useful across many platforms, as well as an |
| 18 | implementation of the clock API in include/linux/clk.h. |
| 19 | Architectures utilizing the common struct clk should select |
Arnd Bergmann | 8fb61e3 | 2012-03-17 21:10:51 +0000 | [diff] [blame] | 20 | this option. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 21 | |
Arnd Bergmann | 8fb61e3 | 2012-03-17 21:10:51 +0000 | [diff] [blame] | 22 | menu "Common Clock Framework" |
| 23 | depends on COMMON_CLK |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 24 | |
Mark Brown | f05259a | 2012-05-17 10:04:57 +0100 | [diff] [blame] | 25 | config COMMON_CLK_WM831X |
| 26 | tristate "Clock driver for WM831x/2x PMICs" |
| 27 | depends on MFD_WM831X |
| 28 | ---help--- |
| 29 | Supports the clocking subsystem of the WM831x/2x series of |
Masanari Iida | fe4e437 | 2014-10-17 00:09:24 +0900 | [diff] [blame] | 30 | PMICs from Wolfson Microelectronics. |
Mark Brown | f05259a | 2012-05-17 10:04:57 +0100 | [diff] [blame] | 31 | |
Pawel Moll | 5ee2b87 | 2013-09-17 17:16:15 +0100 | [diff] [blame] | 32 | source "drivers/clk/versatile/Kconfig" |
Linus Walleij | f9a6aa4 | 2012-08-06 18:32:08 +0200 | [diff] [blame] | 33 | |
Javier Martinez Canillas | 5dbbb00 | 2014-08-18 10:33:00 +0200 | [diff] [blame] | 34 | config COMMON_CLK_MAX_GEN |
| 35 | bool |
| 36 | |
Jonghwa Lee | 73118e6 | 2012-08-28 17:54:28 +0900 | [diff] [blame] | 37 | config COMMON_CLK_MAX77686 |
| 38 | tristate "Clock driver for Maxim 77686 MFD" |
| 39 | depends on MFD_MAX77686 |
Javier Martinez Canillas | 1887d69 | 2014-08-18 10:33:01 +0200 | [diff] [blame] | 40 | select COMMON_CLK_MAX_GEN |
Jonghwa Lee | 73118e6 | 2012-08-28 17:54:28 +0900 | [diff] [blame] | 41 | ---help--- |
| 42 | This driver supports Maxim 77686 crystal oscillator clock. |
| 43 | |
Javier Martinez Canillas | 83ccf16 | 2014-08-18 10:33:03 +0200 | [diff] [blame] | 44 | config COMMON_CLK_MAX77802 |
| 45 | tristate "Clock driver for Maxim 77802 PMIC" |
| 46 | depends on MFD_MAX77686 |
| 47 | select COMMON_CLK_MAX_GEN |
| 48 | ---help--- |
| 49 | This driver supports Maxim 77802 crystal oscillator clock. |
| 50 | |
Chris Zhong | 038b892 | 2014-10-13 15:52:44 -0700 | [diff] [blame] | 51 | config COMMON_CLK_RK808 |
| 52 | tristate "Clock driver for RK808" |
| 53 | depends on MFD_RK808 |
| 54 | ---help--- |
| 55 | This driver supports RK808 crystal oscillator clock. These |
| 56 | multi-function devices have two fixed-rate oscillators, |
| 57 | clocked at 32KHz each. Clkout1 is always on, Clkout2 can off |
| 58 | by control register. |
| 59 | |
Sudeep Holla | cd52c2a | 2015-03-30 10:59:52 +0100 | [diff] [blame] | 60 | config COMMON_CLK_SCPI |
| 61 | tristate "Clock driver controlled via SCPI interface" |
| 62 | depends on ARM_SCPI_PROTOCOL || COMPILE_TEST |
| 63 | ---help--- |
| 64 | This driver provides support for clocks that are controlled |
| 65 | by firmware that implements the SCPI interface. |
| 66 | |
| 67 | This driver uses SCPI Message Protocol to interact with the |
| 68 | firmware providing all the clock controls. |
| 69 | |
Sebastian Hesselbarth | 9abd5f0 | 2013-04-11 21:42:29 +0200 | [diff] [blame] | 70 | config COMMON_CLK_SI5351 |
| 71 | tristate "Clock driver for SiLabs 5351A/B/C" |
| 72 | depends on I2C |
| 73 | select REGMAP_I2C |
| 74 | select RATIONAL |
| 75 | ---help--- |
| 76 | This driver supports Silicon Labs 5351A/B/C programmable clock |
| 77 | generators. |
| 78 | |
Mike Looijmans | 8ce20e6 | 2015-10-02 09:15:29 +0200 | [diff] [blame] | 79 | config COMMON_CLK_SI514 |
| 80 | tristate "Clock driver for SiLabs 514 devices" |
| 81 | depends on I2C |
| 82 | depends on OF |
| 83 | select REGMAP_I2C |
| 84 | help |
| 85 | ---help--- |
| 86 | This driver supports the Silicon Labs 514 programmable clock |
| 87 | generator. |
| 88 | |
Soren Brinkmann | 1459c83 | 2013-09-21 16:40:39 -0700 | [diff] [blame] | 89 | config COMMON_CLK_SI570 |
| 90 | tristate "Clock driver for SiLabs 570 and compatible devices" |
| 91 | depends on I2C |
| 92 | depends on OF |
| 93 | select REGMAP_I2C |
| 94 | help |
| 95 | ---help--- |
| 96 | This driver supports Silicon Labs 570/571/598/599 programmable |
| 97 | clock generators. |
| 98 | |
Mike Looijmans | c7d5a46 | 2015-11-03 12:55:54 +0100 | [diff] [blame] | 99 | config COMMON_CLK_CDCE706 |
| 100 | tristate "Clock driver for TI CDCE706 clock synthesizer" |
| 101 | depends on I2C |
| 102 | select REGMAP_I2C |
| 103 | select RATIONAL |
| 104 | ---help--- |
| 105 | This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. |
| 106 | |
Mike Looijmans | 19fbbbb | 2015-06-03 07:25:19 +0200 | [diff] [blame] | 107 | config COMMON_CLK_CDCE925 |
| 108 | tristate "Clock driver for TI CDCE925 devices" |
| 109 | depends on I2C |
| 110 | depends on OF |
| 111 | select REGMAP_I2C |
| 112 | help |
| 113 | ---help--- |
| 114 | This driver supports the TI CDCE925 programmable clock synthesizer. |
| 115 | The chip contains two PLLs with spread-spectrum clocking support and |
| 116 | five output dividers. The driver only supports the following setup, |
| 117 | and uses a fixed setting for the output muxes. |
| 118 | Y1 is derived from the input clock |
| 119 | Y2 and Y3 derive from PLL1 |
| 120 | Y4 and Y5 derive from PLL2 |
| 121 | Given a target output frequency, the driver will set the PLL and |
| 122 | divider to best approximate the desired output. |
| 123 | |
Kuninori Morimoto | 64dfbe2 | 2015-11-10 01:15:09 +0000 | [diff] [blame] | 124 | config COMMON_CLK_CS2000_CP |
| 125 | tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier" |
| 126 | depends on I2C |
| 127 | help |
| 128 | If you say yes here you get support for the CS2000 clock multiplier. |
| 129 | |
Yadwinder Singh Brar | 7cc560d | 2013-07-07 17:14:20 +0530 | [diff] [blame] | 130 | config COMMON_CLK_S2MPS11 |
Krzysztof Kozlowski | e8b60a4 | 2014-05-21 13:23:01 +0200 | [diff] [blame] | 131 | tristate "Clock driver for S2MPS1X/S5M8767 MFD" |
Yadwinder Singh Brar | 7cc560d | 2013-07-07 17:14:20 +0530 | [diff] [blame] | 132 | depends on MFD_SEC_CORE |
| 133 | ---help--- |
Krzysztof Kozlowski | e8b60a4 | 2014-05-21 13:23:01 +0200 | [diff] [blame] | 134 | This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator |
| 135 | clock. These multi-function devices have two (S2MPS14) or three |
| 136 | (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each. |
Yadwinder Singh Brar | 7cc560d | 2013-07-07 17:14:20 +0530 | [diff] [blame] | 137 | |
Peter Ujfalusi | f9f8c04 | 2012-09-14 17:30:27 +0300 | [diff] [blame] | 138 | config CLK_TWL6040 |
| 139 | tristate "External McPDM functional clock from twl6040" |
| 140 | depends on TWL6040_CORE |
| 141 | ---help--- |
| 142 | Enable the external functional clock support on OMAP4+ platforms for |
| 143 | McPDM. McPDM module is using the external bit clock on the McPDM bus |
| 144 | as functional clock. |
| 145 | |
Lars-Peter Clausen | 0e646c5 | 2013-03-11 16:22:29 +0100 | [diff] [blame] | 146 | config COMMON_CLK_AXI_CLKGEN |
| 147 | tristate "AXI clkgen driver" |
Javier Martinez Canillas | 4a7748c | 2015-10-13 16:18:18 +0200 | [diff] [blame] | 148 | depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST |
Lars-Peter Clausen | 0e646c5 | 2013-03-11 16:22:29 +0100 | [diff] [blame] | 149 | help |
| 150 | ---help--- |
| 151 | Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx |
| 152 | FPGAs. It is commonly used in Analog Devices' reference designs. |
| 153 | |
Tang Yuantian | 93a17c0 | 2015-01-15 14:03:41 +0800 | [diff] [blame] | 154 | config CLK_QORIQ |
| 155 | bool "Clock driver for Freescale QorIQ platforms" |
Linus Torvalds | 2f4bf52 | 2015-11-05 23:38:43 -0800 | [diff] [blame] | 156 | depends on (PPC_E500MC || ARM || ARM64 || COMPILE_TEST) && OF |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 157 | ---help--- |
Tang Yuantian | 93a17c0 | 2015-01-15 14:03:41 +0800 | [diff] [blame] | 158 | This adds the clock driver support for Freescale QorIQ platforms |
| 159 | using common clock framework. |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 160 | |
Loc Ho | 308964c | 2013-06-26 11:56:09 -0600 | [diff] [blame] | 161 | config COMMON_CLK_XGENE |
| 162 | bool "Clock driver for APM XGene SoC" |
| 163 | default y |
Javier Martinez Canillas | 4a7748c | 2015-10-13 16:18:18 +0200 | [diff] [blame] | 164 | depends on ARM64 || COMPILE_TEST |
Loc Ho | 308964c | 2013-06-26 11:56:09 -0600 | [diff] [blame] | 165 | ---help--- |
| 166 | Sypport for the APM X-Gene SoC reference, PLL, and device clocks. |
| 167 | |
Santosh Shilimkar | 6cfc229 | 2013-09-25 21:18:15 -0400 | [diff] [blame] | 168 | config COMMON_CLK_KEYSTONE |
| 169 | tristate "Clock drivers for Keystone based SOCs" |
Javier Martinez Canillas | 4a7748c | 2015-10-13 16:18:18 +0200 | [diff] [blame] | 170 | depends on (ARCH_KEYSTONE || COMPILE_TEST) && OF |
Santosh Shilimkar | 6cfc229 | 2013-09-25 21:18:15 -0400 | [diff] [blame] | 171 | ---help--- |
| 172 | Supports clock drivers for Keystone based SOCs. These SOCs have local |
| 173 | a power sleep control module that gate the clock to the IPs and PLLs. |
| 174 | |
Vladimir Zapolskiy | f7c82a6 | 2015-12-06 12:45:57 +0200 | [diff] [blame] | 175 | config COMMON_CLK_NXP |
| 176 | def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX) |
| 177 | select REGMAP_MMIO if ARCH_LPC32XX |
| 178 | ---help--- |
| 179 | Support for clock providers on NXP platforms. |
| 180 | |
Peter Ujfalusi | 942d1d6 | 2014-06-27 09:01:11 +0300 | [diff] [blame] | 181 | config COMMON_CLK_PALMAS |
| 182 | tristate "Clock driver for TI Palmas devices" |
| 183 | depends on MFD_PALMAS |
| 184 | ---help--- |
| 185 | This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO |
| 186 | using common clock framework. |
| 187 | |
Philipp Zabel | 9a74ccd | 2015-02-13 20:18:52 +0100 | [diff] [blame] | 188 | config COMMON_CLK_PWM |
| 189 | tristate "Clock driver for PWMs used as clock outputs" |
| 190 | depends on PWM |
| 191 | ---help--- |
| 192 | Adapter driver so that any PWM output can be (mis)used as clock signal |
| 193 | at 50% duty cycle. |
| 194 | |
Robert Jarzmik | 98d147f | 2014-10-01 23:39:29 +0200 | [diff] [blame] | 195 | config COMMON_CLK_PXA |
| 196 | def_bool COMMON_CLK && ARCH_PXA |
| 197 | ---help--- |
Mike Looijmans | 048c58b | 2015-11-03 12:55:53 +0100 | [diff] [blame] | 198 | Support for the Marvell PXA SoC. |
Robert Jarzmik | 98d147f | 2014-10-01 23:39:29 +0200 | [diff] [blame] | 199 | |
Purna Chandra Mandal | ce6e118 | 2016-05-13 13:22:40 +0530 | [diff] [blame] | 200 | config COMMON_CLK_PIC32 |
| 201 | def_bool COMMON_CLK && MACH_PIC32 |
| 202 | |
Neil Armstrong | 0bbd72b | 2016-04-18 12:01:35 +0200 | [diff] [blame] | 203 | config COMMON_CLK_OXNAS |
| 204 | bool "Clock driver for the OXNAS SoC Family" |
| 205 | select MFD_SYSCON |
| 206 | ---help--- |
| 207 | Support for the OXNAS SoC Family clocks. |
| 208 | |
Stephen Boyd | 64a12c5 | 2015-05-14 17:38:21 -0700 | [diff] [blame] | 209 | source "drivers/clk/bcm/Kconfig" |
Bintian Wang | 72ea486 | 2015-05-29 10:08:38 +0800 | [diff] [blame] | 210 | source "drivers/clk/hisilicon/Kconfig" |
Sebastian Hesselbarth | 97fa4cf | 2012-11-17 15:22:22 +0100 | [diff] [blame] | 211 | source "drivers/clk/mvebu/Kconfig" |
James Liao | b9e65eb | 2016-01-28 16:58:57 +0800 | [diff] [blame] | 212 | source "drivers/clk/qcom/Kconfig" |
Geert Uytterhoeven | a5bd7f7 | 2016-04-13 11:08:42 +0200 | [diff] [blame] | 213 | source "drivers/clk/renesas/Kconfig" |
Pankaj Dubey | 4ce9b85 | 2014-05-08 13:07:08 +0900 | [diff] [blame] | 214 | source "drivers/clk/samsung/Kconfig" |
Maxime Ripard | 1d80c14 | 2016-06-29 21:05:23 +0200 | [diff] [blame^] | 215 | source "drivers/clk/sunxi-ng/Kconfig" |
Thierry Reding | 31b52ba | 2015-04-01 09:10:58 +0200 | [diff] [blame] | 216 | source "drivers/clk/tegra/Kconfig" |
Tony Lindgren | 2133049 | 2016-02-26 09:35:05 -0800 | [diff] [blame] | 217 | source "drivers/clk/ti/Kconfig" |
James Liao | b9e65eb | 2016-01-28 16:58:57 +0800 | [diff] [blame] | 218 | |
| 219 | endmenu |