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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * IRQ vector handles
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
9 */
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/irq.h>
13
14#include <asm/i8259.h>
15#include <asm/irq_cpu.h>
16#include <asm/gt64120.h>
17#include <asm/ptrace.h>
18
19#include <asm/cobalt/cobalt.h>
20
21extern void cobalt_handle_int(void);
22
23/*
24 * We have two types of interrupts that we handle, ones that come in through
25 * the CPU interrupt lines, and ones that come in on the via chip. The CPU
26 * mappings are:
27 *
28 * 16, - Software interrupt 0 (unused) IE_SW0
29 * 17 - Software interrupt 1 (unused) IE_SW0
30 * 18 - Galileo chip (timer) IE_IRQ0
31 * 19 - Tulip 0 + NCR SCSI IE_IRQ1
32 * 20 - Tulip 1 IE_IRQ2
33 * 21 - 16550 UART IE_IRQ3
34 * 22 - VIA southbridge PIC IE_IRQ4
35 * 23 - unused IE_IRQ5
36 *
37 * The VIA chip is a master/slave 8259 setup and has the following interrupts:
38 *
39 * 8 - RTC
40 * 9 - PCI
41 * 14 - IDE0
42 * 15 - IDE1
43 */
44
45asmlinkage void cobalt_irq(struct pt_regs *regs)
46{
47 unsigned int pending = read_c0_status() & read_c0_cause();
48
49 if (pending & CAUSEF_IP2) { /* int 18 */
50 unsigned long irq_src = GALILEO_INL(GT_INTRCAUSE_OFS);
51
52 /* Check for timer irq ... */
53 if (irq_src & GALILEO_T0EXP) {
54 /* Clear the int line */
55 GALILEO_OUTL(0, GT_INTRCAUSE_OFS);
56 do_IRQ(COBALT_TIMER_IRQ, regs);
57 }
58 return;
59 }
60
61 if (pending & CAUSEF_IP6) { /* int 22 */
62 int irq = i8259_irq();
63
64 if (irq >= 0)
65 do_IRQ(irq, regs);
66 return;
67 }
68
69 if (pending & CAUSEF_IP3) { /* int 19 */
70 do_IRQ(COBALT_ETH0_IRQ, regs);
71 return;
72 }
73
74 if (pending & CAUSEF_IP4) { /* int 20 */
75 do_IRQ(COBALT_ETH1_IRQ, regs);
76 return;
77 }
78
79 if (pending & CAUSEF_IP5) { /* int 21 */
80 do_IRQ(COBALT_SERIAL_IRQ, regs);
81 return;
82 }
83
84 if (pending & CAUSEF_IP7) { /* int 23 */
85 do_IRQ(COBALT_QUBE_SLOT_IRQ, regs);
86 return;
87 }
88}
89
90void __init arch_init_irq(void)
91{
92 set_except_vector(0, cobalt_handle_int);
93
94 init_i8259_irqs(); /* 0 ... 15 */
95 mips_cpu_irq_init(16); /* 16 ... 23 */
96
97 /*
98 * Mask all cpu interrupts
99 * (except IE4, we already masked those at VIA level)
100 */
101 change_c0_status(ST0_IM, IE_IRQ4);
102}