Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * linux/drivers/serial/pmac_zilog.c |
| 3 | * |
| 4 | * Driver for PowerMac Z85c30 based ESCC cell found in the |
| 5 | * "macio" ASICs of various PowerMac models |
| 6 | * |
| 7 | * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) |
| 8 | * |
| 9 | * Derived from drivers/macintosh/macserial.c by Paul Mackerras |
| 10 | * and drivers/serial/sunzilog.c by David S. Miller |
| 11 | * |
| 12 | * Hrm... actually, I ripped most of sunzilog (Thanks David !) and |
| 13 | * adapted special tweaks needed for us. I don't think it's worth |
| 14 | * merging back those though. The DMA code still has to get in |
| 15 | * and once done, I expect that driver to remain fairly stable in |
| 16 | * the long term, unless we change the driver model again... |
| 17 | * |
| 18 | * This program is free software; you can redistribute it and/or modify |
| 19 | * it under the terms of the GNU General Public License as published by |
| 20 | * the Free Software Foundation; either version 2 of the License, or |
| 21 | * (at your option) any later version. |
| 22 | * |
| 23 | * This program is distributed in the hope that it will be useful, |
| 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 26 | * GNU General Public License for more details. |
| 27 | * |
| 28 | * You should have received a copy of the GNU General Public License |
| 29 | * along with this program; if not, write to the Free Software |
| 30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 31 | * |
| 32 | * 2004-08-06 Harald Welte <laforge@gnumonks.org> |
| 33 | * - Enable BREAK interrupt |
| 34 | * - Add support for sysreq |
| 35 | * |
| 36 | * TODO: - Add DMA support |
| 37 | * - Defer port shutdown to a few seconds after close |
| 38 | * - maybe put something right into uap->clk_divisor |
| 39 | */ |
| 40 | |
| 41 | #undef DEBUG |
| 42 | #undef DEBUG_HARD |
| 43 | #undef USE_CTRL_O_SYSRQ |
| 44 | |
| 45 | #include <linux/config.h> |
| 46 | #include <linux/module.h> |
| 47 | #include <linux/tty.h> |
| 48 | |
| 49 | #include <linux/tty_flip.h> |
| 50 | #include <linux/major.h> |
| 51 | #include <linux/string.h> |
| 52 | #include <linux/fcntl.h> |
| 53 | #include <linux/mm.h> |
| 54 | #include <linux/kernel.h> |
| 55 | #include <linux/delay.h> |
| 56 | #include <linux/init.h> |
| 57 | #include <linux/console.h> |
| 58 | #include <linux/slab.h> |
| 59 | #include <linux/adb.h> |
| 60 | #include <linux/pmu.h> |
| 61 | #include <linux/bitops.h> |
| 62 | #include <linux/sysrq.h> |
| 63 | #include <asm/sections.h> |
| 64 | #include <asm/io.h> |
| 65 | #include <asm/irq.h> |
| 66 | #include <asm/prom.h> |
| 67 | #include <asm/machdep.h> |
| 68 | #include <asm/pmac_feature.h> |
| 69 | #include <asm/dbdma.h> |
| 70 | #include <asm/macio.h> |
| 71 | #include <asm/semaphore.h> |
| 72 | |
| 73 | #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
| 74 | #define SUPPORT_SYSRQ |
| 75 | #endif |
| 76 | |
| 77 | #include <linux/serial.h> |
| 78 | #include <linux/serial_core.h> |
| 79 | |
| 80 | #include "pmac_zilog.h" |
| 81 | |
| 82 | /* Not yet implemented */ |
| 83 | #undef HAS_DBDMA |
| 84 | |
| 85 | static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)"; |
| 86 | MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>"); |
| 87 | MODULE_DESCRIPTION("Driver for the PowerMac serial ports."); |
| 88 | MODULE_LICENSE("GPL"); |
| 89 | |
| 90 | #define PWRDBG(fmt, arg...) printk(KERN_DEBUG fmt , ## arg) |
| 91 | |
| 92 | |
| 93 | /* |
| 94 | * For the sake of early serial console, we can do a pre-probe |
| 95 | * (optional) of the ports at rather early boot time. |
| 96 | */ |
| 97 | static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS]; |
| 98 | static int pmz_ports_count; |
| 99 | static DECLARE_MUTEX(pmz_irq_sem); |
| 100 | |
| 101 | static struct uart_driver pmz_uart_reg = { |
| 102 | .owner = THIS_MODULE, |
| 103 | .driver_name = "ttyS", |
| 104 | .devfs_name = "tts/", |
| 105 | .dev_name = "ttyS", |
| 106 | .major = TTY_MAJOR, |
| 107 | }; |
| 108 | |
| 109 | |
| 110 | /* |
| 111 | * Load all registers to reprogram the port |
| 112 | * This function must only be called when the TX is not busy. The UART |
| 113 | * port lock must be held and local interrupts disabled. |
| 114 | */ |
| 115 | static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) |
| 116 | { |
| 117 | int i; |
| 118 | |
| 119 | if (ZS_IS_ASLEEP(uap)) |
| 120 | return; |
| 121 | |
| 122 | /* Let pending transmits finish. */ |
| 123 | for (i = 0; i < 1000; i++) { |
| 124 | unsigned char stat = read_zsreg(uap, R1); |
| 125 | if (stat & ALL_SNT) |
| 126 | break; |
| 127 | udelay(100); |
| 128 | } |
| 129 | |
| 130 | ZS_CLEARERR(uap); |
| 131 | zssync(uap); |
| 132 | ZS_CLEARFIFO(uap); |
| 133 | zssync(uap); |
| 134 | ZS_CLEARERR(uap); |
| 135 | |
| 136 | /* Disable all interrupts. */ |
| 137 | write_zsreg(uap, R1, |
| 138 | regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); |
| 139 | |
| 140 | /* Set parity, sync config, stop bits, and clock divisor. */ |
| 141 | write_zsreg(uap, R4, regs[R4]); |
| 142 | |
| 143 | /* Set misc. TX/RX control bits. */ |
| 144 | write_zsreg(uap, R10, regs[R10]); |
| 145 | |
| 146 | /* Set TX/RX controls sans the enable bits. */ |
| 147 | write_zsreg(uap, R3, regs[R3] & ~RxENABLE); |
| 148 | write_zsreg(uap, R5, regs[R5] & ~TxENABLE); |
| 149 | |
| 150 | /* now set R7 "prime" on ESCC */ |
| 151 | write_zsreg(uap, R15, regs[R15] | EN85C30); |
| 152 | write_zsreg(uap, R7, regs[R7P]); |
| 153 | |
| 154 | /* make sure we use R7 "non-prime" on ESCC */ |
| 155 | write_zsreg(uap, R15, regs[R15] & ~EN85C30); |
| 156 | |
| 157 | /* Synchronous mode config. */ |
| 158 | write_zsreg(uap, R6, regs[R6]); |
| 159 | write_zsreg(uap, R7, regs[R7]); |
| 160 | |
| 161 | /* Disable baud generator. */ |
| 162 | write_zsreg(uap, R14, regs[R14] & ~BRENAB); |
| 163 | |
| 164 | /* Clock mode control. */ |
| 165 | write_zsreg(uap, R11, regs[R11]); |
| 166 | |
| 167 | /* Lower and upper byte of baud rate generator divisor. */ |
| 168 | write_zsreg(uap, R12, regs[R12]); |
| 169 | write_zsreg(uap, R13, regs[R13]); |
| 170 | |
| 171 | /* Now rewrite R14, with BRENAB (if set). */ |
| 172 | write_zsreg(uap, R14, regs[R14]); |
| 173 | |
| 174 | /* Reset external status interrupts. */ |
| 175 | write_zsreg(uap, R0, RES_EXT_INT); |
| 176 | write_zsreg(uap, R0, RES_EXT_INT); |
| 177 | |
| 178 | /* Rewrite R3/R5, this time without enables masked. */ |
| 179 | write_zsreg(uap, R3, regs[R3]); |
| 180 | write_zsreg(uap, R5, regs[R5]); |
| 181 | |
| 182 | /* Rewrite R1, this time without IRQ enabled masked. */ |
| 183 | write_zsreg(uap, R1, regs[R1]); |
| 184 | |
| 185 | /* Enable interrupts */ |
| 186 | write_zsreg(uap, R9, regs[R9]); |
| 187 | } |
| 188 | |
| 189 | /* |
| 190 | * We do like sunzilog to avoid disrupting pending Tx |
| 191 | * Reprogram the Zilog channel HW registers with the copies found in the |
| 192 | * software state struct. If the transmitter is busy, we defer this update |
| 193 | * until the next TX complete interrupt. Else, we do it right now. |
| 194 | * |
| 195 | * The UART port lock must be held and local interrupts disabled. |
| 196 | */ |
| 197 | static void pmz_maybe_update_regs(struct uart_pmac_port *uap) |
| 198 | { |
| 199 | if (!ZS_REGS_HELD(uap)) { |
| 200 | if (ZS_TX_ACTIVE(uap)) { |
| 201 | uap->flags |= PMACZILOG_FLAG_REGS_HELD; |
| 202 | } else { |
| 203 | pmz_debug("pmz: maybe_update_regs: updating\n"); |
| 204 | pmz_load_zsregs(uap, uap->curregs); |
| 205 | } |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap, |
| 210 | struct pt_regs *regs) |
| 211 | { |
| 212 | struct tty_struct *tty = NULL; |
| 213 | unsigned char ch, r1, drop, error; |
| 214 | int loops = 0; |
| 215 | |
| 216 | retry: |
| 217 | /* The interrupt can be enabled when the port isn't open, typically |
| 218 | * that happens when using one port is open and the other closed (stale |
| 219 | * interrupt) or when one port is used as a console. |
| 220 | */ |
| 221 | if (!ZS_IS_OPEN(uap)) { |
| 222 | pmz_debug("pmz: draining input\n"); |
| 223 | /* Port is closed, drain input data */ |
| 224 | for (;;) { |
| 225 | if ((++loops) > 1000) |
| 226 | goto flood; |
| 227 | (void)read_zsreg(uap, R1); |
| 228 | write_zsreg(uap, R0, ERR_RES); |
| 229 | (void)read_zsdata(uap); |
| 230 | ch = read_zsreg(uap, R0); |
| 231 | if (!(ch & Rx_CH_AV)) |
| 232 | break; |
| 233 | } |
| 234 | return NULL; |
| 235 | } |
| 236 | |
| 237 | /* Sanity check, make sure the old bug is no longer happening */ |
| 238 | if (uap->port.info == NULL || uap->port.info->tty == NULL) { |
| 239 | WARN_ON(1); |
| 240 | (void)read_zsdata(uap); |
| 241 | return NULL; |
| 242 | } |
| 243 | tty = uap->port.info->tty; |
| 244 | |
| 245 | while (1) { |
| 246 | error = 0; |
| 247 | drop = 0; |
| 248 | |
| 249 | if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) { |
| 250 | /* Have to drop the lock here */ |
| 251 | pmz_debug("pmz: flip overflow\n"); |
| 252 | spin_unlock(&uap->port.lock); |
| 253 | tty->flip.work.func((void *)tty); |
| 254 | spin_lock(&uap->port.lock); |
| 255 | if (tty->flip.count >= TTY_FLIPBUF_SIZE) |
| 256 | drop = 1; |
| 257 | if (ZS_IS_ASLEEP(uap)) |
| 258 | return NULL; |
| 259 | if (!ZS_IS_OPEN(uap)) |
| 260 | goto retry; |
| 261 | } |
| 262 | |
| 263 | r1 = read_zsreg(uap, R1); |
| 264 | ch = read_zsdata(uap); |
| 265 | |
| 266 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { |
| 267 | write_zsreg(uap, R0, ERR_RES); |
| 268 | zssync(uap); |
| 269 | } |
| 270 | |
| 271 | ch &= uap->parity_mask; |
| 272 | if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { |
| 273 | uap->flags &= ~PMACZILOG_FLAG_BREAK; |
| 274 | } |
| 275 | |
| 276 | #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE) |
| 277 | #ifdef USE_CTRL_O_SYSRQ |
| 278 | /* Handle the SysRq ^O Hack */ |
| 279 | if (ch == '\x0f') { |
| 280 | uap->port.sysrq = jiffies + HZ*5; |
| 281 | goto next_char; |
| 282 | } |
| 283 | #endif /* USE_CTRL_O_SYSRQ */ |
| 284 | if (uap->port.sysrq) { |
| 285 | int swallow; |
| 286 | spin_unlock(&uap->port.lock); |
| 287 | swallow = uart_handle_sysrq_char(&uap->port, ch, regs); |
| 288 | spin_lock(&uap->port.lock); |
| 289 | if (swallow) |
| 290 | goto next_char; |
| 291 | } |
| 292 | #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ |
| 293 | |
| 294 | /* A real serial line, record the character and status. */ |
| 295 | if (drop) |
| 296 | goto next_char; |
| 297 | |
| 298 | *tty->flip.char_buf_ptr = ch; |
| 299 | *tty->flip.flag_buf_ptr = TTY_NORMAL; |
| 300 | uap->port.icount.rx++; |
| 301 | |
| 302 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) { |
| 303 | error = 1; |
| 304 | if (r1 & BRK_ABRT) { |
| 305 | pmz_debug("pmz: got break !\n"); |
| 306 | r1 &= ~(PAR_ERR | CRC_ERR); |
| 307 | uap->port.icount.brk++; |
| 308 | if (uart_handle_break(&uap->port)) |
| 309 | goto next_char; |
| 310 | } |
| 311 | else if (r1 & PAR_ERR) |
| 312 | uap->port.icount.parity++; |
| 313 | else if (r1 & CRC_ERR) |
| 314 | uap->port.icount.frame++; |
| 315 | if (r1 & Rx_OVR) |
| 316 | uap->port.icount.overrun++; |
| 317 | r1 &= uap->port.read_status_mask; |
| 318 | if (r1 & BRK_ABRT) |
| 319 | *tty->flip.flag_buf_ptr = TTY_BREAK; |
| 320 | else if (r1 & PAR_ERR) |
| 321 | *tty->flip.flag_buf_ptr = TTY_PARITY; |
| 322 | else if (r1 & CRC_ERR) |
| 323 | *tty->flip.flag_buf_ptr = TTY_FRAME; |
| 324 | } |
| 325 | |
| 326 | if (uap->port.ignore_status_mask == 0xff || |
| 327 | (r1 & uap->port.ignore_status_mask) == 0) { |
| 328 | tty->flip.flag_buf_ptr++; |
| 329 | tty->flip.char_buf_ptr++; |
| 330 | tty->flip.count++; |
| 331 | } |
| 332 | if ((r1 & Rx_OVR) && |
| 333 | tty->flip.count < TTY_FLIPBUF_SIZE) { |
| 334 | *tty->flip.flag_buf_ptr = TTY_OVERRUN; |
| 335 | tty->flip.flag_buf_ptr++; |
| 336 | tty->flip.char_buf_ptr++; |
| 337 | tty->flip.count++; |
| 338 | } |
| 339 | next_char: |
| 340 | /* We can get stuck in an infinite loop getting char 0 when the |
| 341 | * line is in a wrong HW state, we break that here. |
| 342 | * When that happens, I disable the receive side of the driver. |
| 343 | * Note that what I've been experiencing is a real irq loop where |
| 344 | * I'm getting flooded regardless of the actual port speed. |
| 345 | * Something stange is going on with the HW |
| 346 | */ |
| 347 | if ((++loops) > 1000) |
| 348 | goto flood; |
| 349 | ch = read_zsreg(uap, R0); |
| 350 | if (!(ch & Rx_CH_AV)) |
| 351 | break; |
| 352 | } |
| 353 | |
| 354 | return tty; |
| 355 | flood: |
| 356 | uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); |
| 357 | write_zsreg(uap, R1, uap->curregs[R1]); |
| 358 | zssync(uap); |
| 359 | dev_err(&uap->dev->ofdev.dev, "pmz: rx irq flood !\n"); |
| 360 | return tty; |
| 361 | } |
| 362 | |
| 363 | static void pmz_status_handle(struct uart_pmac_port *uap, struct pt_regs *regs) |
| 364 | { |
| 365 | unsigned char status; |
| 366 | |
| 367 | status = read_zsreg(uap, R0); |
| 368 | write_zsreg(uap, R0, RES_EXT_INT); |
| 369 | zssync(uap); |
| 370 | |
| 371 | if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { |
| 372 | if (status & SYNC_HUNT) |
| 373 | uap->port.icount.dsr++; |
| 374 | |
| 375 | /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. |
| 376 | * But it does not tell us which bit has changed, we have to keep |
| 377 | * track of this ourselves. |
| 378 | * The CTS input is inverted for some reason. -- paulus |
| 379 | */ |
| 380 | if ((status ^ uap->prev_status) & DCD) |
| 381 | uart_handle_dcd_change(&uap->port, |
| 382 | (status & DCD)); |
| 383 | if ((status ^ uap->prev_status) & CTS) |
| 384 | uart_handle_cts_change(&uap->port, |
| 385 | !(status & CTS)); |
| 386 | |
| 387 | wake_up_interruptible(&uap->port.info->delta_msr_wait); |
| 388 | } |
| 389 | |
| 390 | if (status & BRK_ABRT) |
| 391 | uap->flags |= PMACZILOG_FLAG_BREAK; |
| 392 | |
| 393 | uap->prev_status = status; |
| 394 | } |
| 395 | |
| 396 | static void pmz_transmit_chars(struct uart_pmac_port *uap) |
| 397 | { |
| 398 | struct circ_buf *xmit; |
| 399 | |
| 400 | if (ZS_IS_ASLEEP(uap)) |
| 401 | return; |
| 402 | if (ZS_IS_CONS(uap)) { |
| 403 | unsigned char status = read_zsreg(uap, R0); |
| 404 | |
| 405 | /* TX still busy? Just wait for the next TX done interrupt. |
| 406 | * |
| 407 | * It can occur because of how we do serial console writes. It would |
| 408 | * be nice to transmit console writes just like we normally would for |
| 409 | * a TTY line. (ie. buffered and TX interrupt driven). That is not |
| 410 | * easy because console writes cannot sleep. One solution might be |
| 411 | * to poll on enough port->xmit space becomming free. -DaveM |
| 412 | */ |
| 413 | if (!(status & Tx_BUF_EMP)) |
| 414 | return; |
| 415 | } |
| 416 | |
| 417 | uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; |
| 418 | |
| 419 | if (ZS_REGS_HELD(uap)) { |
| 420 | pmz_load_zsregs(uap, uap->curregs); |
| 421 | uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; |
| 422 | } |
| 423 | |
| 424 | if (ZS_TX_STOPPED(uap)) { |
| 425 | uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; |
| 426 | goto ack_tx_int; |
| 427 | } |
| 428 | |
| 429 | if (uap->port.x_char) { |
| 430 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; |
| 431 | write_zsdata(uap, uap->port.x_char); |
| 432 | zssync(uap); |
| 433 | uap->port.icount.tx++; |
| 434 | uap->port.x_char = 0; |
| 435 | return; |
| 436 | } |
| 437 | |
| 438 | if (uap->port.info == NULL) |
| 439 | goto ack_tx_int; |
| 440 | xmit = &uap->port.info->xmit; |
| 441 | if (uart_circ_empty(xmit)) { |
| 442 | uart_write_wakeup(&uap->port); |
| 443 | goto ack_tx_int; |
| 444 | } |
| 445 | if (uart_tx_stopped(&uap->port)) |
| 446 | goto ack_tx_int; |
| 447 | |
| 448 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; |
| 449 | write_zsdata(uap, xmit->buf[xmit->tail]); |
| 450 | zssync(uap); |
| 451 | |
| 452 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
| 453 | uap->port.icount.tx++; |
| 454 | |
| 455 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 456 | uart_write_wakeup(&uap->port); |
| 457 | |
| 458 | return; |
| 459 | |
| 460 | ack_tx_int: |
| 461 | write_zsreg(uap, R0, RES_Tx_P); |
| 462 | zssync(uap); |
| 463 | } |
| 464 | |
| 465 | /* Hrm... we register that twice, fixme later.... */ |
| 466 | static irqreturn_t pmz_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
| 467 | { |
| 468 | struct uart_pmac_port *uap = dev_id; |
| 469 | struct uart_pmac_port *uap_a; |
| 470 | struct uart_pmac_port *uap_b; |
| 471 | int rc = IRQ_NONE; |
| 472 | struct tty_struct *tty; |
| 473 | u8 r3; |
| 474 | |
| 475 | uap_a = pmz_get_port_A(uap); |
| 476 | uap_b = uap_a->mate; |
| 477 | |
| 478 | spin_lock(&uap_a->port.lock); |
| 479 | r3 = read_zsreg(uap_a, R3); |
| 480 | |
| 481 | #ifdef DEBUG_HARD |
| 482 | pmz_debug("irq, r3: %x\n", r3); |
| 483 | #endif |
| 484 | /* Channel A */ |
| 485 | tty = NULL; |
| 486 | if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { |
| 487 | write_zsreg(uap_a, R0, RES_H_IUS); |
| 488 | zssync(uap_a); |
| 489 | if (r3 & CHAEXT) |
| 490 | pmz_status_handle(uap_a, regs); |
| 491 | if (r3 & CHARxIP) |
| 492 | tty = pmz_receive_chars(uap_a, regs); |
| 493 | if (r3 & CHATxIP) |
| 494 | pmz_transmit_chars(uap_a); |
| 495 | rc = IRQ_HANDLED; |
| 496 | } |
| 497 | spin_unlock(&uap_a->port.lock); |
| 498 | if (tty != NULL) |
| 499 | tty_flip_buffer_push(tty); |
| 500 | |
| 501 | if (uap_b->node == NULL) |
| 502 | goto out; |
| 503 | |
| 504 | spin_lock(&uap_b->port.lock); |
| 505 | tty = NULL; |
| 506 | if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { |
| 507 | write_zsreg(uap_b, R0, RES_H_IUS); |
| 508 | zssync(uap_b); |
| 509 | if (r3 & CHBEXT) |
| 510 | pmz_status_handle(uap_b, regs); |
| 511 | if (r3 & CHBRxIP) |
| 512 | tty = pmz_receive_chars(uap_b, regs); |
| 513 | if (r3 & CHBTxIP) |
| 514 | pmz_transmit_chars(uap_b); |
| 515 | rc = IRQ_HANDLED; |
| 516 | } |
| 517 | spin_unlock(&uap_b->port.lock); |
| 518 | if (tty != NULL) |
| 519 | tty_flip_buffer_push(tty); |
| 520 | |
| 521 | out: |
| 522 | #ifdef DEBUG_HARD |
| 523 | pmz_debug("irq done.\n"); |
| 524 | #endif |
| 525 | return rc; |
| 526 | } |
| 527 | |
| 528 | /* |
| 529 | * Peek the status register, lock not held by caller |
| 530 | */ |
| 531 | static inline u8 pmz_peek_status(struct uart_pmac_port *uap) |
| 532 | { |
| 533 | unsigned long flags; |
| 534 | u8 status; |
| 535 | |
| 536 | spin_lock_irqsave(&uap->port.lock, flags); |
| 537 | status = read_zsreg(uap, R0); |
| 538 | spin_unlock_irqrestore(&uap->port.lock, flags); |
| 539 | |
| 540 | return status; |
| 541 | } |
| 542 | |
| 543 | /* |
| 544 | * Check if transmitter is empty |
| 545 | * The port lock is not held. |
| 546 | */ |
| 547 | static unsigned int pmz_tx_empty(struct uart_port *port) |
| 548 | { |
| 549 | struct uart_pmac_port *uap = to_pmz(port); |
| 550 | unsigned char status; |
| 551 | |
| 552 | if (ZS_IS_ASLEEP(uap) || uap->node == NULL) |
| 553 | return TIOCSER_TEMT; |
| 554 | |
| 555 | status = pmz_peek_status(to_pmz(port)); |
| 556 | if (status & Tx_BUF_EMP) |
| 557 | return TIOCSER_TEMT; |
| 558 | return 0; |
| 559 | } |
| 560 | |
| 561 | /* |
| 562 | * Set Modem Control (RTS & DTR) bits |
| 563 | * The port lock is held and interrupts are disabled. |
| 564 | * Note: Shall we really filter out RTS on external ports or |
| 565 | * should that be dealt at higher level only ? |
| 566 | */ |
| 567 | static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl) |
| 568 | { |
| 569 | struct uart_pmac_port *uap = to_pmz(port); |
| 570 | unsigned char set_bits, clear_bits; |
| 571 | |
| 572 | /* Do nothing for irda for now... */ |
| 573 | if (ZS_IS_IRDA(uap)) |
| 574 | return; |
| 575 | /* We get called during boot with a port not up yet */ |
| 576 | if (ZS_IS_ASLEEP(uap) || |
| 577 | !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) |
| 578 | return; |
| 579 | |
| 580 | set_bits = clear_bits = 0; |
| 581 | |
| 582 | if (ZS_IS_INTMODEM(uap)) { |
| 583 | if (mctrl & TIOCM_RTS) |
| 584 | set_bits |= RTS; |
| 585 | else |
| 586 | clear_bits |= RTS; |
| 587 | } |
| 588 | if (mctrl & TIOCM_DTR) |
| 589 | set_bits |= DTR; |
| 590 | else |
| 591 | clear_bits |= DTR; |
| 592 | |
| 593 | /* NOTE: Not subject to 'transmitter active' rule. */ |
| 594 | uap->curregs[R5] |= set_bits; |
| 595 | uap->curregs[R5] &= ~clear_bits; |
| 596 | if (ZS_IS_ASLEEP(uap)) |
| 597 | return; |
| 598 | write_zsreg(uap, R5, uap->curregs[R5]); |
| 599 | pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n", |
| 600 | set_bits, clear_bits, uap->curregs[R5]); |
| 601 | zssync(uap); |
| 602 | } |
| 603 | |
| 604 | /* |
| 605 | * Get Modem Control bits (only the input ones, the core will |
| 606 | * or that with a cached value of the control ones) |
| 607 | * The port lock is not held. |
| 608 | */ |
| 609 | static unsigned int pmz_get_mctrl(struct uart_port *port) |
| 610 | { |
| 611 | struct uart_pmac_port *uap = to_pmz(port); |
| 612 | unsigned char status; |
| 613 | unsigned int ret; |
| 614 | |
| 615 | if (ZS_IS_ASLEEP(uap) || uap->node == NULL) |
| 616 | return 0; |
| 617 | |
| 618 | status = pmz_peek_status(to_pmz(port)); |
| 619 | |
| 620 | ret = 0; |
| 621 | if (status & DCD) |
| 622 | ret |= TIOCM_CAR; |
| 623 | if (status & SYNC_HUNT) |
| 624 | ret |= TIOCM_DSR; |
| 625 | if (!(status & CTS)) |
| 626 | ret |= TIOCM_CTS; |
| 627 | |
| 628 | return ret; |
| 629 | } |
| 630 | |
| 631 | /* |
| 632 | * Stop TX side. Dealt like sunzilog at next Tx interrupt, |
| 633 | * though for DMA, we will have to do a bit more. What is |
| 634 | * the meaning of the tty_stop bit ? XXX |
| 635 | * The port lock is held and interrupts are disabled. |
| 636 | */ |
| 637 | static void pmz_stop_tx(struct uart_port *port, unsigned int tty_stop) |
| 638 | { |
| 639 | to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED; |
| 640 | } |
| 641 | |
| 642 | /* |
| 643 | * Kick the Tx side. |
| 644 | * The port lock is held and interrupts are disabled. |
| 645 | */ |
| 646 | static void pmz_start_tx(struct uart_port *port, unsigned int tty_start) |
| 647 | { |
| 648 | struct uart_pmac_port *uap = to_pmz(port); |
| 649 | unsigned char status; |
| 650 | |
| 651 | pmz_debug("pmz: start_tx()\n"); |
| 652 | |
| 653 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; |
| 654 | uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; |
| 655 | |
| 656 | if (ZS_IS_ASLEEP(uap) || uap->node == NULL) |
| 657 | return; |
| 658 | |
| 659 | status = read_zsreg(uap, R0); |
| 660 | |
| 661 | /* TX busy? Just wait for the TX done interrupt. */ |
| 662 | if (!(status & Tx_BUF_EMP)) |
| 663 | return; |
| 664 | |
| 665 | /* Send the first character to jump-start the TX done |
| 666 | * IRQ sending engine. |
| 667 | */ |
| 668 | if (port->x_char) { |
| 669 | write_zsdata(uap, port->x_char); |
| 670 | zssync(uap); |
| 671 | port->icount.tx++; |
| 672 | port->x_char = 0; |
| 673 | } else { |
| 674 | struct circ_buf *xmit = &port->info->xmit; |
| 675 | |
| 676 | write_zsdata(uap, xmit->buf[xmit->tail]); |
| 677 | zssync(uap); |
| 678 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
| 679 | port->icount.tx++; |
| 680 | |
| 681 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
| 682 | uart_write_wakeup(&uap->port); |
| 683 | } |
| 684 | pmz_debug("pmz: start_tx() done.\n"); |
| 685 | } |
| 686 | |
| 687 | /* |
| 688 | * Stop Rx side, basically disable emitting of |
| 689 | * Rx interrupts on the port. We don't disable the rx |
| 690 | * side of the chip proper though |
| 691 | * The port lock is held. |
| 692 | */ |
| 693 | static void pmz_stop_rx(struct uart_port *port) |
| 694 | { |
| 695 | struct uart_pmac_port *uap = to_pmz(port); |
| 696 | |
| 697 | if (ZS_IS_ASLEEP(uap) || uap->node == NULL) |
| 698 | return; |
| 699 | |
| 700 | pmz_debug("pmz: stop_rx()()\n"); |
| 701 | |
| 702 | /* Disable all RX interrupts. */ |
| 703 | uap->curregs[R1] &= ~RxINT_MASK; |
| 704 | pmz_maybe_update_regs(uap); |
| 705 | |
| 706 | pmz_debug("pmz: stop_rx() done.\n"); |
| 707 | } |
| 708 | |
| 709 | /* |
| 710 | * Enable modem status change interrupts |
| 711 | * The port lock is held. |
| 712 | */ |
| 713 | static void pmz_enable_ms(struct uart_port *port) |
| 714 | { |
| 715 | struct uart_pmac_port *uap = to_pmz(port); |
| 716 | unsigned char new_reg; |
| 717 | |
| 718 | if (ZS_IS_IRDA(uap) || uap->node == NULL) |
| 719 | return; |
| 720 | new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); |
| 721 | if (new_reg != uap->curregs[R15]) { |
| 722 | uap->curregs[R15] = new_reg; |
| 723 | |
| 724 | if (ZS_IS_ASLEEP(uap)) |
| 725 | return; |
| 726 | /* NOTE: Not subject to 'transmitter active' rule. */ |
| 727 | write_zsreg(uap, R15, uap->curregs[R15]); |
| 728 | } |
| 729 | } |
| 730 | |
| 731 | /* |
| 732 | * Control break state emission |
| 733 | * The port lock is not held. |
| 734 | */ |
| 735 | static void pmz_break_ctl(struct uart_port *port, int break_state) |
| 736 | { |
| 737 | struct uart_pmac_port *uap = to_pmz(port); |
| 738 | unsigned char set_bits, clear_bits, new_reg; |
| 739 | unsigned long flags; |
| 740 | |
| 741 | if (uap->node == NULL) |
| 742 | return; |
| 743 | set_bits = clear_bits = 0; |
| 744 | |
| 745 | if (break_state) |
| 746 | set_bits |= SND_BRK; |
| 747 | else |
| 748 | clear_bits |= SND_BRK; |
| 749 | |
| 750 | spin_lock_irqsave(&port->lock, flags); |
| 751 | |
| 752 | new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; |
| 753 | if (new_reg != uap->curregs[R5]) { |
| 754 | uap->curregs[R5] = new_reg; |
| 755 | |
| 756 | /* NOTE: Not subject to 'transmitter active' rule. */ |
| 757 | if (ZS_IS_ASLEEP(uap)) |
| 758 | return; |
| 759 | write_zsreg(uap, R5, uap->curregs[R5]); |
| 760 | } |
| 761 | |
| 762 | spin_unlock_irqrestore(&port->lock, flags); |
| 763 | } |
| 764 | |
| 765 | /* |
| 766 | * Turn power on or off to the SCC and associated stuff |
| 767 | * (port drivers, modem, IR port, etc.) |
| 768 | * Returns the number of milliseconds we should wait before |
| 769 | * trying to use the port. |
| 770 | */ |
| 771 | static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) |
| 772 | { |
| 773 | int delay = 0; |
| 774 | int rc; |
| 775 | |
| 776 | if (state) { |
| 777 | rc = pmac_call_feature( |
| 778 | PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); |
| 779 | pmz_debug("port power on result: %d\n", rc); |
| 780 | if (ZS_IS_INTMODEM(uap)) { |
| 781 | rc = pmac_call_feature( |
| 782 | PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); |
| 783 | delay = 2500; /* wait for 2.5s before using */ |
| 784 | pmz_debug("modem power result: %d\n", rc); |
| 785 | } |
| 786 | } else { |
| 787 | /* TODO: Make that depend on a timer, don't power down |
| 788 | * immediately |
| 789 | */ |
| 790 | if (ZS_IS_INTMODEM(uap)) { |
| 791 | rc = pmac_call_feature( |
| 792 | PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); |
| 793 | pmz_debug("port power off result: %d\n", rc); |
| 794 | } |
| 795 | pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); |
| 796 | } |
| 797 | return delay; |
| 798 | } |
| 799 | |
| 800 | /* |
| 801 | * FixZeroBug....Works around a bug in the SCC receving channel. |
| 802 | * Inspired from Darwin code, 15 Sept. 2000 -DanM |
| 803 | * |
| 804 | * The following sequence prevents a problem that is seen with O'Hare ASICs |
| 805 | * (most versions -- also with some Heathrow and Hydra ASICs) where a zero |
| 806 | * at the input to the receiver becomes 'stuck' and locks up the receiver. |
| 807 | * This problem can occur as a result of a zero bit at the receiver input |
| 808 | * coincident with any of the following events: |
| 809 | * |
| 810 | * The SCC is initialized (hardware or software). |
| 811 | * A framing error is detected. |
| 812 | * The clocking option changes from synchronous or X1 asynchronous |
| 813 | * clocking to X16, X32, or X64 asynchronous clocking. |
| 814 | * The decoding mode is changed among NRZ, NRZI, FM0, or FM1. |
| 815 | * |
| 816 | * This workaround attempts to recover from the lockup condition by placing |
| 817 | * the SCC in synchronous loopback mode with a fast clock before programming |
| 818 | * any of the asynchronous modes. |
| 819 | */ |
| 820 | static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) |
| 821 | { |
| 822 | write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); |
| 823 | zssync(uap); |
| 824 | udelay(10); |
| 825 | write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); |
| 826 | zssync(uap); |
| 827 | |
| 828 | write_zsreg(uap, 4, X1CLK | MONSYNC); |
| 829 | write_zsreg(uap, 3, Rx8); |
| 830 | write_zsreg(uap, 5, Tx8 | RTS); |
| 831 | write_zsreg(uap, 9, NV); /* Didn't we already do this? */ |
| 832 | write_zsreg(uap, 11, RCBR | TCBR); |
| 833 | write_zsreg(uap, 12, 0); |
| 834 | write_zsreg(uap, 13, 0); |
| 835 | write_zsreg(uap, 14, (LOOPBAK | BRSRC)); |
| 836 | write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB)); |
| 837 | write_zsreg(uap, 3, Rx8 | RxENABLE); |
| 838 | write_zsreg(uap, 0, RES_EXT_INT); |
| 839 | write_zsreg(uap, 0, RES_EXT_INT); |
| 840 | write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */ |
| 841 | |
| 842 | /* The channel should be OK now, but it is probably receiving |
| 843 | * loopback garbage. |
| 844 | * Switch to asynchronous mode, disable the receiver, |
| 845 | * and discard everything in the receive buffer. |
| 846 | */ |
| 847 | write_zsreg(uap, 9, NV); |
| 848 | write_zsreg(uap, 4, X16CLK | SB_MASK); |
| 849 | write_zsreg(uap, 3, Rx8); |
| 850 | |
| 851 | while (read_zsreg(uap, 0) & Rx_CH_AV) { |
| 852 | (void)read_zsreg(uap, 8); |
| 853 | write_zsreg(uap, 0, RES_EXT_INT); |
| 854 | write_zsreg(uap, 0, ERR_RES); |
| 855 | } |
| 856 | } |
| 857 | |
| 858 | /* |
| 859 | * Real startup routine, powers up the hardware and sets up |
| 860 | * the SCC. Returns a delay in ms where you need to wait before |
| 861 | * actually using the port, this is typically the internal modem |
| 862 | * powerup delay. This routine expect the lock to be taken. |
| 863 | */ |
| 864 | static int __pmz_startup(struct uart_pmac_port *uap) |
| 865 | { |
| 866 | int pwr_delay = 0; |
| 867 | |
| 868 | memset(&uap->curregs, 0, sizeof(uap->curregs)); |
| 869 | |
| 870 | /* Power up the SCC & underlying hardware (modem/irda) */ |
| 871 | pwr_delay = pmz_set_scc_power(uap, 1); |
| 872 | |
| 873 | /* Nice buggy HW ... */ |
| 874 | pmz_fix_zero_bug_scc(uap); |
| 875 | |
| 876 | /* Reset the channel */ |
| 877 | uap->curregs[R9] = 0; |
| 878 | write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); |
| 879 | zssync(uap); |
| 880 | udelay(10); |
| 881 | write_zsreg(uap, 9, 0); |
| 882 | zssync(uap); |
| 883 | |
| 884 | /* Clear the interrupt registers */ |
| 885 | write_zsreg(uap, R1, 0); |
| 886 | write_zsreg(uap, R0, ERR_RES); |
| 887 | write_zsreg(uap, R0, ERR_RES); |
| 888 | write_zsreg(uap, R0, RES_H_IUS); |
| 889 | write_zsreg(uap, R0, RES_H_IUS); |
| 890 | |
| 891 | /* Setup some valid baud rate */ |
| 892 | uap->curregs[R4] = X16CLK | SB1; |
| 893 | uap->curregs[R3] = Rx8; |
| 894 | uap->curregs[R5] = Tx8 | RTS; |
| 895 | if (!ZS_IS_IRDA(uap)) |
| 896 | uap->curregs[R5] |= DTR; |
| 897 | uap->curregs[R12] = 0; |
| 898 | uap->curregs[R13] = 0; |
| 899 | uap->curregs[R14] = BRENAB; |
| 900 | |
| 901 | /* Clear handshaking, enable BREAK interrupts */ |
| 902 | uap->curregs[R15] = BRKIE; |
| 903 | |
| 904 | /* Master interrupt enable */ |
| 905 | uap->curregs[R9] |= NV | MIE; |
| 906 | |
| 907 | pmz_load_zsregs(uap, uap->curregs); |
| 908 | |
| 909 | /* Enable receiver and transmitter. */ |
| 910 | write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); |
| 911 | write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); |
| 912 | |
| 913 | /* Remember status for DCD/CTS changes */ |
| 914 | uap->prev_status = read_zsreg(uap, R0); |
| 915 | |
| 916 | |
| 917 | return pwr_delay; |
| 918 | } |
| 919 | |
| 920 | static void pmz_irda_reset(struct uart_pmac_port *uap) |
| 921 | { |
| 922 | uap->curregs[R5] |= DTR; |
| 923 | write_zsreg(uap, R5, uap->curregs[R5]); |
| 924 | zssync(uap); |
| 925 | mdelay(110); |
| 926 | uap->curregs[R5] &= ~DTR; |
| 927 | write_zsreg(uap, R5, uap->curregs[R5]); |
| 928 | zssync(uap); |
| 929 | mdelay(10); |
| 930 | } |
| 931 | |
| 932 | /* |
| 933 | * This is the "normal" startup routine, using the above one |
| 934 | * wrapped with the lock and doing a schedule delay |
| 935 | */ |
| 936 | static int pmz_startup(struct uart_port *port) |
| 937 | { |
| 938 | struct uart_pmac_port *uap = to_pmz(port); |
| 939 | unsigned long flags; |
| 940 | int pwr_delay = 0; |
| 941 | |
| 942 | pmz_debug("pmz: startup()\n"); |
| 943 | |
| 944 | if (ZS_IS_ASLEEP(uap)) |
| 945 | return -EAGAIN; |
| 946 | if (uap->node == NULL) |
| 947 | return -ENODEV; |
| 948 | |
| 949 | down(&pmz_irq_sem); |
| 950 | |
| 951 | uap->flags |= PMACZILOG_FLAG_IS_OPEN; |
| 952 | |
| 953 | /* A console is never powered down. Else, power up and |
| 954 | * initialize the chip |
| 955 | */ |
| 956 | if (!ZS_IS_CONS(uap)) { |
| 957 | spin_lock_irqsave(&port->lock, flags); |
| 958 | pwr_delay = __pmz_startup(uap); |
| 959 | spin_unlock_irqrestore(&port->lock, flags); |
| 960 | } |
| 961 | |
| 962 | pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON; |
| 963 | if (request_irq(uap->port.irq, pmz_interrupt, SA_SHIRQ, "PowerMac Zilog", uap)) { |
| 964 | dev_err(&uap->dev->ofdev.dev, |
| 965 | "Unable to register zs interrupt handler.\n"); |
| 966 | pmz_set_scc_power(uap, 0); |
| 967 | up(&pmz_irq_sem); |
| 968 | return -ENXIO; |
| 969 | } |
| 970 | |
| 971 | up(&pmz_irq_sem); |
| 972 | |
| 973 | /* Right now, we deal with delay by blocking here, I'll be |
| 974 | * smarter later on |
| 975 | */ |
| 976 | if (pwr_delay != 0) { |
| 977 | pmz_debug("pmz: delaying %d ms\n", pwr_delay); |
| 978 | msleep(pwr_delay); |
| 979 | } |
| 980 | |
| 981 | /* IrDA reset is done now */ |
| 982 | if (ZS_IS_IRDA(uap)) |
| 983 | pmz_irda_reset(uap); |
| 984 | |
| 985 | /* Enable interrupts emission from the chip */ |
| 986 | spin_lock_irqsave(&port->lock, flags); |
| 987 | uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; |
| 988 | if (!ZS_IS_EXTCLK(uap)) |
| 989 | uap->curregs[R1] |= EXT_INT_ENAB; |
| 990 | write_zsreg(uap, R1, uap->curregs[R1]); |
| 991 | spin_unlock_irqrestore(&port->lock, flags); |
| 992 | |
| 993 | pmz_debug("pmz: startup() done.\n"); |
| 994 | |
| 995 | return 0; |
| 996 | } |
| 997 | |
| 998 | static void pmz_shutdown(struct uart_port *port) |
| 999 | { |
| 1000 | struct uart_pmac_port *uap = to_pmz(port); |
| 1001 | unsigned long flags; |
| 1002 | |
| 1003 | pmz_debug("pmz: shutdown()\n"); |
| 1004 | |
| 1005 | if (uap->node == NULL) |
| 1006 | return; |
| 1007 | |
| 1008 | down(&pmz_irq_sem); |
| 1009 | |
| 1010 | /* Release interrupt handler */ |
| 1011 | free_irq(uap->port.irq, uap); |
| 1012 | |
| 1013 | spin_lock_irqsave(&port->lock, flags); |
| 1014 | |
| 1015 | uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; |
| 1016 | |
| 1017 | if (!ZS_IS_OPEN(uap->mate)) |
| 1018 | pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON; |
| 1019 | |
| 1020 | /* Disable interrupts */ |
| 1021 | if (!ZS_IS_ASLEEP(uap)) { |
| 1022 | uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); |
| 1023 | write_zsreg(uap, R1, uap->curregs[R1]); |
| 1024 | zssync(uap); |
| 1025 | } |
| 1026 | |
| 1027 | if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) { |
| 1028 | spin_unlock_irqrestore(&port->lock, flags); |
| 1029 | up(&pmz_irq_sem); |
| 1030 | return; |
| 1031 | } |
| 1032 | |
| 1033 | /* Disable receiver and transmitter. */ |
| 1034 | uap->curregs[R3] &= ~RxENABLE; |
| 1035 | uap->curregs[R5] &= ~TxENABLE; |
| 1036 | |
| 1037 | /* Disable all interrupts and BRK assertion. */ |
| 1038 | uap->curregs[R5] &= ~SND_BRK; |
| 1039 | pmz_maybe_update_regs(uap); |
| 1040 | |
| 1041 | /* Shut the chip down */ |
| 1042 | pmz_set_scc_power(uap, 0); |
| 1043 | |
| 1044 | spin_unlock_irqrestore(&port->lock, flags); |
| 1045 | |
| 1046 | up(&pmz_irq_sem); |
| 1047 | |
| 1048 | pmz_debug("pmz: shutdown() done.\n"); |
| 1049 | } |
| 1050 | |
| 1051 | /* Shared by TTY driver and serial console setup. The port lock is held |
| 1052 | * and local interrupts are disabled. |
| 1053 | */ |
| 1054 | static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, |
| 1055 | unsigned int iflag, unsigned long baud) |
| 1056 | { |
| 1057 | int brg; |
| 1058 | |
| 1059 | |
| 1060 | /* Switch to external clocking for IrDA high clock rates. That |
| 1061 | * code could be re-used for Midi interfaces with different |
| 1062 | * multipliers |
| 1063 | */ |
| 1064 | if (baud >= 115200 && ZS_IS_IRDA(uap)) { |
| 1065 | uap->curregs[R4] = X1CLK; |
| 1066 | uap->curregs[R11] = RCTRxCP | TCTRxCP; |
| 1067 | uap->curregs[R14] = 0; /* BRG off */ |
| 1068 | uap->curregs[R12] = 0; |
| 1069 | uap->curregs[R13] = 0; |
| 1070 | uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; |
| 1071 | } else { |
| 1072 | switch (baud) { |
| 1073 | case ZS_CLOCK/16: /* 230400 */ |
| 1074 | uap->curregs[R4] = X16CLK; |
| 1075 | uap->curregs[R11] = 0; |
| 1076 | uap->curregs[R14] = 0; |
| 1077 | break; |
| 1078 | case ZS_CLOCK/32: /* 115200 */ |
| 1079 | uap->curregs[R4] = X32CLK; |
| 1080 | uap->curregs[R11] = 0; |
| 1081 | uap->curregs[R14] = 0; |
| 1082 | break; |
| 1083 | default: |
| 1084 | uap->curregs[R4] = X16CLK; |
| 1085 | uap->curregs[R11] = TCBR | RCBR; |
| 1086 | brg = BPS_TO_BRG(baud, ZS_CLOCK / 16); |
| 1087 | uap->curregs[R12] = (brg & 255); |
| 1088 | uap->curregs[R13] = ((brg >> 8) & 255); |
| 1089 | uap->curregs[R14] = BRENAB; |
| 1090 | } |
| 1091 | uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; |
| 1092 | } |
| 1093 | |
| 1094 | /* Character size, stop bits, and parity. */ |
| 1095 | uap->curregs[3] &= ~RxN_MASK; |
| 1096 | uap->curregs[5] &= ~TxN_MASK; |
| 1097 | |
| 1098 | switch (cflag & CSIZE) { |
| 1099 | case CS5: |
| 1100 | uap->curregs[3] |= Rx5; |
| 1101 | uap->curregs[5] |= Tx5; |
| 1102 | uap->parity_mask = 0x1f; |
| 1103 | break; |
| 1104 | case CS6: |
| 1105 | uap->curregs[3] |= Rx6; |
| 1106 | uap->curregs[5] |= Tx6; |
| 1107 | uap->parity_mask = 0x3f; |
| 1108 | break; |
| 1109 | case CS7: |
| 1110 | uap->curregs[3] |= Rx7; |
| 1111 | uap->curregs[5] |= Tx7; |
| 1112 | uap->parity_mask = 0x7f; |
| 1113 | break; |
| 1114 | case CS8: |
| 1115 | default: |
| 1116 | uap->curregs[3] |= Rx8; |
| 1117 | uap->curregs[5] |= Tx8; |
| 1118 | uap->parity_mask = 0xff; |
| 1119 | break; |
| 1120 | }; |
| 1121 | uap->curregs[4] &= ~(SB_MASK); |
| 1122 | if (cflag & CSTOPB) |
| 1123 | uap->curregs[4] |= SB2; |
| 1124 | else |
| 1125 | uap->curregs[4] |= SB1; |
| 1126 | if (cflag & PARENB) |
| 1127 | uap->curregs[4] |= PAR_ENAB; |
| 1128 | else |
| 1129 | uap->curregs[4] &= ~PAR_ENAB; |
| 1130 | if (!(cflag & PARODD)) |
| 1131 | uap->curregs[4] |= PAR_EVEN; |
| 1132 | else |
| 1133 | uap->curregs[4] &= ~PAR_EVEN; |
| 1134 | |
| 1135 | uap->port.read_status_mask = Rx_OVR; |
| 1136 | if (iflag & INPCK) |
| 1137 | uap->port.read_status_mask |= CRC_ERR | PAR_ERR; |
| 1138 | if (iflag & (BRKINT | PARMRK)) |
| 1139 | uap->port.read_status_mask |= BRK_ABRT; |
| 1140 | |
| 1141 | uap->port.ignore_status_mask = 0; |
| 1142 | if (iflag & IGNPAR) |
| 1143 | uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; |
| 1144 | if (iflag & IGNBRK) { |
| 1145 | uap->port.ignore_status_mask |= BRK_ABRT; |
| 1146 | if (iflag & IGNPAR) |
| 1147 | uap->port.ignore_status_mask |= Rx_OVR; |
| 1148 | } |
| 1149 | |
| 1150 | if ((cflag & CREAD) == 0) |
| 1151 | uap->port.ignore_status_mask = 0xff; |
| 1152 | } |
| 1153 | |
| 1154 | |
| 1155 | /* |
| 1156 | * Set the irda codec on the imac to the specified baud rate. |
| 1157 | */ |
| 1158 | static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) |
| 1159 | { |
| 1160 | u8 cmdbyte; |
| 1161 | int t, version; |
| 1162 | |
| 1163 | switch (*baud) { |
| 1164 | /* SIR modes */ |
| 1165 | case 2400: |
| 1166 | cmdbyte = 0x53; |
| 1167 | break; |
| 1168 | case 4800: |
| 1169 | cmdbyte = 0x52; |
| 1170 | break; |
| 1171 | case 9600: |
| 1172 | cmdbyte = 0x51; |
| 1173 | break; |
| 1174 | case 19200: |
| 1175 | cmdbyte = 0x50; |
| 1176 | break; |
| 1177 | case 38400: |
| 1178 | cmdbyte = 0x4f; |
| 1179 | break; |
| 1180 | case 57600: |
| 1181 | cmdbyte = 0x4e; |
| 1182 | break; |
| 1183 | case 115200: |
| 1184 | cmdbyte = 0x4d; |
| 1185 | break; |
| 1186 | /* The FIR modes aren't really supported at this point, how |
| 1187 | * do we select the speed ? via the FCR on KeyLargo ? |
| 1188 | */ |
| 1189 | case 1152000: |
| 1190 | cmdbyte = 0; |
| 1191 | break; |
| 1192 | case 4000000: |
| 1193 | cmdbyte = 0; |
| 1194 | break; |
| 1195 | default: /* 9600 */ |
| 1196 | cmdbyte = 0x51; |
| 1197 | *baud = 9600; |
| 1198 | break; |
| 1199 | } |
| 1200 | |
| 1201 | /* Wait for transmitter to drain */ |
| 1202 | t = 10000; |
| 1203 | while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 |
| 1204 | || (read_zsreg(uap, R1) & ALL_SNT) == 0) { |
| 1205 | if (--t <= 0) { |
| 1206 | dev_err(&uap->dev->ofdev.dev, "transmitter didn't drain\n"); |
| 1207 | return; |
| 1208 | } |
| 1209 | udelay(10); |
| 1210 | } |
| 1211 | |
| 1212 | /* Drain the receiver too */ |
| 1213 | t = 100; |
| 1214 | (void)read_zsdata(uap); |
| 1215 | (void)read_zsdata(uap); |
| 1216 | (void)read_zsdata(uap); |
| 1217 | mdelay(10); |
| 1218 | while (read_zsreg(uap, R0) & Rx_CH_AV) { |
| 1219 | read_zsdata(uap); |
| 1220 | mdelay(10); |
| 1221 | if (--t <= 0) { |
| 1222 | dev_err(&uap->dev->ofdev.dev, "receiver didn't drain\n"); |
| 1223 | return; |
| 1224 | } |
| 1225 | } |
| 1226 | |
| 1227 | /* Switch to command mode */ |
| 1228 | uap->curregs[R5] |= DTR; |
| 1229 | write_zsreg(uap, R5, uap->curregs[R5]); |
| 1230 | zssync(uap); |
| 1231 | mdelay(1); |
| 1232 | |
| 1233 | /* Switch SCC to 19200 */ |
| 1234 | pmz_convert_to_zs(uap, CS8, 0, 19200); |
| 1235 | pmz_load_zsregs(uap, uap->curregs); |
| 1236 | mdelay(1); |
| 1237 | |
| 1238 | /* Write get_version command byte */ |
| 1239 | write_zsdata(uap, 1); |
| 1240 | t = 5000; |
| 1241 | while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { |
| 1242 | if (--t <= 0) { |
| 1243 | dev_err(&uap->dev->ofdev.dev, |
| 1244 | "irda_setup timed out on get_version byte\n"); |
| 1245 | goto out; |
| 1246 | } |
| 1247 | udelay(10); |
| 1248 | } |
| 1249 | version = read_zsdata(uap); |
| 1250 | |
| 1251 | if (version < 4) { |
| 1252 | dev_info(&uap->dev->ofdev.dev, "IrDA: dongle version %d not supported\n", |
| 1253 | version); |
| 1254 | goto out; |
| 1255 | } |
| 1256 | |
| 1257 | /* Send speed mode */ |
| 1258 | write_zsdata(uap, cmdbyte); |
| 1259 | t = 5000; |
| 1260 | while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { |
| 1261 | if (--t <= 0) { |
| 1262 | dev_err(&uap->dev->ofdev.dev, |
| 1263 | "irda_setup timed out on speed mode byte\n"); |
| 1264 | goto out; |
| 1265 | } |
| 1266 | udelay(10); |
| 1267 | } |
| 1268 | t = read_zsdata(uap); |
| 1269 | if (t != cmdbyte) |
| 1270 | dev_err(&uap->dev->ofdev.dev, |
| 1271 | "irda_setup speed mode byte = %x (%x)\n", t, cmdbyte); |
| 1272 | |
| 1273 | dev_info(&uap->dev->ofdev.dev, "IrDA setup for %ld bps, dongle version: %d\n", |
| 1274 | *baud, version); |
| 1275 | |
| 1276 | (void)read_zsdata(uap); |
| 1277 | (void)read_zsdata(uap); |
| 1278 | (void)read_zsdata(uap); |
| 1279 | |
| 1280 | out: |
| 1281 | /* Switch back to data mode */ |
| 1282 | uap->curregs[R5] &= ~DTR; |
| 1283 | write_zsreg(uap, R5, uap->curregs[R5]); |
| 1284 | zssync(uap); |
| 1285 | |
| 1286 | (void)read_zsdata(uap); |
| 1287 | (void)read_zsdata(uap); |
| 1288 | (void)read_zsdata(uap); |
| 1289 | } |
| 1290 | |
| 1291 | |
| 1292 | static void __pmz_set_termios(struct uart_port *port, struct termios *termios, |
| 1293 | struct termios *old) |
| 1294 | { |
| 1295 | struct uart_pmac_port *uap = to_pmz(port); |
| 1296 | unsigned long baud; |
| 1297 | |
| 1298 | pmz_debug("pmz: set_termios()\n"); |
| 1299 | |
| 1300 | if (ZS_IS_ASLEEP(uap)) |
| 1301 | return; |
| 1302 | |
| 1303 | memcpy(&uap->termios_cache, termios, sizeof(struct termios)); |
| 1304 | |
| 1305 | /* XXX Check which revs of machines actually allow 1 and 4Mb speeds |
| 1306 | * on the IR dongle. Note that the IRTTY driver currently doesn't know |
| 1307 | * about the FIR mode and high speed modes. So these are unused. For |
| 1308 | * implementing proper support for these, we should probably add some |
| 1309 | * DMA as well, at least on the Rx side, which isn't a simple thing |
| 1310 | * at this point. |
| 1311 | */ |
| 1312 | if (ZS_IS_IRDA(uap)) { |
| 1313 | /* Calc baud rate */ |
| 1314 | baud = uart_get_baud_rate(port, termios, old, 1200, 4000000); |
| 1315 | pmz_debug("pmz: switch IRDA to %ld bauds\n", baud); |
| 1316 | /* Cet the irda codec to the right rate */ |
| 1317 | pmz_irda_setup(uap, &baud); |
| 1318 | /* Set final baud rate */ |
| 1319 | pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); |
| 1320 | pmz_load_zsregs(uap, uap->curregs); |
| 1321 | zssync(uap); |
| 1322 | } else { |
| 1323 | baud = uart_get_baud_rate(port, termios, old, 1200, 230400); |
| 1324 | pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); |
| 1325 | /* Make sure modem status interrupts are correctly configured */ |
| 1326 | if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { |
| 1327 | uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; |
| 1328 | uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; |
| 1329 | } else { |
| 1330 | uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); |
| 1331 | uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; |
| 1332 | } |
| 1333 | |
| 1334 | /* Load registers to the chip */ |
| 1335 | pmz_maybe_update_regs(uap); |
| 1336 | } |
| 1337 | uart_update_timeout(port, termios->c_cflag, baud); |
| 1338 | |
| 1339 | pmz_debug("pmz: set_termios() done.\n"); |
| 1340 | } |
| 1341 | |
| 1342 | /* The port lock is not held. */ |
| 1343 | static void pmz_set_termios(struct uart_port *port, struct termios *termios, |
| 1344 | struct termios *old) |
| 1345 | { |
| 1346 | struct uart_pmac_port *uap = to_pmz(port); |
| 1347 | unsigned long flags; |
| 1348 | |
| 1349 | spin_lock_irqsave(&port->lock, flags); |
| 1350 | |
| 1351 | /* Disable IRQs on the port */ |
| 1352 | uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); |
| 1353 | write_zsreg(uap, R1, uap->curregs[R1]); |
| 1354 | |
| 1355 | /* Setup new port configuration */ |
| 1356 | __pmz_set_termios(port, termios, old); |
| 1357 | |
| 1358 | /* Re-enable IRQs on the port */ |
| 1359 | if (ZS_IS_OPEN(uap)) { |
| 1360 | uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; |
| 1361 | if (!ZS_IS_EXTCLK(uap)) |
| 1362 | uap->curregs[R1] |= EXT_INT_ENAB; |
| 1363 | write_zsreg(uap, R1, uap->curregs[R1]); |
| 1364 | } |
| 1365 | spin_unlock_irqrestore(&port->lock, flags); |
| 1366 | } |
| 1367 | |
| 1368 | static const char *pmz_type(struct uart_port *port) |
| 1369 | { |
| 1370 | struct uart_pmac_port *uap = to_pmz(port); |
| 1371 | |
| 1372 | if (ZS_IS_IRDA(uap)) |
| 1373 | return "Z85c30 ESCC - Infrared port"; |
| 1374 | else if (ZS_IS_INTMODEM(uap)) |
| 1375 | return "Z85c30 ESCC - Internal modem"; |
| 1376 | return "Z85c30 ESCC - Serial port"; |
| 1377 | } |
| 1378 | |
| 1379 | /* We do not request/release mappings of the registers here, this |
| 1380 | * happens at early serial probe time. |
| 1381 | */ |
| 1382 | static void pmz_release_port(struct uart_port *port) |
| 1383 | { |
| 1384 | } |
| 1385 | |
| 1386 | static int pmz_request_port(struct uart_port *port) |
| 1387 | { |
| 1388 | return 0; |
| 1389 | } |
| 1390 | |
| 1391 | /* These do not need to do anything interesting either. */ |
| 1392 | static void pmz_config_port(struct uart_port *port, int flags) |
| 1393 | { |
| 1394 | } |
| 1395 | |
| 1396 | /* We do not support letting the user mess with the divisor, IRQ, etc. */ |
| 1397 | static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser) |
| 1398 | { |
| 1399 | return -EINVAL; |
| 1400 | } |
| 1401 | |
| 1402 | static struct uart_ops pmz_pops = { |
| 1403 | .tx_empty = pmz_tx_empty, |
| 1404 | .set_mctrl = pmz_set_mctrl, |
| 1405 | .get_mctrl = pmz_get_mctrl, |
| 1406 | .stop_tx = pmz_stop_tx, |
| 1407 | .start_tx = pmz_start_tx, |
| 1408 | .stop_rx = pmz_stop_rx, |
| 1409 | .enable_ms = pmz_enable_ms, |
| 1410 | .break_ctl = pmz_break_ctl, |
| 1411 | .startup = pmz_startup, |
| 1412 | .shutdown = pmz_shutdown, |
| 1413 | .set_termios = pmz_set_termios, |
| 1414 | .type = pmz_type, |
| 1415 | .release_port = pmz_release_port, |
| 1416 | .request_port = pmz_request_port, |
| 1417 | .config_port = pmz_config_port, |
| 1418 | .verify_port = pmz_verify_port, |
| 1419 | }; |
| 1420 | |
| 1421 | /* |
| 1422 | * Setup one port structure after probing, HW is down at this point, |
| 1423 | * Unlike sunzilog, we don't need to pre-init the spinlock as we don't |
| 1424 | * register our console before uart_add_one_port() is called |
| 1425 | */ |
| 1426 | static int __init pmz_init_port(struct uart_pmac_port *uap) |
| 1427 | { |
| 1428 | struct device_node *np = uap->node; |
| 1429 | char *conn; |
| 1430 | struct slot_names_prop { |
| 1431 | int count; |
| 1432 | char name[1]; |
| 1433 | } *slots; |
| 1434 | int len; |
| 1435 | |
| 1436 | /* |
| 1437 | * Request & map chip registers |
| 1438 | */ |
| 1439 | uap->port.mapbase = np->addrs[0].address; |
| 1440 | uap->port.membase = ioremap(uap->port.mapbase, 0x1000); |
| 1441 | |
| 1442 | uap->control_reg = uap->port.membase; |
| 1443 | uap->data_reg = uap->control_reg + 0x10; |
| 1444 | |
| 1445 | /* |
| 1446 | * Request & map DBDMA registers |
| 1447 | */ |
| 1448 | #ifdef HAS_DBDMA |
| 1449 | if (np->n_addrs >= 3 && np->n_intrs >= 3) |
| 1450 | uap->flags |= PMACZILOG_FLAG_HAS_DMA; |
| 1451 | #endif |
| 1452 | if (ZS_HAS_DMA(uap)) { |
| 1453 | uap->tx_dma_regs = ioremap(np->addrs[np->n_addrs - 2].address, 0x1000); |
| 1454 | if (uap->tx_dma_regs == NULL) { |
| 1455 | uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; |
| 1456 | goto no_dma; |
| 1457 | } |
| 1458 | uap->rx_dma_regs = ioremap(np->addrs[np->n_addrs - 1].address, 0x1000); |
| 1459 | if (uap->rx_dma_regs == NULL) { |
| 1460 | iounmap(uap->tx_dma_regs); |
| 1461 | uap->tx_dma_regs = NULL; |
| 1462 | uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; |
| 1463 | goto no_dma; |
| 1464 | } |
| 1465 | uap->tx_dma_irq = np->intrs[1].line; |
| 1466 | uap->rx_dma_irq = np->intrs[2].line; |
| 1467 | } |
| 1468 | no_dma: |
| 1469 | |
| 1470 | /* |
| 1471 | * Detect port type |
| 1472 | */ |
| 1473 | if (device_is_compatible(np, "cobalt")) |
| 1474 | uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; |
| 1475 | conn = get_property(np, "AAPL,connector", &len); |
| 1476 | if (conn && (strcmp(conn, "infrared") == 0)) |
| 1477 | uap->flags |= PMACZILOG_FLAG_IS_IRDA; |
| 1478 | uap->port_type = PMAC_SCC_ASYNC; |
| 1479 | /* 1999 Powerbook G3 has slot-names property instead */ |
| 1480 | slots = (struct slot_names_prop *)get_property(np, "slot-names", &len); |
| 1481 | if (slots && slots->count > 0) { |
| 1482 | if (strcmp(slots->name, "IrDA") == 0) |
| 1483 | uap->flags |= PMACZILOG_FLAG_IS_IRDA; |
| 1484 | else if (strcmp(slots->name, "Modem") == 0) |
| 1485 | uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; |
| 1486 | } |
| 1487 | if (ZS_IS_IRDA(uap)) |
| 1488 | uap->port_type = PMAC_SCC_IRDA; |
| 1489 | if (ZS_IS_INTMODEM(uap)) { |
| 1490 | struct device_node* i2c_modem = find_devices("i2c-modem"); |
| 1491 | if (i2c_modem) { |
| 1492 | char* mid = get_property(i2c_modem, "modem-id", NULL); |
| 1493 | if (mid) switch(*mid) { |
| 1494 | case 0x04 : |
| 1495 | case 0x05 : |
| 1496 | case 0x07 : |
| 1497 | case 0x08 : |
| 1498 | case 0x0b : |
| 1499 | case 0x0c : |
| 1500 | uap->port_type = PMAC_SCC_I2S1; |
| 1501 | } |
| 1502 | printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n", |
| 1503 | mid ? (*mid) : 0); |
| 1504 | } else { |
| 1505 | printk(KERN_INFO "pmac_zilog: serial modem detected\n"); |
| 1506 | } |
| 1507 | } |
| 1508 | |
| 1509 | /* |
| 1510 | * Init remaining bits of "port" structure |
| 1511 | */ |
| 1512 | uap->port.iotype = SERIAL_IO_MEM; |
| 1513 | uap->port.irq = np->intrs[0].line; |
| 1514 | uap->port.uartclk = ZS_CLOCK; |
| 1515 | uap->port.fifosize = 1; |
| 1516 | uap->port.ops = &pmz_pops; |
| 1517 | uap->port.type = PORT_PMAC_ZILOG; |
| 1518 | uap->port.flags = 0; |
| 1519 | |
| 1520 | /* Setup some valid baud rate information in the register |
| 1521 | * shadows so we don't write crap there before baud rate is |
| 1522 | * first initialized. |
| 1523 | */ |
| 1524 | pmz_convert_to_zs(uap, CS8, 0, 9600); |
| 1525 | |
| 1526 | return 0; |
| 1527 | } |
| 1528 | |
| 1529 | /* |
| 1530 | * Get rid of a port on module removal |
| 1531 | */ |
| 1532 | static void pmz_dispose_port(struct uart_pmac_port *uap) |
| 1533 | { |
| 1534 | struct device_node *np; |
| 1535 | |
| 1536 | np = uap->node; |
| 1537 | iounmap(uap->rx_dma_regs); |
| 1538 | iounmap(uap->tx_dma_regs); |
| 1539 | iounmap(uap->control_reg); |
| 1540 | uap->node = NULL; |
| 1541 | of_node_put(np); |
| 1542 | memset(uap, 0, sizeof(struct uart_pmac_port)); |
| 1543 | } |
| 1544 | |
| 1545 | /* |
| 1546 | * Called upon match with an escc node in the devive-tree. |
| 1547 | */ |
| 1548 | static int pmz_attach(struct macio_dev *mdev, const struct of_match *match) |
| 1549 | { |
| 1550 | int i; |
| 1551 | |
| 1552 | /* Iterate the pmz_ports array to find a matching entry |
| 1553 | */ |
| 1554 | for (i = 0; i < MAX_ZS_PORTS; i++) |
| 1555 | if (pmz_ports[i].node == mdev->ofdev.node) { |
| 1556 | struct uart_pmac_port *uap = &pmz_ports[i]; |
| 1557 | |
| 1558 | uap->dev = mdev; |
| 1559 | dev_set_drvdata(&mdev->ofdev.dev, uap); |
| 1560 | if (macio_request_resources(uap->dev, "pmac_zilog")) |
| 1561 | printk(KERN_WARNING "%s: Failed to request resource" |
| 1562 | ", port still active\n", |
| 1563 | uap->node->name); |
| 1564 | else |
| 1565 | uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; |
| 1566 | return 0; |
| 1567 | } |
| 1568 | return -ENODEV; |
| 1569 | } |
| 1570 | |
| 1571 | /* |
| 1572 | * That one should not be called, macio isn't really a hotswap device, |
| 1573 | * we don't expect one of those serial ports to go away... |
| 1574 | */ |
| 1575 | static int pmz_detach(struct macio_dev *mdev) |
| 1576 | { |
| 1577 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); |
| 1578 | |
| 1579 | if (!uap) |
| 1580 | return -ENODEV; |
| 1581 | |
| 1582 | if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { |
| 1583 | macio_release_resources(uap->dev); |
| 1584 | uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; |
| 1585 | } |
| 1586 | dev_set_drvdata(&mdev->ofdev.dev, NULL); |
| 1587 | uap->dev = NULL; |
| 1588 | |
| 1589 | return 0; |
| 1590 | } |
| 1591 | |
| 1592 | |
| 1593 | static int pmz_suspend(struct macio_dev *mdev, u32 pm_state) |
| 1594 | { |
| 1595 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); |
| 1596 | struct uart_state *state; |
| 1597 | unsigned long flags; |
| 1598 | |
| 1599 | if (uap == NULL) { |
| 1600 | printk("HRM... pmz_suspend with NULL uap\n"); |
| 1601 | return 0; |
| 1602 | } |
| 1603 | |
| 1604 | if (pm_state == mdev->ofdev.dev.power.power_state || pm_state < 2) |
| 1605 | return 0; |
| 1606 | |
| 1607 | pmz_debug("suspend, switching to state %d\n", pm_state); |
| 1608 | |
| 1609 | state = pmz_uart_reg.state + uap->port.line; |
| 1610 | |
| 1611 | down(&pmz_irq_sem); |
| 1612 | down(&state->sem); |
| 1613 | |
| 1614 | spin_lock_irqsave(&uap->port.lock, flags); |
| 1615 | |
| 1616 | if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) { |
| 1617 | /* Disable receiver and transmitter. */ |
| 1618 | uap->curregs[R3] &= ~RxENABLE; |
| 1619 | uap->curregs[R5] &= ~TxENABLE; |
| 1620 | |
| 1621 | /* Disable all interrupts and BRK assertion. */ |
| 1622 | uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); |
| 1623 | uap->curregs[R5] &= ~SND_BRK; |
| 1624 | pmz_load_zsregs(uap, uap->curregs); |
| 1625 | uap->flags |= PMACZILOG_FLAG_IS_ASLEEP; |
| 1626 | mb(); |
| 1627 | } |
| 1628 | |
| 1629 | spin_unlock_irqrestore(&uap->port.lock, flags); |
| 1630 | |
| 1631 | if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate)) |
| 1632 | if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) { |
| 1633 | pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON; |
| 1634 | disable_irq(uap->port.irq); |
| 1635 | } |
| 1636 | |
| 1637 | if (ZS_IS_CONS(uap)) |
| 1638 | uap->port.cons->flags &= ~CON_ENABLED; |
| 1639 | |
| 1640 | /* Shut the chip down */ |
| 1641 | pmz_set_scc_power(uap, 0); |
| 1642 | |
| 1643 | up(&state->sem); |
| 1644 | up(&pmz_irq_sem); |
| 1645 | |
| 1646 | pmz_debug("suspend, switching complete\n"); |
| 1647 | |
| 1648 | mdev->ofdev.dev.power.power_state = pm_state; |
| 1649 | |
| 1650 | return 0; |
| 1651 | } |
| 1652 | |
| 1653 | |
| 1654 | static int pmz_resume(struct macio_dev *mdev) |
| 1655 | { |
| 1656 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); |
| 1657 | struct uart_state *state; |
| 1658 | unsigned long flags; |
| 1659 | int pwr_delay = 0; |
| 1660 | |
| 1661 | if (uap == NULL) |
| 1662 | return 0; |
| 1663 | |
| 1664 | if (mdev->ofdev.dev.power.power_state == 0) |
| 1665 | return 0; |
| 1666 | |
| 1667 | pmz_debug("resume, switching to state 0\n"); |
| 1668 | |
| 1669 | state = pmz_uart_reg.state + uap->port.line; |
| 1670 | |
| 1671 | down(&pmz_irq_sem); |
| 1672 | down(&state->sem); |
| 1673 | |
| 1674 | spin_lock_irqsave(&uap->port.lock, flags); |
| 1675 | if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) { |
| 1676 | spin_unlock_irqrestore(&uap->port.lock, flags); |
| 1677 | goto bail; |
| 1678 | } |
| 1679 | pwr_delay = __pmz_startup(uap); |
| 1680 | |
| 1681 | /* Take care of config that may have changed while asleep */ |
| 1682 | __pmz_set_termios(&uap->port, &uap->termios_cache, NULL); |
| 1683 | |
| 1684 | if (ZS_IS_OPEN(uap)) { |
| 1685 | /* Enable interrupts */ |
| 1686 | uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; |
| 1687 | if (!ZS_IS_EXTCLK(uap)) |
| 1688 | uap->curregs[R1] |= EXT_INT_ENAB; |
| 1689 | write_zsreg(uap, R1, uap->curregs[R1]); |
| 1690 | } |
| 1691 | |
| 1692 | spin_unlock_irqrestore(&uap->port.lock, flags); |
| 1693 | |
| 1694 | if (ZS_IS_CONS(uap)) |
| 1695 | uap->port.cons->flags |= CON_ENABLED; |
| 1696 | |
| 1697 | /* Re-enable IRQ on the controller */ |
| 1698 | if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) { |
| 1699 | pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON; |
| 1700 | enable_irq(uap->port.irq); |
| 1701 | } |
| 1702 | |
| 1703 | bail: |
| 1704 | up(&state->sem); |
| 1705 | up(&pmz_irq_sem); |
| 1706 | |
| 1707 | /* Right now, we deal with delay by blocking here, I'll be |
| 1708 | * smarter later on |
| 1709 | */ |
| 1710 | if (pwr_delay != 0) { |
| 1711 | pmz_debug("pmz: delaying %d ms\n", pwr_delay); |
| 1712 | msleep(pwr_delay); |
| 1713 | } |
| 1714 | |
| 1715 | pmz_debug("resume, switching complete\n"); |
| 1716 | |
| 1717 | mdev->ofdev.dev.power.power_state = 0; |
| 1718 | |
| 1719 | return 0; |
| 1720 | } |
| 1721 | |
| 1722 | /* |
| 1723 | * Probe all ports in the system and build the ports array, we register |
| 1724 | * with the serial layer at this point, the macio-type probing is only |
| 1725 | * used later to "attach" to the sysfs tree so we get power management |
| 1726 | * events |
| 1727 | */ |
| 1728 | static int __init pmz_probe(void) |
| 1729 | { |
| 1730 | struct device_node *node_p, *node_a, *node_b, *np; |
| 1731 | int count = 0; |
| 1732 | int rc; |
| 1733 | |
| 1734 | /* |
| 1735 | * Find all escc chips in the system |
| 1736 | */ |
| 1737 | node_p = of_find_node_by_name(NULL, "escc"); |
| 1738 | while (node_p) { |
| 1739 | /* |
| 1740 | * First get channel A/B node pointers |
| 1741 | * |
| 1742 | * TODO: Add routines with proper locking to do that... |
| 1743 | */ |
| 1744 | node_a = node_b = NULL; |
| 1745 | for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) { |
| 1746 | if (strncmp(np->name, "ch-a", 4) == 0) |
| 1747 | node_a = of_node_get(np); |
| 1748 | else if (strncmp(np->name, "ch-b", 4) == 0) |
| 1749 | node_b = of_node_get(np); |
| 1750 | } |
| 1751 | if (!node_a && !node_b) { |
| 1752 | of_node_put(node_a); |
| 1753 | of_node_put(node_b); |
| 1754 | printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n", |
| 1755 | (!node_a) ? 'a' : 'b', node_p->full_name); |
| 1756 | goto next; |
| 1757 | } |
| 1758 | |
| 1759 | /* |
| 1760 | * Fill basic fields in the port structures |
| 1761 | */ |
| 1762 | pmz_ports[count].mate = &pmz_ports[count+1]; |
| 1763 | pmz_ports[count+1].mate = &pmz_ports[count]; |
| 1764 | pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A; |
| 1765 | pmz_ports[count].node = node_a; |
| 1766 | pmz_ports[count+1].node = node_b; |
| 1767 | pmz_ports[count].port.line = count; |
| 1768 | pmz_ports[count+1].port.line = count+1; |
| 1769 | |
| 1770 | /* |
| 1771 | * Setup the ports for real |
| 1772 | */ |
| 1773 | rc = pmz_init_port(&pmz_ports[count]); |
| 1774 | if (rc == 0 && node_b != NULL) |
| 1775 | rc = pmz_init_port(&pmz_ports[count+1]); |
| 1776 | if (rc != 0) { |
| 1777 | of_node_put(node_a); |
| 1778 | of_node_put(node_b); |
| 1779 | memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port)); |
| 1780 | memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port)); |
| 1781 | goto next; |
| 1782 | } |
| 1783 | count += 2; |
| 1784 | next: |
| 1785 | node_p = of_find_node_by_name(node_p, "escc"); |
| 1786 | } |
| 1787 | pmz_ports_count = count; |
| 1788 | |
| 1789 | return 0; |
| 1790 | } |
| 1791 | |
| 1792 | #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE |
| 1793 | |
| 1794 | static void pmz_console_write(struct console *con, const char *s, unsigned int count); |
| 1795 | static int __init pmz_console_setup(struct console *co, char *options); |
| 1796 | |
| 1797 | static struct console pmz_console = { |
| 1798 | .name = "ttyS", |
| 1799 | .write = pmz_console_write, |
| 1800 | .device = uart_console_device, |
| 1801 | .setup = pmz_console_setup, |
| 1802 | .flags = CON_PRINTBUFFER, |
| 1803 | .index = -1, |
| 1804 | .data = &pmz_uart_reg, |
| 1805 | }; |
| 1806 | |
| 1807 | #define PMACZILOG_CONSOLE &pmz_console |
| 1808 | #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ |
| 1809 | #define PMACZILOG_CONSOLE (NULL) |
| 1810 | #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ |
| 1811 | |
| 1812 | /* |
| 1813 | * Register the driver, console driver and ports with the serial |
| 1814 | * core |
| 1815 | */ |
| 1816 | static int __init pmz_register(void) |
| 1817 | { |
| 1818 | int i, rc; |
| 1819 | |
| 1820 | pmz_uart_reg.nr = pmz_ports_count; |
| 1821 | pmz_uart_reg.cons = PMACZILOG_CONSOLE; |
| 1822 | pmz_uart_reg.minor = 64; |
| 1823 | |
| 1824 | /* |
| 1825 | * Register this driver with the serial core |
| 1826 | */ |
| 1827 | rc = uart_register_driver(&pmz_uart_reg); |
| 1828 | if (rc) |
| 1829 | return rc; |
| 1830 | |
| 1831 | /* |
| 1832 | * Register each port with the serial core |
| 1833 | */ |
| 1834 | for (i = 0; i < pmz_ports_count; i++) { |
| 1835 | struct uart_pmac_port *uport = &pmz_ports[i]; |
| 1836 | /* NULL node may happen on wallstreet */ |
| 1837 | if (uport->node != NULL) |
| 1838 | rc = uart_add_one_port(&pmz_uart_reg, &uport->port); |
| 1839 | if (rc) |
| 1840 | goto err_out; |
| 1841 | } |
| 1842 | |
| 1843 | return 0; |
| 1844 | err_out: |
| 1845 | while (i-- > 0) { |
| 1846 | struct uart_pmac_port *uport = &pmz_ports[i]; |
| 1847 | uart_remove_one_port(&pmz_uart_reg, &uport->port); |
| 1848 | } |
| 1849 | uart_unregister_driver(&pmz_uart_reg); |
| 1850 | return rc; |
| 1851 | } |
| 1852 | |
| 1853 | static struct of_match pmz_match[] = |
| 1854 | { |
| 1855 | { |
| 1856 | .name = "ch-a", |
| 1857 | .type = OF_ANY_MATCH, |
| 1858 | .compatible = OF_ANY_MATCH |
| 1859 | }, |
| 1860 | { |
| 1861 | .name = "ch-b", |
| 1862 | .type = OF_ANY_MATCH, |
| 1863 | .compatible = OF_ANY_MATCH |
| 1864 | }, |
| 1865 | {}, |
| 1866 | }; |
| 1867 | |
| 1868 | static struct macio_driver pmz_driver = |
| 1869 | { |
| 1870 | .name = "pmac_zilog", |
| 1871 | .match_table = pmz_match, |
| 1872 | .probe = pmz_attach, |
| 1873 | .remove = pmz_detach, |
| 1874 | .suspend = pmz_suspend, |
| 1875 | .resume = pmz_resume, |
| 1876 | }; |
| 1877 | |
| 1878 | static int __init init_pmz(void) |
| 1879 | { |
| 1880 | int rc, i; |
| 1881 | printk(KERN_INFO "%s\n", version); |
| 1882 | |
| 1883 | /* |
| 1884 | * First, we need to do a direct OF-based probe pass. We |
| 1885 | * do that because we want serial console up before the |
| 1886 | * macio stuffs calls us back, and since that makes it |
| 1887 | * easier to pass the proper number of channels to |
| 1888 | * uart_register_driver() |
| 1889 | */ |
| 1890 | if (pmz_ports_count == 0) |
| 1891 | pmz_probe(); |
| 1892 | |
| 1893 | /* |
| 1894 | * Bail early if no port found |
| 1895 | */ |
| 1896 | if (pmz_ports_count == 0) |
| 1897 | return -ENODEV; |
| 1898 | |
| 1899 | /* |
| 1900 | * Now we register with the serial layer |
| 1901 | */ |
| 1902 | rc = pmz_register(); |
| 1903 | if (rc) { |
| 1904 | printk(KERN_ERR |
| 1905 | "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n" |
| 1906 | "pmac_zilog: Did another serial driver already claim the minors?\n"); |
| 1907 | /* effectively "pmz_unprobe()" */ |
| 1908 | for (i=0; i < pmz_ports_count; i++) |
| 1909 | pmz_dispose_port(&pmz_ports[i]); |
| 1910 | return rc; |
| 1911 | } |
| 1912 | |
| 1913 | /* |
| 1914 | * Then we register the macio driver itself |
| 1915 | */ |
| 1916 | return macio_register_driver(&pmz_driver); |
| 1917 | } |
| 1918 | |
| 1919 | static void __exit exit_pmz(void) |
| 1920 | { |
| 1921 | int i; |
| 1922 | |
| 1923 | /* Get rid of macio-driver (detach from macio) */ |
| 1924 | macio_unregister_driver(&pmz_driver); |
| 1925 | |
| 1926 | for (i = 0; i < pmz_ports_count; i++) { |
| 1927 | struct uart_pmac_port *uport = &pmz_ports[i]; |
| 1928 | if (uport->node != NULL) { |
| 1929 | uart_remove_one_port(&pmz_uart_reg, &uport->port); |
| 1930 | pmz_dispose_port(uport); |
| 1931 | } |
| 1932 | } |
| 1933 | /* Unregister UART driver */ |
| 1934 | uart_unregister_driver(&pmz_uart_reg); |
| 1935 | } |
| 1936 | |
| 1937 | #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE |
| 1938 | |
| 1939 | /* |
| 1940 | * Print a string to the serial port trying not to disturb |
| 1941 | * any possible real use of the port... |
| 1942 | */ |
| 1943 | static void pmz_console_write(struct console *con, const char *s, unsigned int count) |
| 1944 | { |
| 1945 | struct uart_pmac_port *uap = &pmz_ports[con->index]; |
| 1946 | unsigned long flags; |
| 1947 | int i; |
| 1948 | |
| 1949 | if (ZS_IS_ASLEEP(uap)) |
| 1950 | return; |
| 1951 | spin_lock_irqsave(&uap->port.lock, flags); |
| 1952 | |
| 1953 | /* Turn of interrupts and enable the transmitter. */ |
| 1954 | write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); |
| 1955 | write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); |
| 1956 | |
| 1957 | for (i = 0; i < count; i++) { |
| 1958 | /* Wait for the transmit buffer to empty. */ |
| 1959 | while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) |
| 1960 | udelay(5); |
| 1961 | write_zsdata(uap, s[i]); |
| 1962 | if (s[i] == 10) { |
| 1963 | while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) |
| 1964 | udelay(5); |
| 1965 | write_zsdata(uap, R13); |
| 1966 | } |
| 1967 | } |
| 1968 | |
| 1969 | /* Restore the values in the registers. */ |
| 1970 | write_zsreg(uap, R1, uap->curregs[1]); |
| 1971 | /* Don't disable the transmitter. */ |
| 1972 | |
| 1973 | spin_unlock_irqrestore(&uap->port.lock, flags); |
| 1974 | } |
| 1975 | |
| 1976 | /* |
| 1977 | * Setup the serial console |
| 1978 | */ |
| 1979 | static int __init pmz_console_setup(struct console *co, char *options) |
| 1980 | { |
| 1981 | struct uart_pmac_port *uap; |
| 1982 | struct uart_port *port; |
| 1983 | int baud = 38400; |
| 1984 | int bits = 8; |
| 1985 | int parity = 'n'; |
| 1986 | int flow = 'n'; |
| 1987 | unsigned long pwr_delay; |
| 1988 | |
| 1989 | /* |
| 1990 | * XServe's default to 57600 bps |
| 1991 | */ |
| 1992 | if (machine_is_compatible("RackMac1,1") |
| 1993 | || machine_is_compatible("RackMac1,2") |
| 1994 | || machine_is_compatible("MacRISC4")) |
| 1995 | baud = 57600; |
| 1996 | |
| 1997 | /* |
| 1998 | * Check whether an invalid uart number has been specified, and |
| 1999 | * if so, search for the first available port that does have |
| 2000 | * console support. |
| 2001 | */ |
| 2002 | if (co->index >= pmz_ports_count) |
| 2003 | co->index = 0; |
| 2004 | uap = &pmz_ports[co->index]; |
| 2005 | if (uap->node == NULL) |
| 2006 | return -ENODEV; |
| 2007 | port = &uap->port; |
| 2008 | |
| 2009 | /* |
| 2010 | * Mark port as beeing a console |
| 2011 | */ |
| 2012 | uap->flags |= PMACZILOG_FLAG_IS_CONS; |
| 2013 | |
| 2014 | /* |
| 2015 | * Temporary fix for uart layer who didn't setup the spinlock yet |
| 2016 | */ |
| 2017 | spin_lock_init(&port->lock); |
| 2018 | |
| 2019 | /* |
| 2020 | * Enable the hardware |
| 2021 | */ |
| 2022 | pwr_delay = __pmz_startup(uap); |
| 2023 | if (pwr_delay) |
| 2024 | mdelay(pwr_delay); |
| 2025 | |
| 2026 | if (options) |
| 2027 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
| 2028 | |
| 2029 | return uart_set_options(port, co, baud, parity, bits, flow); |
| 2030 | } |
| 2031 | |
| 2032 | static int __init pmz_console_init(void) |
| 2033 | { |
| 2034 | /* Probe ports */ |
| 2035 | pmz_probe(); |
| 2036 | |
| 2037 | /* TODO: Autoprobe console based on OF */ |
| 2038 | /* pmz_console.index = i; */ |
| 2039 | register_console(&pmz_console); |
| 2040 | |
| 2041 | return 0; |
| 2042 | |
| 2043 | } |
| 2044 | console_initcall(pmz_console_init); |
| 2045 | #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ |
| 2046 | |
| 2047 | module_init(init_pmz); |
| 2048 | module_exit(exit_pmz); |