blob: bd7e1c040781d597b29583b0cc3f781f91cf2355 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/video/cyber2000fb.h
3 *
4 * Copyright (C) 1998-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Integraphics Cyber2000 frame buffer device
11 */
12#include <linux/config.h>
13
14/*
15 * Internal CyberPro sizes and offsets.
16 */
17#define MMIO_OFFSET 0x00800000
18#define MMIO_SIZE 0x000c0000
19
20#define NR_PALETTE 256
21
22#if defined(DEBUG) && defined(CONFIG_DEBUG_LL)
23static void debug_printf(char *fmt, ...)
24{
25 extern void printascii(const char *);
26 char buffer[128];
27 va_list ap;
28
29 va_start(ap, fmt);
30 vsprintf(buffer, fmt, ap);
31 va_end(ap);
32
33 printascii(buffer);
34}
35#else
36#define debug_printf(x...) do { } while (0)
37#endif
38
39#define RAMDAC_RAMPWRDN 0x01
40#define RAMDAC_DAC8BIT 0x02
41#define RAMDAC_VREFEN 0x04
42#define RAMDAC_BYPASS 0x10
43#define RAMDAC_DACPWRDN 0x40
44
45#define EXT_CRT_VRTOFL 0x11
46#define EXT_CRT_VRTOFL_LINECOMP10 0x10
47#define EXT_CRT_VRTOFL_INTERLACE 0x20
48
49#define EXT_CRT_IRQ 0x12
50#define EXT_CRT_IRQ_ENABLE 0x01
51#define EXT_CRT_IRQ_ACT_HIGH 0x04
52
53#define EXT_CRT_TEST 0x13
54
55#define EXT_SYNC_CTL 0x16
56#define EXT_SYNC_CTL_HS_NORMAL 0x00
57#define EXT_SYNC_CTL_HS_0 0x01
58#define EXT_SYNC_CTL_HS_1 0x02
59#define EXT_SYNC_CTL_HS_HSVS 0x03
60#define EXT_SYNC_CTL_VS_NORMAL 0x00
61#define EXT_SYNC_CTL_VS_0 0x04
62#define EXT_SYNC_CTL_VS_1 0x08
63#define EXT_SYNC_CTL_VS_COMP 0x0c
64
65#define EXT_BUS_CTL 0x30
66#define EXT_BUS_CTL_LIN_1MB 0x00
67#define EXT_BUS_CTL_LIN_2MB 0x01
68#define EXT_BUS_CTL_LIN_4MB 0x02
69#define EXT_BUS_CTL_ZEROWAIT 0x04
70#define EXT_BUS_CTL_PCIBURST_WRITE 0x20
71#define EXT_BUS_CTL_PCIBURST_READ 0x80 /* CyberPro 5000 only */
72
73#define EXT_SEG_WRITE_PTR 0x31
74#define EXT_SEG_READ_PTR 0x32
75#define EXT_BIU_MISC 0x33
76#define EXT_BIU_MISC_LIN_ENABLE 0x01
77#define EXT_BIU_MISC_COP_ENABLE 0x04
78#define EXT_BIU_MISC_COP_BFC 0x08
79
80#define EXT_FUNC_CTL 0x3c
81#define EXT_FUNC_CTL_EXTREGENBL 0x80 /* enable access to 0xbcxxx */
82
83#define PCI_BM_CTL 0x3e
84#define PCI_BM_CTL_ENABLE 0x01 /* enable bus-master */
85#define PCI_BM_CTL_BURST 0x02 /* enable burst */
86#define PCI_BM_CTL_BACK2BACK 0x04 /* enable back to back */
87#define PCI_BM_CTL_DUMMY 0x08 /* insert dummy cycle */
88
89#define X_V2_VID_MEM_START 0x40
90#define X_V2_VID_SRC_WIDTH 0x43
91#define X_V2_X_START 0x45
92#define X_V2_X_END 0x47
93#define X_V2_Y_START 0x49
94#define X_V2_Y_END 0x4b
95#define X_V2_VID_SRC_WIN_WIDTH 0x4d
96
97#define Y_V2_DDA_X_INC 0x43
98#define Y_V2_DDA_Y_INC 0x47
99#define Y_V2_VID_FIFO_CTL 0x49
100#define Y_V2_VID_FMT 0x4b
101#define Y_V2_VID_DISP_CTL1 0x4c
102#define Y_V2_VID_FIFO_CTL1 0x4d
103
104#define J_X2_VID_MEM_START 0x40
105#define J_X2_VID_SRC_WIDTH 0x43
106#define J_X2_X_START 0x47
107#define J_X2_X_END 0x49
108#define J_X2_Y_START 0x4b
109#define J_X2_Y_END 0x4d
110#define J_X2_VID_SRC_WIN_WIDTH 0x4f
111
112#define K_X2_DDA_X_INIT 0x40
113#define K_X2_DDA_X_INC 0x42
114#define K_X2_DDA_Y_INIT 0x44
115#define K_X2_DDA_Y_INC 0x46
116#define K_X2_VID_FMT 0x48
117#define K_X2_VID_DISP_CTL1 0x49
118
119#define K_CAP_X2_CTL1 0x49
120
121#define CURS_H_START 0x50
122#define CURS_H_PRESET 0x52
123#define CURS_V_START 0x53
124#define CURS_V_PRESET 0x55
125#define CURS_CTL 0x56
126
127#define EXT_ATTRIB_CTL 0x57
128#define EXT_ATTRIB_CTL_EXT 0x01
129
130#define EXT_OVERSCAN_RED 0x58
131#define EXT_OVERSCAN_GREEN 0x59
132#define EXT_OVERSCAN_BLUE 0x5a
133
134#define CAP_X_START 0x60
135#define CAP_X_END 0x62
136#define CAP_Y_START 0x64
137#define CAP_Y_END 0x66
138#define CAP_DDA_X_INIT 0x68
139#define CAP_DDA_X_INC 0x6a
140#define CAP_DDA_Y_INIT 0x6c
141#define CAP_DDA_Y_INC 0x6e
142
143#define EXT_MEM_CTL0 0x70
144#define EXT_MEM_CTL0_7CLK 0x01
145#define EXT_MEM_CTL0_RAS_1 0x02
146#define EXT_MEM_CTL0_RAS2CAS_1 0x04
147#define EXT_MEM_CTL0_MULTCAS 0x08
148#define EXT_MEM_CTL0_ASYM 0x10
149#define EXT_MEM_CTL0_CAS1ON 0x20
150#define EXT_MEM_CTL0_FIFOFLUSH 0x40
151#define EXT_MEM_CTL0_SEQRESET 0x80
152
153#define EXT_MEM_CTL1 0x71
154#define EXT_MEM_CTL1_PAR 0x00
155#define EXT_MEM_CTL1_SERPAR 0x01
156#define EXT_MEM_CTL1_SER 0x03
157#define EXT_MEM_CTL1_SYNC 0x04
158#define EXT_MEM_CTL1_VRAM 0x08
159#define EXT_MEM_CTL1_4K_REFRESH 0x10
160#define EXT_MEM_CTL1_256Kx4 0x00
161#define EXT_MEM_CTL1_512Kx8 0x40
162#define EXT_MEM_CTL1_1Mx16 0x60
163
164#define EXT_MEM_CTL2 0x72
165#define MEM_CTL2_SIZE_1MB 0x00
166#define MEM_CTL2_SIZE_2MB 0x01
167#define MEM_CTL2_SIZE_4MB 0x02
168#define MEM_CTL2_SIZE_MASK 0x03
169#define MEM_CTL2_64BIT 0x04
170
171#define EXT_HIDDEN_CTL1 0x73
172
173#define EXT_FIFO_CTL 0x74
174
175#define EXT_SEQ_MISC 0x77
176#define EXT_SEQ_MISC_8 0x01
177#define EXT_SEQ_MISC_16_RGB565 0x02
178#define EXT_SEQ_MISC_32 0x03
179#define EXT_SEQ_MISC_24_RGB888 0x04
180#define EXT_SEQ_MISC_16_RGB555 0x06
181#define EXT_SEQ_MISC_8_RGB332 0x09
182#define EXT_SEQ_MISC_16_RGB444 0x0a
183
184#define EXT_HIDDEN_CTL4 0x7a
185
186#define CURS_MEM_START 0x7e /* bits 23..12 */
187
188#define CAP_PIP_X_START 0x80
189#define CAP_PIP_X_END 0x82
190#define CAP_PIP_Y_START 0x84
191#define CAP_PIP_Y_END 0x86
192
193#define EXT_CAP_CTL1 0x88
194
195#define EXT_CAP_CTL2 0x89
196#define EXT_CAP_CTL2_ODDFRAMEIRQ 0x01
197#define EXT_CAP_CTL2_ANYFRAMEIRQ 0x02
198
199#define BM_CTRL0 0x9c
200#define BM_CTRL1 0x9d
201
202#define EXT_CAP_MODE1 0xa4
203#define EXT_CAP_MODE1_8BIT 0x01 /* enable 8bit capture mode */
204#define EXT_CAP_MODE1_CCIR656 0x02 /* CCIR656 mode */
205#define EXT_CAP_MODE1_IGNOREVGT 0x04 /* ignore VGT */
206#define EXT_CAP_MODE1_ALTFIFO 0x10 /* use alternate FIFO for capture */
207#define EXT_CAP_MODE1_SWAPUV 0x20 /* swap UV bytes */
208#define EXT_CAP_MODE1_MIRRORY 0x40 /* mirror vertically */
209#define EXT_CAP_MODE1_MIRRORX 0x80 /* mirror horizontally */
210
211#define EXT_CAP_MODE2 0xa5
212#define EXT_CAP_MODE2_CCIRINVOE 0x01
213#define EXT_CAP_MODE2_CCIRINVVGT 0x02
214#define EXT_CAP_MODE2_CCIRINVHGT 0x04
215#define EXT_CAP_MODE2_CCIRINVDG 0x08
216#define EXT_CAP_MODE2_DATEND 0x10
217#define EXT_CAP_MODE2_CCIRDGH 0x20
218#define EXT_CAP_MODE2_FIXSONY 0x40
219#define EXT_CAP_MODE2_SYNCFREEZE 0x80
220
221#define EXT_TV_CTL 0xae
222
223#define EXT_DCLK_MULT 0xb0
224#define EXT_DCLK_DIV 0xb1
225#define EXT_DCLK_DIV_VFSEL 0x20
226#define EXT_MCLK_MULT 0xb2
227#define EXT_MCLK_DIV 0xb3
228
229#define EXT_LATCH1 0xb5
230#define EXT_LATCH1_VAFC_EN 0x01 /* enable VAFC */
231
232#define EXT_FEATURE 0xb7
233#define EXT_FEATURE_BUS_MASK 0x07 /* host bus mask */
234#define EXT_FEATURE_BUS_PCI 0x00
235#define EXT_FEATURE_BUS_VL_STD 0x04
236#define EXT_FEATURE_BUS_VL_LINEAR 0x05
237#define EXT_FEATURE_1682 0x20 /* IGS 1682 compatibility */
238
239#define EXT_LATCH2 0xb6
240#define EXT_LATCH2_I2C_CLKEN 0x10
241#define EXT_LATCH2_I2C_CLK 0x20
242#define EXT_LATCH2_I2C_DATEN 0x40
243#define EXT_LATCH2_I2C_DAT 0x80
244
245#define EXT_XT_CTL 0xbe
246#define EXT_XT_CAP16 0x04
247#define EXT_XT_LINEARFB 0x08
248#define EXT_XT_PAL 0x10
249
250#define EXT_MEM_START 0xc0 /* ext start address 21 bits */
251#define HOR_PHASE_SHIFT 0xc2 /* high 3 bits */
252#define EXT_SRC_WIDTH 0xc3 /* ext offset phase 10 bits */
253#define EXT_SRC_HEIGHT 0xc4 /* high 6 bits */
254#define EXT_X_START 0xc5 /* ext->screen, 16 bits */
255#define EXT_X_END 0xc7 /* ext->screen, 16 bits */
256#define EXT_Y_START 0xc9 /* ext->screen, 16 bits */
257#define EXT_Y_END 0xcb /* ext->screen, 16 bits */
258#define EXT_SRC_WIN_WIDTH 0xcd /* 8 bits */
259#define EXT_COLOUR_COMPARE 0xce /* 24 bits */
260#define EXT_DDA_X_INIT 0xd1 /* ext->screen 16 bits */
261#define EXT_DDA_X_INC 0xd3 /* ext->screen 16 bits */
262#define EXT_DDA_Y_INIT 0xd5 /* ext->screen 16 bits */
263#define EXT_DDA_Y_INC 0xd7 /* ext->screen 16 bits */
264
265#define EXT_VID_FIFO_CTL 0xd9
266
267#define EXT_VID_FMT 0xdb
268#define EXT_VID_FMT_YUV422 0x00 /* formats - does this cause conversion? */
269#define EXT_VID_FMT_RGB555 0x01
270#define EXT_VID_FMT_RGB565 0x02
271#define EXT_VID_FMT_RGB888_24 0x03
272#define EXT_VID_FMT_RGB888_32 0x04
273#define EXT_VID_FMT_RGB8 0x05
274#define EXT_VID_FMT_RGB4444 0x06
275#define EXT_VID_FMT_RGB8T 0x07
276#define EXT_VID_FMT_DUP_PIX_ZOON 0x08 /* duplicate pixel zoom */
277#define EXT_VID_FMT_MOD_3RD_PIX 0x20 /* modify 3rd duplicated pixel */
278#define EXT_VID_FMT_DBL_H_PIX 0x40 /* double horiz pixels */
279#define EXT_VID_FMT_YUV128 0x80 /* YUV data offset by 128 */
280
281#define EXT_VID_DISP_CTL1 0xdc
282#define EXT_VID_DISP_CTL1_INTRAM 0x01 /* video pixels go to internal RAM */
283#define EXT_VID_DISP_CTL1_IGNORE_CCOMP 0x02 /* ignore colour compare registers */
284#define EXT_VID_DISP_CTL1_NOCLIP 0x04 /* do not clip to 16235,16240 */
285#define EXT_VID_DISP_CTL1_UV_AVG 0x08 /* U/V data is averaged */
286#define EXT_VID_DISP_CTL1_Y128 0x10 /* Y data offset by 128 (if YUV128 set) */
287#define EXT_VID_DISP_CTL1_VINTERPOL_OFF 0x20 /* disable vertical interpolation */
288#define EXT_VID_DISP_CTL1_FULL_WIN 0x40 /* video out window full */
289#define EXT_VID_DISP_CTL1_ENABLE_WINDOW 0x80 /* enable video window */
290
291#define EXT_VID_FIFO_CTL1 0xdd
292#define EXT_VID_FIFO_CTL1_OE_HIGH 0x02
293#define EXT_VID_FIFO_CTL1_INTERLEAVE 0x04 /* enable interleaved memory read */
294
295#define EXT_ROM_UCB4GH 0xe5
296#define EXT_ROM_UCB4GH_FREEZE 0x02 /* capture frozen */
297#define EXT_ROM_UCB4GH_ODDFRAME 0x04 /* 1 = odd frame captured */
298#define EXT_ROM_UCB4GH_1HL 0x08 /* first horizonal line after VGT falling edge */
299#define EXT_ROM_UCB4GH_ODD 0x10 /* odd frame indicator */
300#define EXT_ROM_UCB4GH_INTSTAT 0x20 /* video interrupt */
301
302#define VFAC_CTL1 0xe8
303#define VFAC_CTL1_CAPTURE 0x01 /* capture enable (only when VSYNC high)*/
304#define VFAC_CTL1_VFAC_ENABLE 0x02 /* vfac enable */
305#define VFAC_CTL1_FREEZE_CAPTURE 0x04 /* freeze capture */
306#define VFAC_CTL1_FREEZE_CAPTURE_SYNC 0x08 /* sync freeze capture */
307#define VFAC_CTL1_VALIDFRAME_SRC 0x10 /* select valid frame source */
308#define VFAC_CTL1_PHILIPS 0x40 /* select Philips mode */
309#define VFAC_CTL1_MODVINTERPOLCLK 0x80 /* modify vertical interpolation clocl */
310
311#define VFAC_CTL2 0xe9
312#define VFAC_CTL2_INVERT_VIDDATAVALID 0x01 /* invert video data valid */
313#define VFAC_CTL2_INVERT_GRAPHREADY 0x02 /* invert graphic ready output sig */
314#define VFAC_CTL2_INVERT_DATACLK 0x04 /* invert data clock signal */
315#define VFAC_CTL2_INVERT_HSYNC 0x08 /* invert hsync input */
316#define VFAC_CTL2_INVERT_VSYNC 0x10 /* invert vsync input */
317#define VFAC_CTL2_INVERT_FRAME 0x20 /* invert frame odd/even input */
318#define VFAC_CTL2_INVERT_BLANK 0x40 /* invert blank output */
319#define VFAC_CTL2_INVERT_OVSYNC 0x80 /* invert other vsync input */
320
321#define VFAC_CTL3 0xea
322#define VFAC_CTL3_CAP_LARGE_FIFO 0x01 /* large capture fifo */
323#define VFAC_CTL3_CAP_INTERLACE 0x02 /* capture odd and even fields */
324#define VFAC_CTL3_CAP_HOLD_4NS 0x00 /* hold capture data for 4ns */
325#define VFAC_CTL3_CAP_HOLD_2NS 0x04 /* hold capture data for 2ns */
326#define VFAC_CTL3_CAP_HOLD_6NS 0x08 /* hold capture data for 6ns */
327#define VFAC_CTL3_CAP_HOLD_0NS 0x0c /* hold capture data for 0ns */
328#define VFAC_CTL3_CHROMAKEY 0x20 /* capture data will be chromakeyed */
329#define VFAC_CTL3_CAP_IRQ 0x40 /* enable capture interrupt */
330
331#define CAP_MEM_START 0xeb /* 18 bits */
332#define CAP_MAP_WIDTH 0xed /* high 6 bits */
333#define CAP_PITCH 0xee /* 8 bits */
334
335#define CAP_CTL_MISC 0xef
336#define CAP_CTL_MISC_HDIV 0x01
337#define CAP_CTL_MISC_HDIV4 0x02
338#define CAP_CTL_MISC_ODDEVEN 0x04
339#define CAP_CTL_MISC_HSYNCDIV2 0x08
340#define CAP_CTL_MISC_SYNCTZHIGH 0x10
341#define CAP_CTL_MISC_SYNCTZOR 0x20
342#define CAP_CTL_MISC_DISPUSED 0x80
343
344#define REG_BANK 0xfa
345#define REG_BANK_X 0x00
346#define REG_BANK_Y 0x01
347#define REG_BANK_W 0x02
348#define REG_BANK_T 0x03
349#define REG_BANK_J 0x04
350#define REG_BANK_K 0x05
351
352/*
353 * Bus-master
354 */
355#define BM_VID_ADDR_LOW 0xbc040
356#define BM_VID_ADDR_HIGH 0xbc044
357#define BM_ADDRESS_LOW 0xbc080
358#define BM_ADDRESS_HIGH 0xbc084
359#define BM_LENGTH 0xbc088
360#define BM_CONTROL 0xbc08c
361#define BM_CONTROL_ENABLE 0x01 /* enable transfer */
362#define BM_CONTROL_IRQEN 0x02 /* enable IRQ at end of transfer */
363#define BM_CONTROL_INIT 0x04 /* initialise status & count */
364#define BM_COUNT 0xbc090 /* read-only */
365
366/*
367 * TV registers
368 */
369#define TV_VBLANK_EVEN_START 0xbe43c
370#define TV_VBLANK_EVEN_END 0xbe440
371#define TV_VBLANK_ODD_START 0xbe444
372#define TV_VBLANK_ODD_END 0xbe448
373#define TV_SYNC_YGAIN 0xbe44c
374#define TV_UV_GAIN 0xbe450
375#define TV_PED_UVDET 0xbe454
376#define TV_UV_BURST_AMP 0xbe458
377#define TV_HSYNC_START 0xbe45c
378#define TV_HSYNC_END 0xbe460
379#define TV_Y_DELAY1 0xbe464
380#define TV_Y_DELAY2 0xbe468
381#define TV_UV_DELAY1 0xbe46c
382#define TV_BURST_START 0xbe470
383#define TV_BURST_END 0xbe474
384#define TV_HBLANK_START 0xbe478
385#define TV_HBLANK_END 0xbe47c
386#define TV_PED_EVEN_START 0xbe480
387#define TV_PED_EVEN_END 0xbe484
388#define TV_PED_ODD_START 0xbe488
389#define TV_PED_ODD_END 0xbe48c
390#define TV_VSYNC_EVEN_START 0xbe490
391#define TV_VSYNC_EVEN_END 0xbe494
392#define TV_VSYNC_ODD_START 0xbe498
393#define TV_VSYNC_ODD_END 0xbe49c
394#define TV_SCFL 0xbe4a0
395#define TV_SCFH 0xbe4a4
396#define TV_SCP 0xbe4a8
397#define TV_DELAYBYPASS 0xbe4b4
398#define TV_EQL_END 0xbe4bc
399#define TV_SERR_START 0xbe4c0
400#define TV_SERR_END 0xbe4c4
401#define TV_CTL 0xbe4dc /* reflects a previous register- MVFCLR, MVPCLR etc P241*/
402#define TV_VSYNC_VGA_HS 0xbe4e8
403#define TV_FLICK_XMIN 0xbe514
404#define TV_FLICK_XMAX 0xbe518
405#define TV_FLICK_YMIN 0xbe51c
406#define TV_FLICK_YMAX 0xbe520
407
408/*
409 * Graphics Co-processor
410 */
411#define CO_REG_CONTROL 0xbf011
412#define CO_CTRL_BUSY 0x80
413#define CO_CTRL_CMDFULL 0x04
414#define CO_CTRL_FIFOEMPTY 0x02
415#define CO_CTRL_READY 0x01
416
417#define CO_REG_SRC_WIDTH 0xbf018
418#define CO_REG_PIXFMT 0xbf01c
419#define CO_PIXFMT_32BPP 0x03
420#define CO_PIXFMT_24BPP 0x02
421#define CO_PIXFMT_16BPP 0x01
422#define CO_PIXFMT_8BPP 0x00
423
424#define CO_REG_FGMIX 0xbf048
425#define CO_FG_MIX_ZERO 0x00
426#define CO_FG_MIX_SRC_AND_DST 0x01
427#define CO_FG_MIX_SRC_AND_NDST 0x02
428#define CO_FG_MIX_SRC 0x03
429#define CO_FG_MIX_NSRC_AND_DST 0x04
430#define CO_FG_MIX_DST 0x05
431#define CO_FG_MIX_SRC_XOR_DST 0x06
432#define CO_FG_MIX_SRC_OR_DST 0x07
433#define CO_FG_MIX_NSRC_AND_NDST 0x08
434#define CO_FG_MIX_SRC_XOR_NDST 0x09
435#define CO_FG_MIX_NDST 0x0a
436#define CO_FG_MIX_SRC_OR_NDST 0x0b
437#define CO_FG_MIX_NSRC 0x0c
438#define CO_FG_MIX_NSRC_OR_DST 0x0d
439#define CO_FG_MIX_NSRC_OR_NDST 0x0e
440#define CO_FG_MIX_ONES 0x0f
441
442#define CO_REG_FGCOLOUR 0xbf058
443#define CO_REG_BGCOLOUR 0xbf05c
444#define CO_REG_PIXWIDTH 0xbf060
445#define CO_REG_PIXHEIGHT 0xbf062
446#define CO_REG_X_PHASE 0xbf078
447#define CO_REG_CMD_L 0xbf07c
448#define CO_CMD_L_PATTERN_FGCOL 0x8000
449#define CO_CMD_L_INC_LEFT 0x0004
450#define CO_CMD_L_INC_UP 0x0002
451
452#define CO_REG_CMD_H 0xbf07e
453#define CO_CMD_H_BGSRCMAP 0x8000 /* otherwise bg colour */
454#define CO_CMD_H_FGSRCMAP 0x2000 /* otherwise fg colour */
455#define CO_CMD_H_BLITTER 0x0800
456
457#define CO_REG_SRC1_PTR 0xbf170
458#define CO_REG_SRC2_PTR 0xbf174
459#define CO_REG_DEST_PTR 0xbf178
460#define CO_REG_DEST_WIDTH 0xbf218
461
462/*
463 * Private structure
464 */
465struct cfb_info;
466
467struct cyberpro_info {
468 struct pci_dev *dev;
469 unsigned char __iomem *regs;
470 char __iomem *fb;
471 char dev_name[32];
472 unsigned int fb_size;
473 unsigned int chip_id;
474
475 /*
476 * The following is a pointer to be passed into the
477 * functions below. The modules outside the main
478 * cyber2000fb.c driver have no knowledge as to what
479 * is within this structure.
480 */
481 struct cfb_info *info;
482
483 /*
484 * Use these to enable the BM or TV registers. In an SMP
485 * environment, these two function pointers should only be
486 * called from the module_init() or module_exit()
487 * functions.
488 */
489 void (*enable_extregs)(struct cfb_info *);
490 void (*disable_extregs)(struct cfb_info *);
491};
492
493#define ID_IGA_1682 0
494#define ID_CYBERPRO_2000 1
495#define ID_CYBERPRO_2010 2
496#define ID_CYBERPRO_5000 3
497
498struct fb_var_screeninfo;
499
500/*
501 * Note! Writing to the Cyber20x0 registers from an interrupt
502 * routine is definitely a bad idea atm.
503 */
504int cyber2000fb_attach(struct cyberpro_info *info, int idx);
505void cyber2000fb_detach(int idx);
506void cyber2000fb_enable_extregs(struct cfb_info *cfb);
507void cyber2000fb_disable_extregs(struct cfb_info *cfb);
508void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var);