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gerrit-public.fairphone.software / kernel / msm-4.9 / 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 / . / drivers / video / w100fb.h
blob: 41624f961237cdcee3b34ada2d785085dc0f5d82 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame^]1/*
2 * linux/drivers/video/w100fb.h
3 *
4 * Frame Buffer Device for ATI w100 (Wallaby)
5 *
6 * Copyright (C) 2002, ATI Corp.
7 * Copyright (C) 2004-2005 Richard Purdie
8 *
9 * Modified to work with 2.6 by Richard Purdie <rpurdie@rpsys.net>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16
17#if !defined (_W100FB_H)
18#define _W100FB_H
19
20/* Block CIF Start: */
21#define mmCHIP_ID 0x0000
22#define mmREVISION_ID 0x0004
23#define mmWRAP_BUF_A 0x0008
24#define mmWRAP_BUF_B 0x000C
25#define mmWRAP_TOP_DIR 0x0010
26#define mmWRAP_START_DIR 0x0014
27#define mmCIF_CNTL 0x0018
28#define mmCFGREG_BASE 0x001C
29#define mmCIF_IO 0x0020
30#define mmCIF_READ_DBG 0x0024
31#define mmCIF_WRITE_DBG 0x0028
32#define cfgIND_ADDR_A_0 0x0000
33#define cfgIND_ADDR_A_1 0x0001
34#define cfgIND_ADDR_A_2 0x0002
35#define cfgIND_DATA_A 0x0003
36#define cfgREG_BASE 0x0004
37#define cfgINTF_CNTL 0x0005
38#define cfgSTATUS 0x0006
39#define cfgCPU_DEFAULTS 0x0007
40#define cfgIND_ADDR_B_0 0x0008
41#define cfgIND_ADDR_B_1 0x0009
42#define cfgIND_ADDR_B_2 0x000A
43#define cfgIND_DATA_B 0x000B
44#define cfgPM4_RPTR 0x000C
45#define cfgSCRATCH 0x000D
46#define cfgPM4_WRPTR_0 0x000E
47#define cfgPM4_WRPTR_1 0x000F
48/* Block CIF End: */
49
50/* Block CP Start: */
51#define mmSCRATCH_UMSK 0x0280
52#define mmSCRATCH_ADDR 0x0284
53#define mmGEN_INT_CNTL 0x0200
54#define mmGEN_INT_STATUS 0x0204
55/* Block CP End: */
56
57/* Block DISPLAY Start: */
58#define mmLCD_FORMAT 0x0410
59#define mmGRAPHIC_CTRL 0x0414
60#define mmGRAPHIC_OFFSET 0x0418
61#define mmGRAPHIC_PITCH 0x041C
62#define mmCRTC_TOTAL 0x0420
63#define mmACTIVE_H_DISP 0x0424
64#define mmACTIVE_V_DISP 0x0428
65#define mmGRAPHIC_H_DISP 0x042C
66#define mmGRAPHIC_V_DISP 0x0430
67#define mmVIDEO_CTRL 0x0434
68#define mmGRAPHIC_KEY 0x0438
69#define mmBRIGHTNESS_CNTL 0x045C
70#define mmDISP_INT_CNTL 0x0488
71#define mmCRTC_SS 0x048C
72#define mmCRTC_LS 0x0490
73#define mmCRTC_REV 0x0494
74#define mmCRTC_DCLK 0x049C
75#define mmCRTC_GS 0x04A0
76#define mmCRTC_VPOS_GS 0x04A4
77#define mmCRTC_GCLK 0x04A8
78#define mmCRTC_GOE 0x04AC
79#define mmCRTC_FRAME 0x04B0
80#define mmCRTC_FRAME_VPOS 0x04B4
81#define mmGPIO_DATA 0x04B8
82#define mmGPIO_CNTL1 0x04BC
83#define mmGPIO_CNTL2 0x04C0
84#define mmLCDD_CNTL1 0x04C4
85#define mmLCDD_CNTL2 0x04C8
86#define mmGENLCD_CNTL1 0x04CC
87#define mmGENLCD_CNTL2 0x04D0
88#define mmDISP_DEBUG 0x04D4
89#define mmDISP_DB_BUF_CNTL 0x04D8
90#define mmDISP_CRC_SIG 0x04DC
91#define mmCRTC_DEFAULT_COUNT 0x04E0
92#define mmLCD_BACKGROUND_COLOR 0x04E4
93#define mmCRTC_PS2 0x04E8
94#define mmCRTC_PS2_VPOS 0x04EC
95#define mmCRTC_PS1_ACTIVE 0x04F0
96#define mmCRTC_PS1_NACTIVE 0x04F4
97#define mmCRTC_GCLK_EXT 0x04F8
98#define mmCRTC_ALW 0x04FC
99#define mmCRTC_ALW_VPOS 0x0500
100#define mmCRTC_PSK 0x0504
101#define mmCRTC_PSK_HPOS 0x0508
102#define mmCRTC_CV4_START 0x050C
103#define mmCRTC_CV4_END 0x0510
104#define mmCRTC_CV4_HPOS 0x0514
105#define mmCRTC_ECK 0x051C
106#define mmREFRESH_CNTL 0x0520
107#define mmGENLCD_CNTL3 0x0524
108#define mmGPIO_DATA2 0x0528
109#define mmGPIO_CNTL3 0x052C
110#define mmGPIO_CNTL4 0x0530
111#define mmCHIP_STRAP 0x0534
112#define mmDISP_DEBUG2 0x0538
113#define mmDEBUG_BUS_CNTL 0x053C
114#define mmGAMMA_VALUE1 0x0540
115#define mmGAMMA_VALUE2 0x0544
116#define mmGAMMA_SLOPE 0x0548
117#define mmGEN_STATUS 0x054C
118#define mmHW_INT 0x0550
119/* Block DISPLAY End: */
120
121/* Block GFX Start: */
122#define mmBRUSH_OFFSET 0x108C
123#define mmBRUSH_Y_X 0x1074
124#define mmDEFAULT_PITCH_OFFSET 0x10A0
125#define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8
126#define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC
127#define mmGLOBAL_ALPHA 0x1210
128#define mmFILTER_COEF 0x1214
129#define mmMVC_CNTL_START 0x11E0
130#define mmE2_ARITHMETIC_CNTL 0x1220
131#define mmENG_CNTL 0x13E8
132#define mmENG_PERF_CNT 0x13F0
133/* Block GFX End: */
134
135/* Block IDCT Start: */
136#define mmIDCT_RUNS 0x0C00
137#define mmIDCT_LEVELS 0x0C04
138#define mmIDCT_CONTROL 0x0C3C
139#define mmIDCT_AUTH_CONTROL 0x0C08
140#define mmIDCT_AUTH 0x0C0C
141/* Block IDCT End: */
142
143/* Block MC Start: */
144#define mmMEM_CNTL 0x0180
145#define mmMEM_ARB 0x0184
146#define mmMC_FB_LOCATION 0x0188
147#define mmMEM_EXT_CNTL 0x018C
148#define mmMC_EXT_MEM_LOCATION 0x0190
149#define mmMEM_EXT_TIMING_CNTL 0x0194
150#define mmMEM_SDRAM_MODE_REG 0x0198
151#define mmMEM_IO_CNTL 0x019C
152#define mmMC_DEBUG 0x01A0
153#define mmMC_BIST_CTRL 0x01A4
154#define mmMC_BIST_COLLAR_READ 0x01A8
155#define mmTC_MISMATCH 0x01AC
156#define mmMC_PERF_MON_CNTL 0x01B0
157#define mmMC_PERF_COUNTERS 0x01B4
158/* Block MC End: */
159
160/* Block RBBM Start: */
161#define mmWAIT_UNTIL 0x1400
162#define mmISYNC_CNTL 0x1404
163#define mmRBBM_CNTL 0x0144
164#define mmNQWAIT_UNTIL 0x0150
165/* Block RBBM End: */
166
167/* Block CG Start: */
168#define mmCLK_PIN_CNTL 0x0080
169#define mmPLL_REF_FB_DIV 0x0084
170#define mmPLL_CNTL 0x0088
171#define mmSCLK_CNTL 0x008C
172#define mmPCLK_CNTL 0x0090
173#define mmCLK_TEST_CNTL 0x0094
174#define mmPWRMGT_CNTL 0x0098
175#define mmPWRMGT_STATUS 0x009C
176/* Block CG End: */
177
178/* default value definitions */
179#define defWRAP_TOP_DIR 0x00000000
180#define defWRAP_START_DIR 0x00000000
181#define defCFGREG_BASE 0x00000000
182#define defCIF_IO 0x000C0902
183#define defINTF_CNTL 0x00000011
184#define defCPU_DEFAULTS 0x00000006
185#define defHW_INT 0x00000000
186#define defMC_EXT_MEM_LOCATION 0x07ff0000
187#define defTC_MISMATCH 0x00000000
188
189#define W100_CFG_BASE 0x0
190#define W100_CFG_LEN 0x10
191#define W100_REG_BASE 0x10000
192#define W100_REG_LEN 0x2000
193#define MEM_INT_BASE_VALUE 0x100000
194#define MEM_INT_TOP_VALUE_W100 0x15ffff
195#define MEM_EXT_BASE_VALUE 0x800000
196#define MEM_EXT_TOP_VALUE 0x9fffff
197#define WRAP_BUF_BASE_VALUE 0x80000
198#define WRAP_BUF_TOP_VALUE 0xbffff
199
200
201/* data structure definitions */
202
203struct wrap_top_dir_t {
204 unsigned long top_addr : 23;
205 unsigned long : 9;
206} __attribute__((packed));
207
208union wrap_top_dir_u {
209 unsigned long val : 32;
210 struct wrap_top_dir_t f;
211} __attribute__((packed));
212
213struct wrap_start_dir_t {
214 unsigned long start_addr : 23;
215 unsigned long : 9;
216} __attribute__((packed));
217
218union wrap_start_dir_u {
219 unsigned long val : 32;
220 struct wrap_start_dir_t f;
221} __attribute__((packed));
222
223struct cif_cntl_t {
224 unsigned long swap_reg : 2;
225 unsigned long swap_fbuf_1 : 2;
226 unsigned long swap_fbuf_2 : 2;
227 unsigned long swap_fbuf_3 : 2;
228 unsigned long pmi_int_disable : 1;
229 unsigned long pmi_schmen_disable : 1;
230 unsigned long intb_oe : 1;
231 unsigned long en_wait_to_compensate_dq_prop_dly : 1;
232 unsigned long compensate_wait_rd_size : 2;
233 unsigned long wait_asserted_timeout_val : 2;
234 unsigned long wait_masked_val : 2;
235 unsigned long en_wait_timeout : 1;
236 unsigned long en_one_clk_setup_before_wait : 1;
237 unsigned long interrupt_active_high : 1;
238 unsigned long en_overwrite_straps : 1;
239 unsigned long strap_wait_active_hi : 1;
240 unsigned long lat_busy_count : 2;
241 unsigned long lat_rd_pm4_sclk_busy : 1;
242 unsigned long dis_system_bits : 1;
243 unsigned long dis_mr : 1;
244 unsigned long cif_spare_1 : 4;
245} __attribute__((packed));
246
247union cif_cntl_u {
248 unsigned long val : 32;
249 struct cif_cntl_t f;
250} __attribute__((packed));
251
252struct cfgreg_base_t {
253 unsigned long cfgreg_base : 24;
254 unsigned long : 8;
255} __attribute__((packed));
256
257union cfgreg_base_u {
258 unsigned long val : 32;
259 struct cfgreg_base_t f;
260} __attribute__((packed));
261
262struct cif_io_t {
263 unsigned long dq_srp : 1;
264 unsigned long dq_srn : 1;
265 unsigned long dq_sp : 4;
266 unsigned long dq_sn : 4;
267 unsigned long waitb_srp : 1;
268 unsigned long waitb_srn : 1;
269 unsigned long waitb_sp : 4;
270 unsigned long waitb_sn : 4;
271 unsigned long intb_srp : 1;
272 unsigned long intb_srn : 1;
273 unsigned long intb_sp : 4;
274 unsigned long intb_sn : 4;
275 unsigned long : 2;
276} __attribute__((packed));
277
278union cif_io_u {
279 unsigned long val : 32;
280 struct cif_io_t f;
281} __attribute__((packed));
282
283struct cif_read_dbg_t {
284 unsigned long unpacker_pre_fetch_trig_gen : 2;
285 unsigned long dly_second_rd_fetch_trig : 1;
286 unsigned long rst_rd_burst_id : 1;
287 unsigned long dis_rd_burst_id : 1;
288 unsigned long en_block_rd_when_packer_is_not_emp : 1;
289 unsigned long dis_pre_fetch_cntl_sm : 1;
290 unsigned long rbbm_chrncy_dis : 1;
291 unsigned long rbbm_rd_after_wr_lat : 2;
292 unsigned long dis_be_during_rd : 1;
293 unsigned long one_clk_invalidate_pulse : 1;
294 unsigned long dis_chnl_priority : 1;
295 unsigned long rst_read_path_a_pls : 1;
296 unsigned long rst_read_path_b_pls : 1;
297 unsigned long dis_reg_rd_fetch_trig : 1;
298 unsigned long dis_rd_fetch_trig_from_ind_addr : 1;
299 unsigned long dis_rd_same_byte_to_trig_fetch : 1;
300 unsigned long dis_dir_wrap : 1;
301 unsigned long dis_ring_buf_to_force_dec : 1;
302 unsigned long dis_addr_comp_in_16bit : 1;
303 unsigned long clr_w : 1;
304 unsigned long err_rd_tag_is_3 : 1;
305 unsigned long err_load_when_ful_a : 1;
306 unsigned long err_load_when_ful_b : 1;
307 unsigned long : 7;
308} __attribute__((packed));
309
310union cif_read_dbg_u {
311 unsigned long val : 32;
312 struct cif_read_dbg_t f;
313} __attribute__((packed));
314
315struct cif_write_dbg_t {
316 unsigned long packer_timeout_count : 2;
317 unsigned long en_upper_load_cond : 1;
318 unsigned long en_chnl_change_cond : 1;
319 unsigned long dis_addr_comp_cond : 1;
320 unsigned long dis_load_same_byte_addr_cond : 1;
321 unsigned long dis_timeout_cond : 1;
322 unsigned long dis_timeout_during_rbbm : 1;
323 unsigned long dis_packer_ful_during_rbbm_timeout : 1;
324 unsigned long en_dword_split_to_rbbm : 1;
325 unsigned long en_dummy_val : 1;
326 unsigned long dummy_val_sel : 1;
327 unsigned long mask_pm4_wrptr_dec : 1;
328 unsigned long dis_mc_clean_cond : 1;
329 unsigned long err_two_reqi_during_ful : 1;
330 unsigned long err_reqi_during_idle_clk : 1;
331 unsigned long err_global : 1;
332 unsigned long en_wr_buf_dbg_load : 1;
333 unsigned long en_wr_buf_dbg_path : 1;
334 unsigned long sel_wr_buf_byte : 3;
335 unsigned long dis_rd_flush_wr : 1;
336 unsigned long dis_packer_ful_cond : 1;
337 unsigned long dis_invalidate_by_ops_chnl : 1;
338 unsigned long en_halt_when_reqi_err : 1;
339 unsigned long cif_spare_2 : 5;
340 unsigned long : 1;
341} __attribute__((packed));
342
343union cif_write_dbg_u {
344 unsigned long val : 32;
345 struct cif_write_dbg_t f;
346} __attribute__((packed));
347
348
349struct intf_cntl_t {
350 unsigned char ad_inc_a : 1;
351 unsigned char ring_buf_a : 1;
352 unsigned char rd_fetch_trigger_a : 1;
353 unsigned char rd_data_rdy_a : 1;
354 unsigned char ad_inc_b : 1;
355 unsigned char ring_buf_b : 1;
356 unsigned char rd_fetch_trigger_b : 1;
357 unsigned char rd_data_rdy_b : 1;
358} __attribute__((packed));
359
360union intf_cntl_u {
361 unsigned char val : 8;
362 struct intf_cntl_t f;
363} __attribute__((packed));
364
365struct cpu_defaults_t {
366 unsigned char unpack_rd_data : 1;
367 unsigned char access_ind_addr_a: 1;
368 unsigned char access_ind_addr_b: 1;
369 unsigned char access_scratch_reg : 1;
370 unsigned char pack_wr_data : 1;
371 unsigned char transition_size : 1;
372 unsigned char en_read_buf_mode : 1;
373 unsigned char rd_fetch_scratch : 1;
374} __attribute__((packed));
375
376union cpu_defaults_u {
377 unsigned char val : 8;
378 struct cpu_defaults_t f;
379} __attribute__((packed));
380
381struct video_ctrl_t {
382 unsigned long video_mode : 1;
383 unsigned long keyer_en : 1;
384 unsigned long en_video_req : 1;
385 unsigned long en_graphic_req_video : 1;
386 unsigned long en_video_crtc : 1;
387 unsigned long video_hor_exp : 2;
388 unsigned long video_ver_exp : 2;
389 unsigned long uv_combine : 1;
390 unsigned long total_req_video : 9;
391 unsigned long video_ch_sel : 1;
392 unsigned long video_portrait : 2;
393 unsigned long yuv2rgb_en : 1;
394 unsigned long yuv2rgb_option : 1;
395 unsigned long video_inv_hor : 1;
396 unsigned long video_inv_ver : 1;
397 unsigned long gamma_sel : 2;
398 unsigned long dis_limit : 1;
399 unsigned long en_uv_hblend : 1;
400 unsigned long rgb_gamma_sel : 2;
401} __attribute__((packed));
402
403union video_ctrl_u {
404 unsigned long val : 32;
405 struct video_ctrl_t f;
406} __attribute__((packed));
407
408struct disp_db_buf_cntl_rd_t {
409 unsigned long en_db_buf : 1;
410 unsigned long update_db_buf_done : 1;
411 unsigned long db_buf_cntl : 6;
412 unsigned long : 24;
413} __attribute__((packed));
414
415union disp_db_buf_cntl_rd_u {
416 unsigned long val : 32;
417 struct disp_db_buf_cntl_rd_t f;
418} __attribute__((packed));
419
420struct disp_db_buf_cntl_wr_t {
421 unsigned long en_db_buf : 1;
422 unsigned long update_db_buf : 1;
423 unsigned long db_buf_cntl : 6;
424 unsigned long : 24;
425} __attribute__((packed));
426
427union disp_db_buf_cntl_wr_u {
428 unsigned long val : 32;
429 struct disp_db_buf_cntl_wr_t f;
430} __attribute__((packed));
431
432struct gamma_value1_t {
433 unsigned long gamma1 : 8;
434 unsigned long gamma2 : 8;
435 unsigned long gamma3 : 8;
436 unsigned long gamma4 : 8;
437} __attribute__((packed));
438
439union gamma_value1_u {
440 unsigned long val : 32;
441 struct gamma_value1_t f;
442} __attribute__((packed));
443
444struct gamma_value2_t {
445 unsigned long gamma5 : 8;
446 unsigned long gamma6 : 8;
447 unsigned long gamma7 : 8;
448 unsigned long gamma8 : 8;
449} __attribute__((packed));
450
451union gamma_value2_u {
452 unsigned long val : 32;
453 struct gamma_value2_t f;
454} __attribute__((packed));
455
456struct gamma_slope_t {
457 unsigned long slope1 : 3;
458 unsigned long slope2 : 3;
459 unsigned long slope3 : 3;
460 unsigned long slope4 : 3;
461 unsigned long slope5 : 3;
462 unsigned long slope6 : 3;
463 unsigned long slope7 : 3;
464 unsigned long slope8 : 3;
465 unsigned long : 8;
466} __attribute__((packed));
467
468union gamma_slope_u {
469 unsigned long val : 32;
470 struct gamma_slope_t f;
471} __attribute__((packed));
472
473struct mc_ext_mem_location_t {
474 unsigned long mc_ext_mem_start : 16;
475 unsigned long mc_ext_mem_top : 16;
476} __attribute__((packed));
477
478union mc_ext_mem_location_u {
479 unsigned long val : 32;
480 struct mc_ext_mem_location_t f;
481} __attribute__((packed));
482
483struct clk_pin_cntl_t {
484 unsigned long osc_en : 1;
485 unsigned long osc_gain : 5;
486 unsigned long dont_use_xtalin : 1;
487 unsigned long xtalin_pm_en : 1;
488 unsigned long xtalin_dbl_en : 1;
489 unsigned long : 7;
490 unsigned long cg_debug : 16;
491} __attribute__((packed));
492
493union clk_pin_cntl_u {
494 unsigned long val : 32;
495 struct clk_pin_cntl_t f;
496} __attribute__((packed));
497
498struct pll_ref_fb_div_t {
499 unsigned long pll_ref_div : 4;
500 unsigned long : 4;
501 unsigned long pll_fb_div_int : 6;
502 unsigned long : 2;
503 unsigned long pll_fb_div_frac : 3;
504 unsigned long : 1;
505 unsigned long pll_reset_time : 4;
506 unsigned long pll_lock_time : 8;
507} __attribute__((packed));
508
509union pll_ref_fb_div_u {
510 unsigned long val : 32;
511 struct pll_ref_fb_div_t f;
512} __attribute__((packed));
513
514struct pll_cntl_t {
515 unsigned long pll_pwdn : 1;
516 unsigned long pll_reset : 1;
517 unsigned long pll_pm_en : 1;
518 unsigned long pll_mode : 1;
519 unsigned long pll_refclk_sel : 1;
520 unsigned long pll_fbclk_sel : 1;
521 unsigned long pll_tcpoff : 1;
522 unsigned long pll_pcp : 3;
523 unsigned long pll_pvg : 3;
524 unsigned long pll_vcofr : 1;
525 unsigned long pll_ioffset : 2;
526 unsigned long pll_pecc_mode : 2;
527 unsigned long pll_pecc_scon : 2;
528 unsigned long pll_dactal : 4;
529 unsigned long pll_cp_clip : 2;
530 unsigned long pll_conf : 3;
531 unsigned long pll_mbctrl : 2;
532 unsigned long pll_ring_off : 1;
533} __attribute__((packed));
534
535union pll_cntl_u {
536 unsigned long val : 32;
537 struct pll_cntl_t f;
538} __attribute__((packed));
539
540struct sclk_cntl_t {
541 unsigned long sclk_src_sel : 2;
542 unsigned long : 2;
543 unsigned long sclk_post_div_fast : 4;
544 unsigned long sclk_clkon_hys : 3;
545 unsigned long sclk_post_div_slow : 4;
546 unsigned long disp_cg_ok2switch_en : 1;
547 unsigned long sclk_force_reg : 1;
548 unsigned long sclk_force_disp : 1;
549 unsigned long sclk_force_mc : 1;
550 unsigned long sclk_force_extmc : 1;
551 unsigned long sclk_force_cp : 1;
552 unsigned long sclk_force_e2 : 1;
553 unsigned long sclk_force_e3 : 1;
554 unsigned long sclk_force_idct : 1;
555 unsigned long sclk_force_bist : 1;
556 unsigned long busy_extend_cp : 1;
557 unsigned long busy_extend_e2 : 1;
558 unsigned long busy_extend_e3 : 1;
559 unsigned long busy_extend_idct : 1;
560 unsigned long : 3;
561} __attribute__((packed));
562
563union sclk_cntl_u {
564 unsigned long val : 32;
565 struct sclk_cntl_t f;
566} __attribute__((packed));
567
568struct pclk_cntl_t {
569 unsigned long pclk_src_sel : 2;
570 unsigned long : 2;
571 unsigned long pclk_post_div : 4;
572 unsigned long : 8;
573 unsigned long pclk_force_disp : 1;
574 unsigned long : 15;
575} __attribute__((packed));
576
577union pclk_cntl_u {
578 unsigned long val : 32;
579 struct pclk_cntl_t f;
580} __attribute__((packed));
581
582struct clk_test_cntl_t {
583 unsigned long testclk_sel : 4;
584 unsigned long : 3;
585 unsigned long start_check_freq : 1;
586 unsigned long tstcount_rst : 1;
587 unsigned long : 15;
588 unsigned long test_count : 8;
589} __attribute__((packed));
590
591union clk_test_cntl_u {
592 unsigned long val : 32;
593 struct clk_test_cntl_t f;
594} __attribute__((packed));
595
596struct pwrmgt_cntl_t {
597 unsigned long pwm_enable : 1;
598 unsigned long : 1;
599 unsigned long pwm_mode_req : 2;
600 unsigned long pwm_wakeup_cond : 2;
601 unsigned long pwm_fast_noml_hw_en : 1;
602 unsigned long pwm_noml_fast_hw_en : 1;
603 unsigned long pwm_fast_noml_cond : 4;
604 unsigned long pwm_noml_fast_cond : 4;
605 unsigned long pwm_idle_timer : 8;
606 unsigned long pwm_busy_timer : 8;
607} __attribute__((packed));
608
609union pwrmgt_cntl_u {
610 unsigned long val : 32;
611 struct pwrmgt_cntl_t f;
612} __attribute__((packed));
613
614#endif
615