| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /****************************************************************************/ |
| 2 | |
| 3 | /* |
| 4 | * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. |
| 5 | * |
| 6 | * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) |
| 7 | */ |
| 8 | |
| 9 | /****************************************************************************/ |
| 10 | #ifndef m527xsim_h |
| 11 | #define m527xsim_h |
| 12 | /****************************************************************************/ |
| 13 | |
| 14 | #include <linux/config.h> |
| 15 | |
| 16 | /* |
| 17 | * Define the 5270/5271 SIM register set addresses. |
| 18 | */ |
| 19 | #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ |
| 20 | #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ |
| 21 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| 22 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
| 23 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
| 24 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
| 25 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
| 26 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
| 27 | #define MCFINTC_IRLR 0x18 /* */ |
| 28 | #define MCFINTC_IACKL 0x19 /* */ |
| 29 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ |
| 30 | |
| 31 | #define MCFINT_VECBASE 64 /* Vector base number */ |
| 32 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ |
| 33 | #define MCFINT_UART1 14 /* Interrupt number for UART1 */ |
| 34 | #define MCFINT_UART2 15 /* Interrupt number for UART2 */ |
| 35 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ |
| 36 | |
| 37 | /* |
| 38 | * SDRAM configuration registers. |
| 39 | */ |
| 40 | #ifdef CONFIG_M5271EVB |
| 41 | #define MCFSIM_DCR 0x40 /* SDRAM control */ |
| 42 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ |
| 43 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ |
| 44 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ |
| 45 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ |
| 46 | #else |
| 47 | #define MCFSIM_DMR 0x40 /* SDRAM mode */ |
| 48 | #define MCFSIM_DCR 0x44 /* SDRAM control */ |
| 49 | #define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ |
| 50 | #define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ |
| 51 | #define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ |
| 52 | #define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ |
| 53 | #define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ |
| 54 | #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ |
| 55 | #endif |
| 56 | |
| 57 | /****************************************************************************/ |
| 58 | #endif /* m527xsim_h */ |