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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Format of an instruction in memory.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 */
10#ifndef _ASM_INST_H
11#define _ASM_INST_H
12
13/*
14 * Major opcodes; before MIPS IV cop1x was called cop3.
15 */
16enum major_op {
17 spec_op, bcond_op, j_op, jal_op,
18 beq_op, bne_op, blez_op, bgtz_op,
19 addi_op, addiu_op, slti_op, sltiu_op,
20 andi_op, ori_op, xori_op, lui_op,
21 cop0_op, cop1_op, cop2_op, cop1x_op,
22 beql_op, bnel_op, blezl_op, bgtzl_op,
23 daddi_op, daddiu_op, ldl_op, ldr_op,
24 major_1c_op, jalx_op, major_1e_op, major_1f_op,
25 lb_op, lh_op, lwl_op, lw_op,
26 lbu_op, lhu_op, lwr_op, lwu_op,
27 sb_op, sh_op, swl_op, sw_op,
28 sdl_op, sdr_op, swr_op, cache_op,
29 ll_op, lwc1_op, lwc2_op, pref_op,
30 lld_op, ldc1_op, ldc2_op, ld_op,
31 sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */
32 scd_op, sdc1_op, sdc2_op, sd_op
33};
34
35/*
36 * func field of spec opcode.
37 */
38enum spec_op {
39 sll_op, movc_op, srl_op, sra_op,
40 sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */
41 jr_op, jalr_op, movz_op, movn_op,
42 syscall_op, break_op, spim_op, sync_op,
43 mfhi_op, mthi_op, mflo_op, mtlo_op,
44 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
45 mult_op, multu_op, div_op, divu_op,
46 dmult_op, dmultu_op, ddiv_op, ddivu_op,
47 add_op, addu_op, sub_op, subu_op,
48 and_op, or_op, xor_op, nor_op,
49 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
50 dadd_op, daddu_op, dsub_op, dsubu_op,
51 tge_op, tgeu_op, tlt_op, tltu_op,
52 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
53 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
54 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
55};
56
57/*
58 * rt field of bcond opcodes.
59 */
60enum rt_op {
61 bltz_op, bgez_op, bltzl_op, bgezl_op,
62 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
63 tgei_op, tgeiu_op, tlti_op, tltiu_op,
64 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
65 bltzal_op, bgezal_op, bltzall_op, bgezall_op
66 /*
67 * The others (0x14 - 0x1f) are unused.
68 */
69};
70
71/*
72 * rs field of cop opcodes.
73 */
74enum cop_op {
75 mfc_op = 0x00, dmfc_op = 0x01,
76 cfc_op = 0x02, mtc_op = 0x04,
77 dmtc_op = 0x05, ctc_op = 0x06,
78 bc_op = 0x08, cop_op = 0x10,
79 copm_op = 0x18
80};
81
82/*
83 * rt field of cop.bc_op opcodes
84 */
85enum bcop_op {
86 bcf_op, bct_op, bcfl_op, bctl_op
87};
88
89/*
90 * func field of cop0 coi opcodes.
91 */
92enum cop0_coi_func {
93 tlbr_op = 0x01, tlbwi_op = 0x02,
94 tlbwr_op = 0x06, tlbp_op = 0x08,
95 rfe_op = 0x10, eret_op = 0x18
96};
97
98/*
99 * func field of cop0 com opcodes.
100 */
101enum cop0_com_func {
102 tlbr1_op = 0x01, tlbw_op = 0x02,
103 tlbp1_op = 0x08, dctr_op = 0x09,
104 dctw_op = 0x0a
105};
106
107/*
108 * fmt field of cop1 opcodes.
109 */
110enum cop1_fmt {
111 s_fmt, d_fmt, e_fmt, q_fmt,
112 w_fmt, l_fmt
113};
114
115/*
116 * func field of cop1 instructions using d, s or w format.
117 */
118enum cop1_sdw_func {
119 fadd_op = 0x00, fsub_op = 0x01,
120 fmul_op = 0x02, fdiv_op = 0x03,
121 fsqrt_op = 0x04, fabs_op = 0x05,
122 fmov_op = 0x06, fneg_op = 0x07,
123 froundl_op = 0x08, ftruncl_op = 0x09,
124 fceill_op = 0x0a, ffloorl_op = 0x0b,
125 fround_op = 0x0c, ftrunc_op = 0x0d,
126 fceil_op = 0x0e, ffloor_op = 0x0f,
127 fmovc_op = 0x11, fmovz_op = 0x12,
128 fmovn_op = 0x13, frecip_op = 0x15,
129 frsqrt_op = 0x16, fcvts_op = 0x20,
130 fcvtd_op = 0x21, fcvte_op = 0x22,
131 fcvtw_op = 0x24, fcvtl_op = 0x25,
132 fcmp_op = 0x30
133};
134
135/*
136 * func field of cop1x opcodes (MIPS IV).
137 */
138enum cop1x_func {
139 lwxc1_op = 0x00, ldxc1_op = 0x01,
140 pfetch_op = 0x07, swxc1_op = 0x08,
141 sdxc1_op = 0x09, madd_s_op = 0x20,
142 madd_d_op = 0x21, madd_e_op = 0x22,
143 msub_s_op = 0x28, msub_d_op = 0x29,
144 msub_e_op = 0x2a, nmadd_s_op = 0x30,
145 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
146 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
147 nmsub_e_op = 0x3a
148};
149
150/*
151 * func field for mad opcodes (MIPS IV).
152 */
153enum mad_func {
154 madd_op = 0x08, msub_op = 0x0a,
155 nmadd_op = 0x0c, nmsub_op = 0x0e
156};
157
158/*
159 * Damn ... bitfields depend from byteorder :-(
160 */
161#ifdef __MIPSEB__
162struct j_format { /* Jump format */
163 unsigned int opcode : 6;
164 unsigned int target : 26;
165};
166
167struct i_format { /* Immediate format (addi, lw, ...) */
168 unsigned int opcode : 6;
169 unsigned int rs : 5;
170 unsigned int rt : 5;
171 signed int simmediate : 16;
172};
173
174struct u_format { /* Unsigned immediate format (ori, xori, ...) */
175 unsigned int opcode : 6;
176 unsigned int rs : 5;
177 unsigned int rt : 5;
178 unsigned int uimmediate : 16;
179};
180
181struct c_format { /* Cache (>= R6000) format */
182 unsigned int opcode : 6;
183 unsigned int rs : 5;
184 unsigned int c_op : 3;
185 unsigned int cache : 2;
186 unsigned int simmediate : 16;
187};
188
189struct r_format { /* Register format */
190 unsigned int opcode : 6;
191 unsigned int rs : 5;
192 unsigned int rt : 5;
193 unsigned int rd : 5;
194 unsigned int re : 5;
195 unsigned int func : 6;
196};
197
198struct p_format { /* Performance counter format (R10000) */
199 unsigned int opcode : 6;
200 unsigned int rs : 5;
201 unsigned int rt : 5;
202 unsigned int rd : 5;
203 unsigned int re : 5;
204 unsigned int func : 6;
205};
206
207struct f_format { /* FPU register format */
208 unsigned int opcode : 6;
209 unsigned int : 1;
210 unsigned int fmt : 4;
211 unsigned int rt : 5;
212 unsigned int rd : 5;
213 unsigned int re : 5;
214 unsigned int func : 6;
215};
216
217struct ma_format { /* FPU multipy and add format (MIPS IV) */
218 unsigned int opcode : 6;
219 unsigned int fr : 5;
220 unsigned int ft : 5;
221 unsigned int fs : 5;
222 unsigned int fd : 5;
223 unsigned int func : 4;
224 unsigned int fmt : 2;
225};
226
227#elif defined(__MIPSEL__)
228
229struct j_format { /* Jump format */
230 unsigned int target : 26;
231 unsigned int opcode : 6;
232};
233
234struct i_format { /* Immediate format */
235 signed int simmediate : 16;
236 unsigned int rt : 5;
237 unsigned int rs : 5;
238 unsigned int opcode : 6;
239};
240
241struct u_format { /* Unsigned immediate format */
242 unsigned int uimmediate : 16;
243 unsigned int rt : 5;
244 unsigned int rs : 5;
245 unsigned int opcode : 6;
246};
247
248struct c_format { /* Cache (>= R6000) format */
249 unsigned int simmediate : 16;
250 unsigned int cache : 2;
251 unsigned int c_op : 3;
252 unsigned int rs : 5;
253 unsigned int opcode : 6;
254};
255
256struct r_format { /* Register format */
257 unsigned int func : 6;
258 unsigned int re : 5;
259 unsigned int rd : 5;
260 unsigned int rt : 5;
261 unsigned int rs : 5;
262 unsigned int opcode : 6;
263};
264
265struct p_format { /* Performance counter format (R10000) */
266 unsigned int func : 6;
267 unsigned int re : 5;
268 unsigned int rd : 5;
269 unsigned int rt : 5;
270 unsigned int rs : 5;
271 unsigned int opcode : 6;
272};
273
274struct f_format { /* FPU register format */
275 unsigned int func : 6;
276 unsigned int re : 5;
277 unsigned int rd : 5;
278 unsigned int rt : 5;
279 unsigned int fmt : 4;
280 unsigned int : 1;
281 unsigned int opcode : 6;
282};
283
284struct ma_format { /* FPU multipy and add format (MIPS IV) */
285 unsigned int fmt : 2;
286 unsigned int func : 4;
287 unsigned int fd : 5;
288 unsigned int fs : 5;
289 unsigned int ft : 5;
290 unsigned int fr : 5;
291 unsigned int opcode : 6;
292};
293
294#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
295#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
296#endif
297
298union mips_instruction {
299 unsigned int word;
300 unsigned short halfword[2];
301 unsigned char byte[4];
302 struct j_format j_format;
303 struct i_format i_format;
304 struct u_format u_format;
305 struct c_format c_format;
306 struct r_format r_format;
307 struct f_format f_format;
308 struct ma_format ma_format;
309};
310
311/* HACHACHAHCAHC ... */
312
313/* In case some other massaging is needed, keep MIPSInst as wrapper */
314
315#define MIPSInst(x) x
316
317#define I_OPCODE_SFT 26
318#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
319
320#define I_JTARGET_SFT 0
321#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
322
323#define I_RS_SFT 21
324#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
325
326#define I_RT_SFT 16
327#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
328
329#define I_IMM_SFT 0
330#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
331#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
332
333#define I_CACHEOP_SFT 18
334#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
335
336#define I_CACHESEL_SFT 16
337#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
338
339#define I_RD_SFT 11
340#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
341
342#define I_RE_SFT 6
343#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
344
345#define I_FUNC_SFT 0
346#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
347
348#define I_FFMT_SFT 21
349#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
350
351#define I_FT_SFT 16
352#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
353
354#define I_FS_SFT 11
355#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
356
357#define I_FD_SFT 6
358#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
359
360#define I_FR_SFT 21
361#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
362
363#define I_FMA_FUNC_SFT 2
364#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
365
366#define I_FMA_FFMT_SFT 0
367#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
368
369typedef unsigned int mips_instruction;
370
371#endif /* _ASM_INST_H */