Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1 | /* bnx2x_init.h: Broadcom Everest network driver. |
| 2 | * |
Eliezer Tamir | e8717a4 | 2008-02-28 11:57:29 -0800 | [diff] [blame] | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
Eilon Greenstein | 24e3fce | 2008-06-12 14:30:28 -0700 | [diff] [blame] | 9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
| 10 | * Written by: Eliezer Tamir |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #ifndef BNX2X_INIT_H |
| 14 | #define BNX2X_INIT_H |
| 15 | |
| 16 | #define COMMON 0x1 |
| 17 | #define PORT0 0x2 |
| 18 | #define PORT1 0x4 |
| 19 | |
| 20 | #define INIT_EMULATION 0x1 |
| 21 | #define INIT_FPGA 0x2 |
| 22 | #define INIT_ASIC 0x4 |
| 23 | #define INIT_HARDWARE 0x7 |
| 24 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 25 | #define STORM_INTMEM_SIZE_E1 (0x5800 / 4) |
| 26 | #define STORM_INTMEM_SIZE_E1H (0x10000 / 4) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 27 | #define TSTORM_INTMEM_ADDR 0x1a0000 |
| 28 | #define CSTORM_INTMEM_ADDR 0x220000 |
| 29 | #define XSTORM_INTMEM_ADDR 0x2a0000 |
| 30 | #define USTORM_INTMEM_ADDR 0x320000 |
| 31 | |
| 32 | |
| 33 | /* Init operation types and structures */ |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 34 | /* Common for both E1 and E1H */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 35 | #define OP_RD 0x1 /* read single register */ |
| 36 | #define OP_WR 0x2 /* write single register */ |
| 37 | #define OP_IW 0x3 /* write single register using mailbox */ |
| 38 | #define OP_SW 0x4 /* copy a string to the device */ |
| 39 | #define OP_SI 0x5 /* copy a string using mailbox */ |
| 40 | #define OP_ZR 0x6 /* clear memory */ |
| 41 | #define OP_ZP 0x7 /* unzip then copy with DMAE */ |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 42 | #define OP_WR_64 0x8 /* write 64 bit pattern */ |
| 43 | #define OP_WB 0x9 /* copy a string using DMAE */ |
| 44 | |
| 45 | /* Operation specific for E1 */ |
| 46 | #define OP_RD_E1 0xa /* read single register */ |
| 47 | #define OP_WR_E1 0xb /* write single register */ |
| 48 | #define OP_IW_E1 0xc /* write single register using mailbox */ |
| 49 | #define OP_SW_E1 0xd /* copy a string to the device */ |
| 50 | #define OP_SI_E1 0xe /* copy a string using mailbox */ |
| 51 | #define OP_ZR_E1 0xf /* clear memory */ |
| 52 | #define OP_ZP_E1 0x10 /* unzip then copy with DMAE */ |
| 53 | #define OP_WR_64_E1 0x11 /* write 64 bit pattern on E1 */ |
| 54 | #define OP_WB_E1 0x12 /* copy a string using DMAE */ |
| 55 | |
| 56 | /* Operation specific for E1H */ |
| 57 | #define OP_RD_E1H 0x13 /* read single register */ |
| 58 | #define OP_WR_E1H 0x14 /* write single register */ |
| 59 | #define OP_IW_E1H 0x15 /* write single register using mailbox */ |
| 60 | #define OP_SW_E1H 0x16 /* copy a string to the device */ |
| 61 | #define OP_SI_E1H 0x17 /* copy a string using mailbox */ |
| 62 | #define OP_ZR_E1H 0x18 /* clear memory */ |
| 63 | #define OP_ZP_E1H 0x19 /* unzip then copy with DMAE */ |
| 64 | #define OP_WR_64_E1H 0x1a /* write 64 bit pattern on E1H */ |
| 65 | #define OP_WB_E1H 0x1b /* copy a string using DMAE */ |
| 66 | |
| 67 | /* FPGA and EMUL specific operations */ |
| 68 | #define OP_WR_EMUL_E1H 0x1c /* write single register on E1H Emul */ |
| 69 | #define OP_WR_EMUL 0x1d /* write single register on Emulation */ |
| 70 | #define OP_WR_FPGA 0x1e /* write single register on FPGA */ |
| 71 | #define OP_WR_ASIC 0x1f /* write single register on ASIC */ |
| 72 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 73 | |
| 74 | struct raw_op { |
Eilon Greenstein | 6378c02 | 2008-08-13 15:59:25 -0700 | [diff] [blame] | 75 | u32 op:8; |
| 76 | u32 offset:24; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 77 | u32 raw_data; |
| 78 | }; |
| 79 | |
| 80 | struct op_read { |
Eilon Greenstein | 6378c02 | 2008-08-13 15:59:25 -0700 | [diff] [blame] | 81 | u32 op:8; |
| 82 | u32 offset:24; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 83 | u32 pad; |
| 84 | }; |
| 85 | |
| 86 | struct op_write { |
Eilon Greenstein | 6378c02 | 2008-08-13 15:59:25 -0700 | [diff] [blame] | 87 | u32 op:8; |
| 88 | u32 offset:24; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 89 | u32 val; |
| 90 | }; |
| 91 | |
| 92 | struct op_string_write { |
Eilon Greenstein | 6378c02 | 2008-08-13 15:59:25 -0700 | [diff] [blame] | 93 | u32 op:8; |
| 94 | u32 offset:24; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 95 | #ifdef __LITTLE_ENDIAN |
| 96 | u16 data_off; |
| 97 | u16 data_len; |
| 98 | #else /* __BIG_ENDIAN */ |
| 99 | u16 data_len; |
| 100 | u16 data_off; |
| 101 | #endif |
| 102 | }; |
| 103 | |
| 104 | struct op_zero { |
Eilon Greenstein | 6378c02 | 2008-08-13 15:59:25 -0700 | [diff] [blame] | 105 | u32 op:8; |
| 106 | u32 offset:24; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 107 | u32 len; |
| 108 | }; |
| 109 | |
| 110 | union init_op { |
| 111 | struct op_read read; |
| 112 | struct op_write write; |
| 113 | struct op_string_write str_wr; |
| 114 | struct op_zero zero; |
| 115 | struct raw_op raw; |
| 116 | }; |
| 117 | |
| 118 | #include "bnx2x_init_values.h" |
| 119 | |
| 120 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 121 | static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len); |
| 122 | |
| 123 | static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data, |
| 124 | u32 len) |
| 125 | { |
| 126 | int i; |
| 127 | |
| 128 | for (i = 0; i < len; i++) { |
| 129 | REG_WR(bp, addr + i*4, data[i]); |
| 130 | if (!(i % 10000)) { |
| 131 | touch_softlockup_watchdog(); |
| 132 | cpu_relax(); |
| 133 | } |
| 134 | } |
| 135 | } |
| 136 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 137 | static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data, |
| 138 | u16 len) |
| 139 | { |
| 140 | int i; |
| 141 | |
| 142 | for (i = 0; i < len; i++) { |
| 143 | REG_WR_IND(bp, addr + i*4, data[i]); |
| 144 | if (!(i % 10000)) { |
| 145 | touch_softlockup_watchdog(); |
| 146 | cpu_relax(); |
| 147 | } |
| 148 | } |
| 149 | } |
| 150 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 151 | static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) |
| 152 | { |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 153 | int offset = 0; |
| 154 | |
| 155 | if (bp->dmae_ready) { |
| 156 | while (len > DMAE_LEN32_WR_MAX) { |
| 157 | bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, |
| 158 | addr + offset, DMAE_LEN32_WR_MAX); |
| 159 | offset += DMAE_LEN32_WR_MAX * 4; |
| 160 | len -= DMAE_LEN32_WR_MAX; |
| 161 | } |
| 162 | bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, |
| 163 | addr + offset, len); |
| 164 | } else |
| 165 | bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
| 169 | { |
| 170 | if ((len * 4) > FW_BUF_SIZE) { |
| 171 | BNX2X_ERR("LARGE DMAE OPERATION ! addr 0x%x len 0x%x\n", |
| 172 | addr, len*4); |
| 173 | return; |
| 174 | } |
| 175 | memset(bp->gunzip_buf, fill, len * 4); |
| 176 | |
| 177 | bnx2x_write_big_buf(bp, addr, len); |
| 178 | } |
| 179 | |
| 180 | static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data, |
| 181 | u32 len64) |
| 182 | { |
| 183 | u32 buf_len32 = FW_BUF_SIZE/4; |
| 184 | u32 len = len64*2; |
| 185 | u64 data64 = 0; |
| 186 | int i; |
| 187 | |
| 188 | /* 64 bit value is in a blob: first low DWORD, then high DWORD */ |
| 189 | data64 = HILO_U64((*(data + 1)), (*data)); |
| 190 | len64 = min((u32)(FW_BUF_SIZE/8), len64); |
| 191 | for (i = 0; i < len64; i++) { |
| 192 | u64 *pdata = ((u64 *)(bp->gunzip_buf)) + i; |
| 193 | |
| 194 | *pdata = data64; |
| 195 | } |
| 196 | |
| 197 | for (i = 0; i < len; i += buf_len32) { |
| 198 | u32 cur_len = min(buf_len32, len - i); |
| 199 | |
| 200 | bnx2x_write_big_buf(bp, addr + i * 4, cur_len); |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | /********************************************************* |
| 205 | There are different blobs for each PRAM section. |
| 206 | In addition, each blob write operation is divided into a few operations |
Eilon Greenstein | 3347162 | 2008-08-13 15:59:08 -0700 | [diff] [blame] | 207 | in order to decrease the amount of phys. contiguous buffer needed. |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 208 | Thus, when we select a blob the address may be with some offset |
| 209 | from the beginning of PRAM section. |
| 210 | The same holds for the INT_TABLE sections. |
| 211 | **********************************************************/ |
| 212 | #define IF_IS_INT_TABLE_ADDR(base, addr) \ |
| 213 | if (((base) <= (addr)) && ((base) + 0x400 >= (addr))) |
| 214 | |
| 215 | #define IF_IS_PRAM_ADDR(base, addr) \ |
| 216 | if (((base) <= (addr)) && ((base) + 0x40000 >= (addr))) |
| 217 | |
| 218 | static const u32 *bnx2x_sel_blob(u32 addr, const u32 *data, int is_e1) |
| 219 | { |
| 220 | IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr) |
| 221 | data = is_e1 ? tsem_int_table_data_e1 : |
| 222 | tsem_int_table_data_e1h; |
| 223 | else |
| 224 | IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 225 | data = is_e1 ? csem_int_table_data_e1 : |
| 226 | csem_int_table_data_e1h; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 227 | else |
| 228 | IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 229 | data = is_e1 ? usem_int_table_data_e1 : |
| 230 | usem_int_table_data_e1h; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 231 | else |
| 232 | IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 233 | data = is_e1 ? xsem_int_table_data_e1 : |
| 234 | xsem_int_table_data_e1h; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 235 | else |
| 236 | IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 237 | data = is_e1 ? tsem_pram_data_e1 : tsem_pram_data_e1h; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 238 | else |
| 239 | IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 240 | data = is_e1 ? csem_pram_data_e1 : csem_pram_data_e1h; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 241 | else |
| 242 | IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 243 | data = is_e1 ? usem_pram_data_e1 : usem_pram_data_e1h; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 244 | else |
| 245 | IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr) |
Eilon Greenstein | 34f80b0 | 2008-06-23 20:33:01 -0700 | [diff] [blame] | 246 | data = is_e1 ? xsem_pram_data_e1 : xsem_pram_data_e1h; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 247 | |
| 248 | return data; |
| 249 | } |
| 250 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 251 | static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data, |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 252 | u32 len, int gunzip, int is_e1, u32 blob_off) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 253 | { |
| 254 | int offset = 0; |
| 255 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 256 | data = bnx2x_sel_blob(addr, data, is_e1) + blob_off; |
| 257 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 258 | if (gunzip) { |
| 259 | int rc; |
| 260 | #ifdef __BIG_ENDIAN |
| 261 | int i, size; |
| 262 | u32 *temp; |
| 263 | |
| 264 | temp = kmalloc(len, GFP_KERNEL); |
| 265 | size = (len / 4) + ((len % 4) ? 1 : 0); |
| 266 | for (i = 0; i < size; i++) |
| 267 | temp[i] = swab32(data[i]); |
| 268 | data = temp; |
| 269 | #endif |
| 270 | rc = bnx2x_gunzip(bp, (u8 *)data, len); |
| 271 | if (rc) { |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 272 | BNX2X_ERR("gunzip failed ! rc %d\n", rc); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 273 | return; |
| 274 | } |
| 275 | len = bp->gunzip_outlen; |
| 276 | #ifdef __BIG_ENDIAN |
| 277 | kfree(temp); |
| 278 | for (i = 0; i < len; i++) |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 279 | ((u32 *)bp->gunzip_buf)[i] = |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 280 | swab32(((u32 *)bp->gunzip_buf)[i]); |
| 281 | #endif |
| 282 | } else { |
| 283 | if ((len * 4) > FW_BUF_SIZE) { |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 284 | BNX2X_ERR("LARGE DMAE OPERATION ! " |
| 285 | "addr 0x%x len 0x%x\n", addr, len*4); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 286 | return; |
| 287 | } |
| 288 | memcpy(bp->gunzip_buf, data, len * 4); |
| 289 | } |
| 290 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 291 | if (bp->dmae_ready) { |
| 292 | while (len > DMAE_LEN32_WR_MAX) { |
| 293 | bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, |
| 294 | addr + offset, DMAE_LEN32_WR_MAX); |
| 295 | offset += DMAE_LEN32_WR_MAX * 4; |
| 296 | len -= DMAE_LEN32_WR_MAX; |
| 297 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 298 | bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 299 | addr + offset, len); |
| 300 | } else |
| 301 | bnx2x_init_ind_wr(bp, addr, bp->gunzip_buf, len); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end) |
| 305 | { |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 306 | int is_e1 = CHIP_IS_E1(bp); |
| 307 | int is_e1h = CHIP_IS_E1H(bp); |
| 308 | int is_emul_e1h = (CHIP_REV_IS_EMUL(bp) && is_e1h); |
| 309 | int hw_wr, i; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 310 | union init_op *op; |
| 311 | u32 op_type, addr, len; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 312 | const u32 *data, *data_base; |
| 313 | |
| 314 | if (CHIP_REV_IS_FPGA(bp)) |
| 315 | hw_wr = OP_WR_FPGA; |
| 316 | else if (CHIP_REV_IS_EMUL(bp)) |
| 317 | hw_wr = OP_WR_EMUL; |
| 318 | else |
| 319 | hw_wr = OP_WR_ASIC; |
| 320 | |
| 321 | if (is_e1) |
| 322 | data_base = init_data_e1; |
| 323 | else /* CHIP_IS_E1H(bp) */ |
| 324 | data_base = init_data_e1h; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 325 | |
| 326 | for (i = op_start; i < op_end; i++) { |
| 327 | |
| 328 | op = (union init_op *)&(init_ops[i]); |
| 329 | |
| 330 | op_type = op->str_wr.op; |
| 331 | addr = op->str_wr.offset; |
| 332 | len = op->str_wr.data_len; |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 333 | data = data_base + op->str_wr.data_off; |
| 334 | |
Eilon Greenstein | 3347162 | 2008-08-13 15:59:08 -0700 | [diff] [blame] | 335 | /* careful! it must be in order */ |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 336 | if (unlikely(op_type > OP_WB)) { |
| 337 | |
| 338 | /* If E1 only */ |
| 339 | if (op_type <= OP_WB_E1) { |
| 340 | if (is_e1) |
| 341 | op_type -= (OP_RD_E1 - OP_RD); |
| 342 | |
| 343 | /* If E1H only */ |
| 344 | } else if (op_type <= OP_WB_E1H) { |
| 345 | if (is_e1h) |
| 346 | op_type -= (OP_RD_E1H - OP_RD); |
| 347 | } |
| 348 | |
| 349 | /* HW/EMUL specific */ |
| 350 | if (op_type == hw_wr) |
| 351 | op_type = OP_WR; |
| 352 | |
| 353 | /* EMUL on E1H is special */ |
| 354 | if ((op_type == OP_WR_EMUL_E1H) && is_emul_e1h) |
| 355 | op_type = OP_WR; |
| 356 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 357 | |
| 358 | switch (op_type) { |
| 359 | case OP_RD: |
| 360 | REG_RD(bp, addr); |
| 361 | break; |
| 362 | case OP_WR: |
| 363 | REG_WR(bp, addr, op->write.val); |
| 364 | break; |
| 365 | case OP_SW: |
| 366 | bnx2x_init_str_wr(bp, addr, data, len); |
| 367 | break; |
| 368 | case OP_WB: |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 369 | bnx2x_init_wr_wb(bp, addr, data, len, 0, is_e1, 0); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 370 | break; |
| 371 | case OP_SI: |
| 372 | bnx2x_init_ind_wr(bp, addr, data, len); |
| 373 | break; |
| 374 | case OP_ZR: |
| 375 | bnx2x_init_fill(bp, addr, 0, op->zero.len); |
| 376 | break; |
| 377 | case OP_ZP: |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 378 | bnx2x_init_wr_wb(bp, addr, data, len, 1, is_e1, |
| 379 | op->str_wr.data_off); |
| 380 | break; |
| 381 | case OP_WR_64: |
| 382 | bnx2x_init_wr_64(bp, addr, data, len); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 383 | break; |
| 384 | default: |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 385 | /* happens whenever an op is of a diff HW */ |
| 386 | #if 0 |
| 387 | DP(NETIF_MSG_HW, "skipping init operation " |
| 388 | "index %d[%d:%d]: type %d addr 0x%x " |
| 389 | "len %d(0x%x)\n", |
| 390 | i, op_start, op_end, op_type, addr, len, len); |
| 391 | #endif |
| 392 | break; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 393 | } |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | |
| 398 | /**************************************************************************** |
| 399 | * PXP |
| 400 | ****************************************************************************/ |
| 401 | /* |
| 402 | * This code configures the PCI read/write arbiter |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 403 | * which implements a weighted round robin |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 404 | * between the virtual queues in the chip. |
| 405 | * |
| 406 | * The values were derived for each PCI max payload and max request size. |
| 407 | * since max payload and max request size are only known at run time, |
| 408 | * this is done as a separate init stage. |
| 409 | */ |
| 410 | |
| 411 | #define NUM_WR_Q 13 |
| 412 | #define NUM_RD_Q 29 |
| 413 | #define MAX_RD_ORD 3 |
| 414 | #define MAX_WR_ORD 2 |
| 415 | |
| 416 | /* configuration for one arbiter queue */ |
| 417 | struct arb_line { |
| 418 | int l; |
| 419 | int add; |
| 420 | int ubound; |
| 421 | }; |
| 422 | |
| 423 | /* derived configuration for each read queue for each max request size */ |
| 424 | static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = { |
| 425 | {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} }, |
| 426 | {{4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4} }, |
| 427 | {{4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3} }, |
| 428 | {{8 , 3 , 6}, {16 , 3 , 11}, {16 , 3 , 11}, {16 , 3 , 11} }, |
| 429 | {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} }, |
| 430 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, |
| 431 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, |
| 432 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, |
| 433 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, |
| 434 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 435 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 436 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 437 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 438 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 439 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 440 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 441 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 442 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 443 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 444 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 445 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 446 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 447 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 448 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 449 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 450 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 451 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 452 | {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, |
| 453 | {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81}, {64 , 64 , 120} } |
| 454 | }; |
| 455 | |
| 456 | /* derived configuration for each write queue for each max request size */ |
| 457 | static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = { |
| 458 | {{4 , 6 , 3}, {4 , 6 , 3}, {4 , 6 , 3} }, |
| 459 | {{4 , 2 , 3}, {4 , 2 , 3}, {4 , 2 , 3} }, |
| 460 | {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, |
| 461 | {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, |
| 462 | {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, |
| 463 | {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, |
| 464 | {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25} }, |
| 465 | {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, |
| 466 | {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, |
| 467 | {{8 , 9 , 6}, {16 , 9 , 11}, {32 , 9 , 21} }, |
| 468 | {{8 , 47 , 19}, {16 , 47 , 19}, {32 , 47 , 21} }, |
| 469 | {{8 , 9 , 6}, {16 , 9 , 11}, {16 , 9 , 11} }, |
| 470 | {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} } |
| 471 | }; |
| 472 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 473 | /* register addresses for read queues */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 474 | static const struct arb_line read_arb_addr[NUM_RD_Q-1] = { |
| 475 | {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0, |
| 476 | PXP2_REG_RQ_BW_RD_UBOUND0}, |
| 477 | {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, |
| 478 | PXP2_REG_PSWRQ_BW_UB1}, |
| 479 | {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, |
| 480 | PXP2_REG_PSWRQ_BW_UB2}, |
| 481 | {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, |
| 482 | PXP2_REG_PSWRQ_BW_UB3}, |
| 483 | {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4, |
| 484 | PXP2_REG_RQ_BW_RD_UBOUND4}, |
| 485 | {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5, |
| 486 | PXP2_REG_RQ_BW_RD_UBOUND5}, |
| 487 | {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, |
| 488 | PXP2_REG_PSWRQ_BW_UB6}, |
| 489 | {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, |
| 490 | PXP2_REG_PSWRQ_BW_UB7}, |
| 491 | {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, |
| 492 | PXP2_REG_PSWRQ_BW_UB8}, |
| 493 | {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, |
| 494 | PXP2_REG_PSWRQ_BW_UB9}, |
| 495 | {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, |
| 496 | PXP2_REG_PSWRQ_BW_UB10}, |
| 497 | {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, |
| 498 | PXP2_REG_PSWRQ_BW_UB11}, |
| 499 | {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12, |
| 500 | PXP2_REG_RQ_BW_RD_UBOUND12}, |
| 501 | {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13, |
| 502 | PXP2_REG_RQ_BW_RD_UBOUND13}, |
| 503 | {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14, |
| 504 | PXP2_REG_RQ_BW_RD_UBOUND14}, |
| 505 | {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15, |
| 506 | PXP2_REG_RQ_BW_RD_UBOUND15}, |
| 507 | {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16, |
| 508 | PXP2_REG_RQ_BW_RD_UBOUND16}, |
| 509 | {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17, |
| 510 | PXP2_REG_RQ_BW_RD_UBOUND17}, |
| 511 | {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18, |
| 512 | PXP2_REG_RQ_BW_RD_UBOUND18}, |
| 513 | {PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19, |
| 514 | PXP2_REG_RQ_BW_RD_UBOUND19}, |
| 515 | {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20, |
| 516 | PXP2_REG_RQ_BW_RD_UBOUND20}, |
| 517 | {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22, |
| 518 | PXP2_REG_RQ_BW_RD_UBOUND22}, |
| 519 | {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23, |
| 520 | PXP2_REG_RQ_BW_RD_UBOUND23}, |
| 521 | {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24, |
| 522 | PXP2_REG_RQ_BW_RD_UBOUND24}, |
| 523 | {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25, |
| 524 | PXP2_REG_RQ_BW_RD_UBOUND25}, |
| 525 | {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26, |
| 526 | PXP2_REG_RQ_BW_RD_UBOUND26}, |
| 527 | {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27, |
| 528 | PXP2_REG_RQ_BW_RD_UBOUND27}, |
| 529 | {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, |
| 530 | PXP2_REG_PSWRQ_BW_UB28} |
| 531 | }; |
| 532 | |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 533 | /* register addresses for write queues */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 534 | static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { |
| 535 | {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, |
| 536 | PXP2_REG_PSWRQ_BW_UB1}, |
| 537 | {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, |
| 538 | PXP2_REG_PSWRQ_BW_UB2}, |
| 539 | {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, |
| 540 | PXP2_REG_PSWRQ_BW_UB3}, |
| 541 | {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, |
| 542 | PXP2_REG_PSWRQ_BW_UB6}, |
| 543 | {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, |
| 544 | PXP2_REG_PSWRQ_BW_UB7}, |
| 545 | {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, |
| 546 | PXP2_REG_PSWRQ_BW_UB8}, |
| 547 | {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, |
| 548 | PXP2_REG_PSWRQ_BW_UB9}, |
| 549 | {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, |
| 550 | PXP2_REG_PSWRQ_BW_UB10}, |
| 551 | {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, |
| 552 | PXP2_REG_PSWRQ_BW_UB11}, |
| 553 | {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, |
| 554 | PXP2_REG_PSWRQ_BW_UB28}, |
| 555 | {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29, |
| 556 | PXP2_REG_RQ_BW_WR_UBOUND29}, |
| 557 | {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30, |
| 558 | PXP2_REG_RQ_BW_WR_UBOUND30} |
| 559 | }; |
| 560 | |
| 561 | static void bnx2x_init_pxp(struct bnx2x *bp) |
| 562 | { |
Eilon Greenstein | 7d96567 | 2008-11-03 16:46:19 -0800 | [diff] [blame] | 563 | u16 devctl; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 564 | int r_order, w_order; |
| 565 | u32 val, i; |
| 566 | |
| 567 | pci_read_config_word(bp->pdev, |
Eilon Greenstein | 7d96567 | 2008-11-03 16:46:19 -0800 | [diff] [blame] | 568 | bp->pcie_cap + PCI_EXP_DEVCTL, &devctl); |
| 569 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
| 570 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
| 571 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 572 | |
| 573 | if (r_order > MAX_RD_ORD) { |
| 574 | DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n", |
| 575 | r_order, MAX_RD_ORD); |
| 576 | r_order = MAX_RD_ORD; |
| 577 | } |
| 578 | if (w_order > MAX_WR_ORD) { |
| 579 | DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n", |
| 580 | w_order, MAX_WR_ORD); |
| 581 | w_order = MAX_WR_ORD; |
| 582 | } |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 583 | if (CHIP_REV_IS_FPGA(bp)) { |
| 584 | DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n"); |
| 585 | w_order = 0; |
| 586 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 587 | DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order); |
| 588 | |
| 589 | for (i = 0; i < NUM_RD_Q-1; i++) { |
| 590 | REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); |
| 591 | REG_WR(bp, read_arb_addr[i].add, |
| 592 | read_arb_data[i][r_order].add); |
| 593 | REG_WR(bp, read_arb_addr[i].ubound, |
| 594 | read_arb_data[i][r_order].ubound); |
| 595 | } |
| 596 | |
| 597 | for (i = 0; i < NUM_WR_Q-1; i++) { |
| 598 | if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) || |
| 599 | (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) { |
| 600 | |
| 601 | REG_WR(bp, write_arb_addr[i].l, |
| 602 | write_arb_data[i][w_order].l); |
| 603 | |
| 604 | REG_WR(bp, write_arb_addr[i].add, |
| 605 | write_arb_data[i][w_order].add); |
| 606 | |
| 607 | REG_WR(bp, write_arb_addr[i].ubound, |
| 608 | write_arb_data[i][w_order].ubound); |
| 609 | } else { |
| 610 | |
| 611 | val = REG_RD(bp, write_arb_addr[i].l); |
| 612 | REG_WR(bp, write_arb_addr[i].l, |
| 613 | val | (write_arb_data[i][w_order].l << 10)); |
| 614 | |
| 615 | val = REG_RD(bp, write_arb_addr[i].add); |
| 616 | REG_WR(bp, write_arb_addr[i].add, |
| 617 | val | (write_arb_data[i][w_order].add << 10)); |
| 618 | |
| 619 | val = REG_RD(bp, write_arb_addr[i].ubound); |
| 620 | REG_WR(bp, write_arb_addr[i].ubound, |
| 621 | val | (write_arb_data[i][w_order].ubound << 7)); |
| 622 | } |
| 623 | } |
| 624 | |
| 625 | val = write_arb_data[NUM_WR_Q-1][w_order].add; |
| 626 | val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10; |
| 627 | val += write_arb_data[NUM_WR_Q-1][w_order].l << 17; |
| 628 | REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val); |
| 629 | |
| 630 | val = read_arb_data[NUM_RD_Q-1][r_order].add; |
| 631 | val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10; |
| 632 | val += read_arb_data[NUM_RD_Q-1][r_order].l << 17; |
| 633 | REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); |
| 634 | |
| 635 | REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); |
Eliezer Tamir | e8717a4 | 2008-02-28 11:57:29 -0800 | [diff] [blame] | 636 | REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 637 | REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); |
Eliezer Tamir | e8717a4 | 2008-02-28 11:57:29 -0800 | [diff] [blame] | 638 | REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order); |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 639 | |
Eliezer Tamir | e8717a4 | 2008-02-28 11:57:29 -0800 | [diff] [blame] | 640 | if (r_order == MAX_RD_ORD) |
| 641 | REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); |
| 642 | |
| 643 | REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 644 | |
| 645 | if (CHIP_IS_E1H(bp)) { |
| 646 | REG_WR(bp, PXP2_REG_WR_HC_MPS, w_order+1); |
| 647 | REG_WR(bp, PXP2_REG_WR_USDM_MPS, w_order+1); |
| 648 | REG_WR(bp, PXP2_REG_WR_CSDM_MPS, w_order+1); |
| 649 | REG_WR(bp, PXP2_REG_WR_TSDM_MPS, w_order+1); |
| 650 | REG_WR(bp, PXP2_REG_WR_XSDM_MPS, w_order+1); |
| 651 | REG_WR(bp, PXP2_REG_WR_QM_MPS, w_order+1); |
| 652 | REG_WR(bp, PXP2_REG_WR_TM_MPS, w_order+1); |
| 653 | REG_WR(bp, PXP2_REG_WR_SRC_MPS, w_order+1); |
| 654 | REG_WR(bp, PXP2_REG_WR_DBG_MPS, w_order+1); |
| 655 | REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */ |
| 656 | REG_WR(bp, PXP2_REG_WR_CDU_MPS, w_order+1); |
| 657 | } |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 658 | } |
| 659 | |
| 660 | |
| 661 | /**************************************************************************** |
| 662 | * CDU |
| 663 | ****************************************************************************/ |
| 664 | |
| 665 | #define CDU_REGION_NUMBER_XCM_AG 2 |
| 666 | #define CDU_REGION_NUMBER_UCM_AG 4 |
| 667 | |
| 668 | /** |
| 669 | * String-to-compress [31:8] = CID (all 24 bits) |
| 670 | * String-to-compress [7:4] = Region |
| 671 | * String-to-compress [3:0] = Type |
| 672 | */ |
| 673 | #define CDU_VALID_DATA(_cid, _region, _type) \ |
| 674 | (((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf))) |
| 675 | #define CDU_CRC8(_cid, _region, _type) \ |
| 676 | calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff) |
| 677 | #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \ |
| 678 | (0x80 | (CDU_CRC8(_cid, _region, _type) & 0x7f)) |
| 679 | #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \ |
| 680 | (0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7)) |
| 681 | #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) |
| 682 | |
| 683 | /***************************************************************************** |
| 684 | * Description: |
| 685 | * Calculates crc 8 on a word value: polynomial 0-1-2-8 |
| 686 | * Code was translated from Verilog. |
| 687 | ****************************************************************************/ |
| 688 | static u8 calc_crc8(u32 data, u8 crc) |
| 689 | { |
| 690 | u8 D[32]; |
| 691 | u8 NewCRC[8]; |
| 692 | u8 C[8]; |
| 693 | u8 crc_res; |
| 694 | u8 i; |
| 695 | |
| 696 | /* split the data into 31 bits */ |
| 697 | for (i = 0; i < 32; i++) { |
| 698 | D[i] = data & 1; |
| 699 | data = data >> 1; |
| 700 | } |
| 701 | |
| 702 | /* split the crc into 8 bits */ |
| 703 | for (i = 0; i < 8; i++) { |
| 704 | C[i] = crc & 1; |
| 705 | crc = crc >> 1; |
| 706 | } |
| 707 | |
| 708 | NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ |
| 709 | D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ |
| 710 | C[6] ^ C[7]; |
| 711 | NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ |
| 712 | D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ |
| 713 | D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6]; |
| 714 | NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ |
| 715 | D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ |
| 716 | C[0] ^ C[1] ^ C[4] ^ C[5]; |
| 717 | NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ |
| 718 | D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ |
| 719 | C[1] ^ C[2] ^ C[5] ^ C[6]; |
| 720 | NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ |
| 721 | D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ |
| 722 | C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; |
| 723 | NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ |
| 724 | D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ |
| 725 | C[3] ^ C[4] ^ C[7]; |
| 726 | NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ |
| 727 | D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ |
| 728 | C[5]; |
| 729 | NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ |
| 730 | D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ |
| 731 | C[6]; |
| 732 | |
| 733 | crc_res = 0; |
| 734 | for (i = 0; i < 8; i++) |
| 735 | crc_res |= (NewCRC[i] << i); |
| 736 | |
| 737 | return crc_res; |
| 738 | } |
| 739 | |
Eilon Greenstein | 3347162 | 2008-08-13 15:59:08 -0700 | [diff] [blame] | 740 | /* registers addresses are not in order |
Eilon Greenstein | ad8d394 | 2008-06-23 20:29:02 -0700 | [diff] [blame] | 741 | so these arrays help simplify the code */ |
| 742 | static const int cm_start[E1H_FUNC_MAX][9] = { |
| 743 | {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START, |
| 744 | XCM_FUNC0_START, TSEM_FUNC0_START, USEM_FUNC0_START, CSEM_FUNC0_START, |
| 745 | XSEM_FUNC0_START}, |
| 746 | {MISC_FUNC1_START, TCM_FUNC1_START, UCM_FUNC1_START, CCM_FUNC1_START, |
| 747 | XCM_FUNC1_START, TSEM_FUNC1_START, USEM_FUNC1_START, CSEM_FUNC1_START, |
| 748 | XSEM_FUNC1_START}, |
| 749 | {MISC_FUNC2_START, TCM_FUNC2_START, UCM_FUNC2_START, CCM_FUNC2_START, |
| 750 | XCM_FUNC2_START, TSEM_FUNC2_START, USEM_FUNC2_START, CSEM_FUNC2_START, |
| 751 | XSEM_FUNC2_START}, |
| 752 | {MISC_FUNC3_START, TCM_FUNC3_START, UCM_FUNC3_START, CCM_FUNC3_START, |
| 753 | XCM_FUNC3_START, TSEM_FUNC3_START, USEM_FUNC3_START, CSEM_FUNC3_START, |
| 754 | XSEM_FUNC3_START}, |
| 755 | {MISC_FUNC4_START, TCM_FUNC4_START, UCM_FUNC4_START, CCM_FUNC4_START, |
| 756 | XCM_FUNC4_START, TSEM_FUNC4_START, USEM_FUNC4_START, CSEM_FUNC4_START, |
| 757 | XSEM_FUNC4_START}, |
| 758 | {MISC_FUNC5_START, TCM_FUNC5_START, UCM_FUNC5_START, CCM_FUNC5_START, |
| 759 | XCM_FUNC5_START, TSEM_FUNC5_START, USEM_FUNC5_START, CSEM_FUNC5_START, |
| 760 | XSEM_FUNC5_START}, |
| 761 | {MISC_FUNC6_START, TCM_FUNC6_START, UCM_FUNC6_START, CCM_FUNC6_START, |
| 762 | XCM_FUNC6_START, TSEM_FUNC6_START, USEM_FUNC6_START, CSEM_FUNC6_START, |
| 763 | XSEM_FUNC6_START}, |
| 764 | {MISC_FUNC7_START, TCM_FUNC7_START, UCM_FUNC7_START, CCM_FUNC7_START, |
| 765 | XCM_FUNC7_START, TSEM_FUNC7_START, USEM_FUNC7_START, CSEM_FUNC7_START, |
| 766 | XSEM_FUNC7_START} |
| 767 | }; |
| 768 | |
| 769 | static const int cm_end[E1H_FUNC_MAX][9] = { |
| 770 | {MISC_FUNC0_END, TCM_FUNC0_END, UCM_FUNC0_END, CCM_FUNC0_END, |
| 771 | XCM_FUNC0_END, TSEM_FUNC0_END, USEM_FUNC0_END, CSEM_FUNC0_END, |
| 772 | XSEM_FUNC0_END}, |
| 773 | {MISC_FUNC1_END, TCM_FUNC1_END, UCM_FUNC1_END, CCM_FUNC1_END, |
| 774 | XCM_FUNC1_END, TSEM_FUNC1_END, USEM_FUNC1_END, CSEM_FUNC1_END, |
| 775 | XSEM_FUNC1_END}, |
| 776 | {MISC_FUNC2_END, TCM_FUNC2_END, UCM_FUNC2_END, CCM_FUNC2_END, |
| 777 | XCM_FUNC2_END, TSEM_FUNC2_END, USEM_FUNC2_END, CSEM_FUNC2_END, |
| 778 | XSEM_FUNC2_END}, |
| 779 | {MISC_FUNC3_END, TCM_FUNC3_END, UCM_FUNC3_END, CCM_FUNC3_END, |
| 780 | XCM_FUNC3_END, TSEM_FUNC3_END, USEM_FUNC3_END, CSEM_FUNC3_END, |
| 781 | XSEM_FUNC3_END}, |
| 782 | {MISC_FUNC4_END, TCM_FUNC4_END, UCM_FUNC4_END, CCM_FUNC4_END, |
| 783 | XCM_FUNC4_END, TSEM_FUNC4_END, USEM_FUNC4_END, CSEM_FUNC4_END, |
| 784 | XSEM_FUNC4_END}, |
| 785 | {MISC_FUNC5_END, TCM_FUNC5_END, UCM_FUNC5_END, CCM_FUNC5_END, |
| 786 | XCM_FUNC5_END, TSEM_FUNC5_END, USEM_FUNC5_END, CSEM_FUNC5_END, |
| 787 | XSEM_FUNC5_END}, |
| 788 | {MISC_FUNC6_END, TCM_FUNC6_END, UCM_FUNC6_END, CCM_FUNC6_END, |
| 789 | XCM_FUNC6_END, TSEM_FUNC6_END, USEM_FUNC6_END, CSEM_FUNC6_END, |
| 790 | XSEM_FUNC6_END}, |
| 791 | {MISC_FUNC7_END, TCM_FUNC7_END, UCM_FUNC7_END, CCM_FUNC7_END, |
| 792 | XCM_FUNC7_END, TSEM_FUNC7_END, USEM_FUNC7_END, CSEM_FUNC7_END, |
| 793 | XSEM_FUNC7_END}, |
| 794 | }; |
| 795 | |
| 796 | static const int hc_limits[E1H_FUNC_MAX][2] = { |
| 797 | {HC_FUNC0_START, HC_FUNC0_END}, |
| 798 | {HC_FUNC1_START, HC_FUNC1_END}, |
| 799 | {HC_FUNC2_START, HC_FUNC2_END}, |
| 800 | {HC_FUNC3_START, HC_FUNC3_END}, |
| 801 | {HC_FUNC4_START, HC_FUNC4_END}, |
| 802 | {HC_FUNC5_START, HC_FUNC5_END}, |
| 803 | {HC_FUNC6_START, HC_FUNC6_END}, |
| 804 | {HC_FUNC7_START, HC_FUNC7_END} |
| 805 | }; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 806 | |
| 807 | #endif /* BNX2X_INIT_H */ |
| 808 | |