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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34#ifndef _SMC91X_H_
35#define _SMC91X_H_
36
Magnus Damm3e947942008-02-22 19:55:15 +090037#include <linux/smc91x.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
39/*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
Eric Miao38fd6c32008-06-24 16:14:26 +080043#if defined(CONFIG_ARCH_LUBBOCK) ||\
Eric Miao88c36eb2008-06-24 16:47:37 +080044 defined(CONFIG_MACH_MAINSTONE) ||\
Eric Miaoe1719da2008-06-24 16:49:41 +080045 defined(CONFIG_MACH_ZYLONITE) ||\
Marc Zyngier175ff202008-07-22 16:59:44 +020046 defined(CONFIG_MACH_LITTLETON) ||\
47 defined(CONFIG_ARCH_VIPER)
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
Eric Miao38fd6c32008-06-24 16:14:26 +080049#include <asm/mach-types.h>
50
51/* Now the bus width is specified in the platform data
52 * pretend here to support all I/O access types
53 */
54#define SMC_CAN_USE_8BIT 1
Linus Torvalds1da177e2005-04-16 15:20:36 -070055#define SMC_CAN_USE_16BIT 1
Eric Miao38fd6c32008-06-24 16:14:26 +080056#define SMC_CAN_USE_32BIT 1
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#define SMC_NOWAIT 1
58
Eric Miao3aed74c2008-06-24 15:51:02 +080059#define SMC_IO_SHIFT (lp->io_shift)
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
Eric Miao38fd6c32008-06-24 16:14:26 +080061#define SMC_inb(a, r) readb((a) + (r))
Linus Torvalds1da177e2005-04-16 15:20:36 -070062#define SMC_inw(a, r) readw((a) + (r))
Eric Miao38fd6c32008-06-24 16:14:26 +080063#define SMC_inl(a, r) readl((a) + (r))
64#define SMC_outb(v, a, r) writeb(v, (a) + (r))
65#define SMC_outl(v, a, r) writel(v, (a) + (r))
Linus Torvalds1da177e2005-04-16 15:20:36 -070066#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
67#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
Eric Miao38fd6c32008-06-24 16:14:26 +080068#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
69#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
Russell Kinge7b3dc72008-01-14 22:30:10 +000070#define SMC_IRQ_FLAGS (-1) /* from resource */
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Eric Miao38fd6c32008-06-24 16:14:26 +080072/* We actually can't write halfwords properly if not word aligned */
73static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
74{
75 if (machine_is_mainstone() && reg & 2) {
76 unsigned int v = val << 16;
77 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
78 writel(v, ioaddr + (reg & ~2));
79 } else {
80 writew(val, ioaddr + reg);
81 }
82}
83
Mike Frysinger95af9fe2007-11-23 17:55:50 +080084#elif defined(CONFIG_BLACKFIN)
Wu, Bryan0851a282007-05-06 14:50:32 -070085
86#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
Jean-Christian de Rivazc5760abd2007-06-11 17:44:14 +080087#define RPC_LSA_DEFAULT RPC_LED_100_10
88#define RPC_LSB_DEFAULT RPC_LED_TX_RX
Wu, Bryan0851a282007-05-06 14:50:32 -070089
Wu, Bryan0851a282007-05-06 14:50:32 -070090#define SMC_CAN_USE_8BIT 0
91#define SMC_CAN_USE_16BIT 1
Mike Frysingera61fc1e2008-11-17 21:23:40 +000092# if defined(CONFIG_BF561)
Wu, Bryan0851a282007-05-06 14:50:32 -070093#define SMC_CAN_USE_32BIT 1
Wu, Bryan0851a282007-05-06 14:50:32 -070094# else
Wu, Bryan0851a282007-05-06 14:50:32 -070095#define SMC_CAN_USE_32BIT 0
Mike Frysingera61fc1e2008-11-17 21:23:40 +000096# endif
Wu, Bryan0851a282007-05-06 14:50:32 -070097#define SMC_IO_SHIFT 0
98#define SMC_NOWAIT 1
99#define SMC_USE_BFIN_DMA 0
100
Mike Frysingera61fc1e2008-11-17 21:23:40 +0000101#define SMC_inw(a, r) readw((a) + (r))
102#define SMC_outw(v, a, r) writew(v, (a) + (r))
103#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
104#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
105# if SMC_CAN_USE_32BIT
106#define SMC_inl(a, r) readl((a) + (r))
107#define SMC_outl(v, a, r) writel(v, (a) + (r))
108#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
109#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
Wu, Bryan0851a282007-05-06 14:50:32 -0700110# endif
Mike Frysingera61fc1e2008-11-17 21:23:40 +0000111
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
113
114/* We can only do 16-bit reads and writes in the static memory space. */
115#define SMC_CAN_USE_8BIT 0
116#define SMC_CAN_USE_16BIT 1
117#define SMC_CAN_USE_32BIT 0
118#define SMC_NOWAIT 1
119
120#define SMC_IO_SHIFT 0
121
122#define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
123#define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
124#define SMC_insw(a, r, p, l) \
125 do { \
126 unsigned long __port = (a) + (r); \
127 u16 *__p = (u16 *)(p); \
128 int __l = (l); \
129 insw(__port, __p, __l); \
130 while (__l > 0) { \
131 *__p = swab16(*__p); \
132 __p++; \
133 __l--; \
134 } \
135 } while (0)
136#define SMC_outsw(a, r, p, l) \
137 do { \
138 unsigned long __port = (a) + (r); \
139 u16 *__p = (u16 *)(p); \
140 int __l = (l); \
141 while (__l > 0) { \
142 /* Believe it or not, the swab isn't needed. */ \
143 outw( /* swab16 */ (*__p++), __port); \
144 __l--; \
145 } \
146 } while (0)
Russell King9ded96f2006-01-08 01:02:07 -0800147#define SMC_IRQ_FLAGS (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148
149#elif defined(CONFIG_SA1100_PLEB)
150/* We can only do 16-bit reads and writes in the static memory space. */
151#define SMC_CAN_USE_8BIT 1
152#define SMC_CAN_USE_16BIT 1
153#define SMC_CAN_USE_32BIT 0
154#define SMC_IO_SHIFT 0
155#define SMC_NOWAIT 1
156
Russell King1cf99be2005-11-12 21:49:36 +0000157#define SMC_inb(a, r) readb((a) + (r))
158#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
159#define SMC_inw(a, r) readw((a) + (r))
160#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
161#define SMC_outb(v, a, r) writeb(v, (a) + (r))
162#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
163#define SMC_outw(v, a, r) writew(v, (a) + (r))
164#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165
Russell Kinge7b3dc72008-01-14 22:30:10 +0000166#define SMC_IRQ_FLAGS (-1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167
168#elif defined(CONFIG_SA1100_ASSABET)
169
Russell Kinga09e64f2008-08-05 16:14:15 +0100170#include <mach/neponset.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171
172/* We can only do 8-bit reads and writes in the static memory space. */
173#define SMC_CAN_USE_8BIT 1
174#define SMC_CAN_USE_16BIT 0
175#define SMC_CAN_USE_32BIT 0
176#define SMC_NOWAIT 1
177
178/* The first two address lines aren't connected... */
179#define SMC_IO_SHIFT 2
180
181#define SMC_inb(a, r) readb((a) + (r))
182#define SMC_outb(v, a, r) writeb(v, (a) + (r))
183#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
184#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
Russell Kinge7b3dc72008-01-14 22:30:10 +0000185#define SMC_IRQ_FLAGS (-1) /* from resource */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186
Lennert Buytenhekb0348b92006-03-28 17:19:50 +0200187#elif defined(CONFIG_MACH_LOGICPD_PXA270)
188
189#define SMC_CAN_USE_8BIT 0
190#define SMC_CAN_USE_16BIT 1
191#define SMC_CAN_USE_32BIT 0
192#define SMC_IO_SHIFT 0
193#define SMC_NOWAIT 1
Lennert Buytenhekb0348b92006-03-28 17:19:50 +0200194
Lennert Buytenhekb0348b92006-03-28 17:19:50 +0200195#define SMC_inw(a, r) readw((a) + (r))
Lennert Buytenhekb0348b92006-03-28 17:19:50 +0200196#define SMC_outw(v, a, r) writew(v, (a) + (r))
Lennert Buytenhekb0348b92006-03-28 17:19:50 +0200197#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
198#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
199
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200#elif defined(CONFIG_ARCH_INNOKOM) || \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 defined(CONFIG_ARCH_PXA_IDP) || \
Robert Schwebel4f15a982008-01-08 08:50:02 +0100202 defined(CONFIG_ARCH_RAMSES) || \
203 defined(CONFIG_ARCH_PCM027)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204
205#define SMC_CAN_USE_8BIT 1
206#define SMC_CAN_USE_16BIT 1
207#define SMC_CAN_USE_32BIT 1
208#define SMC_IO_SHIFT 0
209#define SMC_NOWAIT 1
210#define SMC_USE_PXA_DMA 1
211
212#define SMC_inb(a, r) readb((a) + (r))
213#define SMC_inw(a, r) readw((a) + (r))
214#define SMC_inl(a, r) readl((a) + (r))
215#define SMC_outb(v, a, r) writeb(v, (a) + (r))
216#define SMC_outl(v, a, r) writel(v, (a) + (r))
217#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
218#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
Russell Kinge7b3dc72008-01-14 22:30:10 +0000219#define SMC_IRQ_FLAGS (-1) /* from resource */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220
221/* We actually can't write halfwords properly if not word aligned */
222static inline void
Nicolas Pitreeb1d6982005-05-12 20:19:09 -0400223SMC_outw(u16 val, void __iomem *ioaddr, int reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224{
225 if (reg & 2) {
226 unsigned int v = val << 16;
227 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
228 writel(v, ioaddr + (reg & ~2));
229 } else {
230 writew(val, ioaddr + reg);
231 }
232}
233
234#elif defined(CONFIG_ARCH_OMAP)
235
236/* We can only do 16-bit reads and writes in the static memory space. */
237#define SMC_CAN_USE_8BIT 0
238#define SMC_CAN_USE_16BIT 1
239#define SMC_CAN_USE_32BIT 0
240#define SMC_IO_SHIFT 0
241#define SMC_NOWAIT 1
242
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243#define SMC_inw(a, r) readw((a) + (r))
244#define SMC_outw(v, a, r) writew(v, (a) + (r))
245#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
246#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
Russell Kinge7b3dc72008-01-14 22:30:10 +0000247#define SMC_IRQ_FLAGS (-1) /* from resource */
David Brownell5f13e7e2005-05-16 08:53:52 -0700248
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249#elif defined(CONFIG_SH_SH4202_MICRODEV)
250
251#define SMC_CAN_USE_8BIT 0
252#define SMC_CAN_USE_16BIT 1
253#define SMC_CAN_USE_32BIT 0
254
255#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
256#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
257#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
258#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
259#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
260#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
261#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
262#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
263#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
264#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
265
Russell King9ded96f2006-01-08 01:02:07 -0800266#define SMC_IRQ_FLAGS (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268#elif defined(CONFIG_M32R)
269
270#define SMC_CAN_USE_8BIT 0
271#define SMC_CAN_USE_16BIT 1
272#define SMC_CAN_USE_32BIT 0
273
Mariusz Kozlowski59dc76a2006-12-04 15:04:56 -0800274#define SMC_inb(a, r) inb(((u32)a) + (r))
Hirokazu Takataf3ac9fb2005-10-30 15:00:06 -0800275#define SMC_inw(a, r) inw(((u32)a) + (r))
276#define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
277#define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
278#define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
279#define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280
Russell King9ded96f2006-01-08 01:02:07 -0800281#define SMC_IRQ_FLAGS (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282
283#define RPC_LSA_DEFAULT RPC_LED_TX_RX
284#define RPC_LSB_DEFAULT RPC_LED_100_10
285
Marc Singerd4adcff2006-05-16 11:41:40 +0100286#elif defined(CONFIG_MACH_LPD79520) \
287 || defined(CONFIG_MACH_LPD7A400) \
288 || defined(CONFIG_MACH_LPD7A404)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289
Marc Singerd4adcff2006-05-16 11:41:40 +0100290/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
291 * way that the CPU handles chip selects and the way that the SMC chip
292 * expects the chip select to operate. Refer to
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
Marc Singerd4adcff2006-05-16 11:41:40 +0100294 * IOBARRIER is a byte, in order that we read the least-common
295 * denominator. It would be wasteful to read 32 bits from an 8-bit
296 * accessible region.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297 *
298 * There is no explicit protection against interrupts intervening
299 * between the writew and the IOBARRIER. In SMC ISR there is a
300 * preamble that performs an IOBARRIER in the extremely unlikely event
301 * that the driver interrupts itself between a writew to the chip an
302 * the IOBARRIER that follows *and* the cache is large enough that the
303 * first off-chip access while handing the interrupt is to the SMC
304 * chip. Other devices in the same address space as the SMC chip must
305 * be aware of the potential for trouble and perform a similar
306 * IOBARRIER on entry to their ISR.
307 */
308
Russell Kinga09e64f2008-08-05 16:14:15 +0100309#include <mach/constants.h> /* IOBARRIER_VIRT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310
311#define SMC_CAN_USE_8BIT 0
312#define SMC_CAN_USE_16BIT 1
313#define SMC_CAN_USE_32BIT 0
314#define SMC_NOWAIT 0
Marc Singerd4adcff2006-05-16 11:41:40 +0100315#define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316
Marc Singerd4adcff2006-05-16 11:41:40 +0100317#define SMC_inw(a,r)\
318 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
319#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320
Marc Singerd4adcff2006-05-16 11:41:40 +0100321#define SMC_insw LPD7_SMC_insw
322static inline void LPD7_SMC_insw (unsigned char* a, int r,
323 unsigned char* p, int l)
324{
325 unsigned short* ps = (unsigned short*) p;
326 while (l-- > 0) {
327 *ps++ = readw (a + r);
328 LPD7X_IOBARRIER;
329 }
330}
Nicolas Pitre09779c62006-03-20 11:54:27 -0500331
Marc Singerd4adcff2006-05-16 11:41:40 +0100332#define SMC_outsw LPD7_SMC_outsw
333static inline void LPD7_SMC_outsw (unsigned char* a, int r,
334 unsigned char* p, int l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335{
336 unsigned short* ps = (unsigned short*) p;
337 while (l-- > 0) {
338 writew (*ps++, a + r);
Marc Singerd4adcff2006-05-16 11:41:40 +0100339 LPD7X_IOBARRIER;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 }
341}
342
Marc Singerd4adcff2006-05-16 11:41:40 +0100343#define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344
345#define RPC_LSA_DEFAULT RPC_LED_TX_RX
346#define RPC_LSB_DEFAULT RPC_LED_100_10
347
Pete Popov55793452005-11-09 22:46:05 -0500348#elif defined(CONFIG_SOC_AU1X00)
349
350#include <au1xxx.h>
351
352/* We can only do 16-bit reads and writes in the static memory space. */
353#define SMC_CAN_USE_8BIT 0
354#define SMC_CAN_USE_16BIT 1
355#define SMC_CAN_USE_32BIT 0
356#define SMC_IO_SHIFT 0
357#define SMC_NOWAIT 1
358
359#define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
360#define SMC_insw(a, r, p, l) \
361 do { \
362 unsigned long _a = (unsigned long)((a) + (r)); \
363 int _l = (l); \
364 u16 *_p = (u16 *)(p); \
365 while (_l-- > 0) \
366 *_p++ = au_readw(_a); \
367 } while(0)
368#define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
369#define SMC_outsw(a, r, p, l) \
370 do { \
371 unsigned long _a = (unsigned long)((a) + (r)); \
372 int _l = (l); \
373 const u16 *_p = (const u16 *)(p); \
374 while (_l-- > 0) \
375 au_writew(*_p++ , _a); \
376 } while(0)
377
Russell King9ded96f2006-01-08 01:02:07 -0800378#define SMC_IRQ_FLAGS (0)
Pete Popov55793452005-11-09 22:46:05 -0500379
Deepak Saxena8431adf2006-07-11 23:02:48 -0700380#elif defined(CONFIG_ARCH_VERSATILE)
381
382#define SMC_CAN_USE_8BIT 1
383#define SMC_CAN_USE_16BIT 1
384#define SMC_CAN_USE_32BIT 1
385#define SMC_NOWAIT 1
386
387#define SMC_inb(a, r) readb((a) + (r))
388#define SMC_inw(a, r) readw((a) + (r))
389#define SMC_inl(a, r) readl((a) + (r))
390#define SMC_outb(v, a, r) writeb(v, (a) + (r))
391#define SMC_outw(v, a, r) writew(v, (a) + (r))
392#define SMC_outl(v, a, r) writel(v, (a) + (r))
393#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
394#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
Russell Kinge7b3dc72008-01-14 22:30:10 +0000395#define SMC_IRQ_FLAGS (-1) /* from resource */
Deepak Saxena8431adf2006-07-11 23:02:48 -0700396
David Howellsb920de12008-02-08 04:19:31 -0800397#elif defined(CONFIG_MN10300)
398
399/*
400 * MN10300/AM33 configuration
401 */
402
403#include <asm/unit/smc91111.h>
404
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405#else
406
David Howellsb920de12008-02-08 04:19:31 -0800407/*
408 * Default configuration
409 */
410
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411#define SMC_CAN_USE_8BIT 1
412#define SMC_CAN_USE_16BIT 1
413#define SMC_CAN_USE_32BIT 1
414#define SMC_NOWAIT 1
415
Magnus Dammd1c5ea32008-09-08 14:02:34 +0900416#define SMC_IO_SHIFT (lp->io_shift)
417
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418#define SMC_inb(a, r) readb((a) + (r))
419#define SMC_inw(a, r) readw((a) + (r))
420#define SMC_inl(a, r) readl((a) + (r))
421#define SMC_outb(v, a, r) writeb(v, (a) + (r))
422#define SMC_outw(v, a, r) writew(v, (a) + (r))
423#define SMC_outl(v, a, r) writel(v, (a) + (r))
Magnus Damm8a214c12008-02-22 19:55:24 +0900424#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
425#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
427#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
428
429#define RPC_LSA_DEFAULT RPC_LED_100_10
430#define RPC_LSB_DEFAULT RPC_LED_TX_RX
431
432#endif
433
Russell King073ac8f2007-09-01 21:27:18 +0100434
435/* store this information for the driver.. */
436struct smc_local {
437 /*
438 * If I have to wait until memory is available to send a
439 * packet, I will store the skbuff here, until I get the
440 * desired memory. Then, I'll send it out and free it.
441 */
442 struct sk_buff *pending_tx_skb;
443 struct tasklet_struct tx_task;
444
445 /* version/revision of the SMC91x chip */
446 int version;
447
448 /* Contains the current active transmission mode */
449 int tcr_cur_mode;
450
451 /* Contains the current active receive mode */
452 int rcr_cur_mode;
453
454 /* Contains the current active receive/phy mode */
455 int rpc_cur_mode;
456 int ctl_rfduplx;
457 int ctl_rspeed;
458
459 u32 msg_enable;
460 u32 phy_type;
461 struct mii_if_info mii;
462
463 /* work queue */
464 struct work_struct phy_configure;
465 struct net_device *dev;
466 int work_pending;
467
468 spinlock_t lock;
469
Eric Miao52256c02008-06-24 15:36:05 +0800470#ifdef CONFIG_ARCH_PXA
Russell King073ac8f2007-09-01 21:27:18 +0100471 /* DMA needs the physical address of the chip */
472 u_long physaddr;
473 struct device *device;
474#endif
475 void __iomem *base;
476 void __iomem *datacs;
Magnus Damm3e947942008-02-22 19:55:15 +0900477
Eric Miao15919882008-06-24 13:38:50 +0800478 /* the low address lines on some platforms aren't connected... */
479 int io_shift;
480
Magnus Damm3e947942008-02-22 19:55:15 +0900481 struct smc91x_platdata cfg;
Russell King073ac8f2007-09-01 21:27:18 +0100482};
483
Eric Miaofa6d3be2008-06-19 17:19:57 +0800484#define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
485#define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
486#define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
Russell King073ac8f2007-09-01 21:27:18 +0100487
Eric Miao52256c02008-06-24 15:36:05 +0800488#ifdef CONFIG_ARCH_PXA
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489/*
490 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
491 * always happening in irq context so no need to worry about races. TX is
492 * different and probably not worth it for that reason, and not as critical
493 * as RX which can overrun memory and lose packets.
494 */
495#include <linux/dma-mapping.h>
Russell Kingdcea83a2008-11-29 11:40:28 +0000496#include <mach/dma.h>
Russell King05678a92008-11-28 16:04:54 +0000497#include <mach/hardware.h>
Russell Kinga09e64f2008-08-05 16:14:15 +0100498#include <mach/pxa-regs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499
500#ifdef SMC_insl
501#undef SMC_insl
502#define SMC_insl(a, r, p, l) \
Russell King073ac8f2007-09-01 21:27:18 +0100503 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504static inline void
Russell King073ac8f2007-09-01 21:27:18 +0100505smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506 u_char *buf, int len)
507{
Russell King073ac8f2007-09-01 21:27:18 +0100508 u_long physaddr = lp->physaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509 dma_addr_t dmabuf;
510
511 /* fallback if no DMA available */
512 if (dma == (unsigned char)-1) {
513 readsl(ioaddr + reg, buf, len);
514 return;
515 }
516
517 /* 64 bit alignment is required for memory to memory DMA */
518 if ((long)buf & 4) {
519 *((u32 *)buf) = SMC_inl(ioaddr, reg);
520 buf += 4;
521 len--;
522 }
523
524 len *= 4;
Russell King073ac8f2007-09-01 21:27:18 +0100525 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526 DCSR(dma) = DCSR_NODESC;
527 DTADR(dma) = dmabuf;
528 DSADR(dma) = physaddr + reg;
529 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
530 DCMD_WIDTH4 | (DCMD_LENGTH & len));
531 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
532 while (!(DCSR(dma) & DCSR_STOPSTATE))
533 cpu_relax();
534 DCSR(dma) = 0;
Russell King073ac8f2007-09-01 21:27:18 +0100535 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536}
537#endif
538
539#ifdef SMC_insw
540#undef SMC_insw
541#define SMC_insw(a, r, p, l) \
Russell King073ac8f2007-09-01 21:27:18 +0100542 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700543static inline void
Russell King073ac8f2007-09-01 21:27:18 +0100544smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545 u_char *buf, int len)
546{
Russell King073ac8f2007-09-01 21:27:18 +0100547 u_long physaddr = lp->physaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548 dma_addr_t dmabuf;
549
550 /* fallback if no DMA available */
551 if (dma == (unsigned char)-1) {
552 readsw(ioaddr + reg, buf, len);
553 return;
554 }
555
556 /* 64 bit alignment is required for memory to memory DMA */
557 while ((long)buf & 6) {
558 *((u16 *)buf) = SMC_inw(ioaddr, reg);
559 buf += 2;
560 len--;
561 }
562
563 len *= 2;
Russell King073ac8f2007-09-01 21:27:18 +0100564 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 DCSR(dma) = DCSR_NODESC;
566 DTADR(dma) = dmabuf;
567 DSADR(dma) = physaddr + reg;
568 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
569 DCMD_WIDTH2 | (DCMD_LENGTH & len));
570 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
571 while (!(DCSR(dma) & DCSR_STOPSTATE))
572 cpu_relax();
573 DCSR(dma) = 0;
Russell King073ac8f2007-09-01 21:27:18 +0100574 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575}
576#endif
577
578static void
David Howells7d12e782006-10-05 14:55:46 +0100579smc_pxa_dma_irq(int dma, void *dummy)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580{
581 DCSR(dma) = 0;
582}
Eric Miao52256c02008-06-24 15:36:05 +0800583#endif /* CONFIG_ARCH_PXA */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584
585
Nicolas Pitre09779c62006-03-20 11:54:27 -0500586/*
587 * Everything a particular hardware setup needs should have been defined
588 * at this point. Add stubs for the undefined cases, mainly to avoid
589 * compilation warnings since they'll be optimized away, or to prevent buggy
590 * use of them.
591 */
592
593#if ! SMC_CAN_USE_32BIT
594#define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
595#define SMC_outl(x, ioaddr, reg) BUG()
596#define SMC_insl(a, r, p, l) BUG()
597#define SMC_outsl(a, r, p, l) BUG()
598#endif
599
600#if !defined(SMC_insl) || !defined(SMC_outsl)
601#define SMC_insl(a, r, p, l) BUG()
602#define SMC_outsl(a, r, p, l) BUG()
603#endif
604
605#if ! SMC_CAN_USE_16BIT
606
607/*
608 * Any 16-bit access is performed with two 8-bit accesses if the hardware
609 * can't do it directly. Most registers are 16-bit so those are mandatory.
610 */
611#define SMC_outw(x, ioaddr, reg) \
612 do { \
613 unsigned int __val16 = (x); \
614 SMC_outb( __val16, ioaddr, reg ); \
615 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
616 } while (0)
617#define SMC_inw(ioaddr, reg) \
618 ({ \
619 unsigned int __val16; \
620 __val16 = SMC_inb( ioaddr, reg ); \
621 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
622 __val16; \
623 })
624
625#define SMC_insw(a, r, p, l) BUG()
626#define SMC_outsw(a, r, p, l) BUG()
627
628#endif
629
630#if !defined(SMC_insw) || !defined(SMC_outsw)
631#define SMC_insw(a, r, p, l) BUG()
632#define SMC_outsw(a, r, p, l) BUG()
633#endif
634
635#if ! SMC_CAN_USE_8BIT
636#define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
637#define SMC_outb(x, ioaddr, reg) BUG()
638#define SMC_insb(a, r, p, l) BUG()
639#define SMC_outsb(a, r, p, l) BUG()
640#endif
641
642#if !defined(SMC_insb) || !defined(SMC_outsb)
643#define SMC_insb(a, r, p, l) BUG()
644#define SMC_outsb(a, r, p, l) BUG()
645#endif
646
647#ifndef SMC_CAN_USE_DATACS
648#define SMC_CAN_USE_DATACS 0
649#endif
650
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651#ifndef SMC_IO_SHIFT
652#define SMC_IO_SHIFT 0
653#endif
Nicolas Pitre09779c62006-03-20 11:54:27 -0500654
655#ifndef SMC_IRQ_FLAGS
Thomas Gleixner1fb9df52006-07-01 19:29:39 -0700656#define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
Nicolas Pitre09779c62006-03-20 11:54:27 -0500657#endif
658
659#ifndef SMC_INTERRUPT_PREAMBLE
660#define SMC_INTERRUPT_PREAMBLE
661#endif
662
663
664/* Because of bank switching, the LAN91x uses only 16 I/O ports */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
666#define SMC_DATA_EXTENT (4)
667
668/*
669 . Bank Select Register:
670 .
671 . yyyy yyyy 0000 00xx
672 . xx = bank number
673 . yyyy yyyy = 0x33, for identification purposes.
674*/
675#define BANK_SELECT (14 << SMC_IO_SHIFT)
676
677
678// Transmit Control Register
679/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900680#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681#define TCR_ENABLE 0x0001 // When 1 we can transmit
682#define TCR_LOOP 0x0002 // Controls output pin LBK
683#define TCR_FORCOL 0x0004 // When 1 will force a collision
684#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
685#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
686#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
687#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
688#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
689#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
690#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
691
692#define TCR_CLEAR 0 /* do NOTHING */
693/* the default settings for the TCR register : */
694#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
695
696
697// EPH Status Register
698/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900699#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700#define ES_TX_SUC 0x0001 // Last TX was successful
701#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
702#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
703#define ES_LTX_MULT 0x0008 // Last tx was a multicast
704#define ES_16COL 0x0010 // 16 Collisions Reached
705#define ES_SQET 0x0020 // Signal Quality Error Test
706#define ES_LTXBRD 0x0040 // Last tx was a broadcast
707#define ES_TXDEFR 0x0080 // Transmit Deferred
708#define ES_LATCOL 0x0200 // Late collision detected on last tx
709#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
710#define ES_EXC_DEF 0x0800 // Excessive Deferral
711#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
712#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
713#define ES_TXUNRN 0x8000 // Tx Underrun
714
715
716// Receive Control Register
717/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900718#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
720#define RCR_PRMS 0x0002 // Enable promiscuous mode
721#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
722#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
723#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
724#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
725#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
726#define RCR_SOFTRST 0x8000 // resets the chip
727
728/* the normal settings for the RCR register : */
729#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
730#define RCR_CLEAR 0x0 // set it to a base state
731
732
733// Counter Register
734/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900735#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736
737
738// Memory Information Register
739/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900740#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741
742
743// Receive/Phy Control Register
744/* BANK 0 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900745#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
747#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
748#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
749#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
750#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751
752#ifndef RPC_LSA_DEFAULT
753#define RPC_LSA_DEFAULT RPC_LED_100
754#endif
755#ifndef RPC_LSB_DEFAULT
756#define RPC_LSB_DEFAULT RPC_LED_FD
757#endif
758
Russell Kingb0dbcf52008-09-04 21:13:37 +0100759#define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760
761
762/* Bank 0 0x0C is reserved */
763
764// Bank Select Register
765/* All Banks */
766#define BSR_REG 0x000E
767
768
769// Configuration Reg
770/* BANK 1 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900771#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
773#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
774#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
775#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
776
777// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
778#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
779
780
781// Base Address Register
782/* BANK 1 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900783#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784
785
786// Individual Address Registers
787/* BANK 1 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900788#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
789#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
790#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700791
792
793// General Purpose Register
794/* BANK 1 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900795#define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796
797
798// Control Register
799/* BANK 1 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900800#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
802#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
803#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
804#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
805#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
806#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
807#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
808#define CTL_STORE 0x0001 // When set stores registers into EEPROM
809
810
811// MMU Command Register
812/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900813#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814#define MC_BUSY 1 // When 1 the last release has not completed
815#define MC_NOP (0<<5) // No Op
816#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
817#define MC_RESET (2<<5) // Reset MMU to initial state
818#define MC_REMOVE (3<<5) // Remove the current rx packet
819#define MC_RELEASE (4<<5) // Remove and release the current rx packet
820#define MC_FREEPKT (5<<5) // Release packet in PNR register
821#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
822#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
823
824
825// Packet Number Register
826/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900827#define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828
829
830// Allocation Result Register
831/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900832#define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833#define AR_FAILED 0x80 // Alocation Failed
834
835
836// TX FIFO Ports Register
837/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900838#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
840
841// RX FIFO Ports Register
842/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900843#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
845
Magnus Dammcfdfa862008-02-22 19:55:05 +0900846#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847
848// Pointer Register
849/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900850#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
852#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
853#define PTR_READ 0x2000 // When 1 the operation is a read
854
855
856// Data Register
857/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900858#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859
860
861// Interrupt Status/Acknowledge Register
862/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900863#define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864
865
866// Interrupt Mask Register
867/* BANK 2 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900868#define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
870#define IM_ERCV_INT 0x40 // Early Receive Interrupt
871#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
872#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
873#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
874#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
875#define IM_TX_INT 0x02 // Transmit Interrupt
876#define IM_RCV_INT 0x01 // Receive Interrupt
877
878
879// Multicast Table Registers
880/* BANK 3 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900881#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
882#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
883#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
884#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700885
886
887// Management Interface Register (MII)
888/* BANK 3 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900889#define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
891#define MII_MDOE 0x0008 // MII Output Enable
892#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
893#define MII_MDI 0x0002 // MII Input, pin MDI
894#define MII_MDO 0x0001 // MII Output, pin MDO
895
896
897// Revision Register
898/* BANK 3 */
899/* ( hi: chip id low: rev # ) */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900900#define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901
902
903// Early RCV Register
904/* BANK 3 */
905/* this is NOT on SMC9192 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900906#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
908#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
909
910
911// External Register
912/* BANK 7 */
Magnus Dammcfdfa862008-02-22 19:55:05 +0900913#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914
915
916#define CHIP_9192 3
917#define CHIP_9194 4
918#define CHIP_9195 5
919#define CHIP_9196 6
920#define CHIP_91100 7
921#define CHIP_91100FD 8
922#define CHIP_91111FD 9
923
924static const char * chip_ids[ 16 ] = {
925 NULL, NULL, NULL,
926 /* 3 */ "SMC91C90/91C92",
927 /* 4 */ "SMC91C94",
928 /* 5 */ "SMC91C95",
929 /* 6 */ "SMC91C96",
930 /* 7 */ "SMC91C100",
931 /* 8 */ "SMC91C100FD",
932 /* 9 */ "SMC91C11xFD",
933 NULL, NULL, NULL,
934 NULL, NULL, NULL};
935
936
937/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 . Receive status bits
939*/
940#define RS_ALGNERR 0x8000
941#define RS_BRODCAST 0x4000
942#define RS_BADCRC 0x2000
943#define RS_ODDFRAME 0x1000
944#define RS_TOOLONG 0x0800
945#define RS_TOOSHORT 0x0400
946#define RS_MULTICAST 0x0001
947#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
948
949
950/*
951 * PHY IDs
952 * LAN83C183 == LAN91C111 Internal PHY
953 */
954#define PHY_LAN83C183 0x0016f840
955#define PHY_LAN83C180 0x02821c50
956
957/*
958 * PHY Register Addresses (LAN91C111 Internal PHY)
959 *
960 * Generic PHY registers can be found in <linux/mii.h>
961 *
962 * These phy registers are specific to our on-board phy.
963 */
964
965// PHY Configuration Register 1
966#define PHY_CFG1_REG 0x10
967#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
968#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
969#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
970#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
971#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
972#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
973#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
974#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
975#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
976#define PHY_CFG1_TLVL_MASK 0x003C
977#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
978
979
980// PHY Configuration Register 2
981#define PHY_CFG2_REG 0x11
982#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
983#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
984#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
985#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
986
987// PHY Status Output (and Interrupt status) Register
988#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
989#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
990#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
991#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
992#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
993#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
994#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
995#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
996#define PHY_INT_JAB 0x0100 // 1=Jabber detected
997#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
998#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
999
1000// PHY Interrupt/Status Mask Register
1001#define PHY_MASK_REG 0x13 // Interrupt Mask
1002// Uses the same bit definitions as PHY_INT_REG
1003
1004
1005/*
1006 * SMC91C96 ethernet config and status registers.
1007 * These are in the "attribute" space.
1008 */
1009#define ECOR 0x8000
1010#define ECOR_RESET 0x80
1011#define ECOR_LEVEL_IRQ 0x40
1012#define ECOR_WR_ATTRIB 0x04
1013#define ECOR_ENABLE 0x01
1014
1015#define ECSR 0x8002
1016#define ECSR_IOIS8 0x20
1017#define ECSR_PWRDWN 0x04
1018#define ECSR_INT 0x02
1019
1020#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1021
1022
1023/*
1024 * Macros to abstract register access according to the data bus
1025 * capabilities. Please use those and not the in/out primitives.
1026 * Note: the following macros do *not* select the bank -- this must
1027 * be done separately as needed in the main code. The SMC_REG() macro
1028 * only uses the bank argument for debugging purposes (when enabled).
Nicolas Pitre09779c62006-03-20 11:54:27 -05001029 *
1030 * Note: despite inline functions being safer, everything leading to this
1031 * should preferably be macros to let BUG() display the line number in
1032 * the core source code since we're interested in the top call site
1033 * not in any inline function location.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034 */
1035
1036#if SMC_DEBUG > 0
Magnus Dammcfdfa862008-02-22 19:55:05 +09001037#define SMC_REG(lp, reg, bank) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001038 ({ \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001039 int __b = SMC_CURRENT_BANK(lp); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001040 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1041 printk( "%s: bank reg screwed (0x%04x)\n", \
1042 CARDNAME, __b ); \
1043 BUG(); \
1044 } \
1045 reg<<SMC_IO_SHIFT; \
1046 })
1047#else
Magnus Dammcfdfa862008-02-22 19:55:05 +09001048#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049#endif
1050
Nicolas Pitre09779c62006-03-20 11:54:27 -05001051/*
1052 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1053 * aligned to a 32 bit boundary. I tell you that does exist!
1054 * Fortunately the affected register accesses can be easily worked around
1055 * since we can write zeroes to the preceeding 16 bits without adverse
1056 * effects and use a 32-bit access.
1057 *
1058 * Enforce it on any 32-bit capable setup for now.
1059 */
Magnus Damm3e947942008-02-22 19:55:15 +09001060#define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
Nicolas Pitre09779c62006-03-20 11:54:27 -05001061
Magnus Dammcfdfa862008-02-22 19:55:05 +09001062#define SMC_GET_PN(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001063 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001064 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001065
Magnus Dammcfdfa862008-02-22 19:55:05 +09001066#define SMC_SET_PN(lp, x) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001067 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001068 if (SMC_MUST_ALIGN_WRITE(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001069 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
Magnus Damm3e947942008-02-22 19:55:15 +09001070 else if (SMC_8BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001071 SMC_outb(x, ioaddr, PN_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001072 else \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001073 SMC_outw(x, ioaddr, PN_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001074 } while (0)
1075
Magnus Dammcfdfa862008-02-22 19:55:05 +09001076#define SMC_GET_AR(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001077 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001078 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001079
Magnus Dammcfdfa862008-02-22 19:55:05 +09001080#define SMC_GET_TXFIFO(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001081 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001082 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001083
Magnus Dammcfdfa862008-02-22 19:55:05 +09001084#define SMC_GET_RXFIFO(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001085 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001086 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001087
Magnus Dammcfdfa862008-02-22 19:55:05 +09001088#define SMC_GET_INT(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001089 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001090 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001091
Magnus Dammcfdfa862008-02-22 19:55:05 +09001092#define SMC_ACK_INT(lp, x) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001094 if (SMC_8BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001095 SMC_outb(x, ioaddr, INT_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001096 else { \
1097 unsigned long __flags; \
1098 int __mask; \
1099 local_irq_save(__flags); \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001100 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1101 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001102 local_irq_restore(__flags); \
1103 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104 } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105
Magnus Dammcfdfa862008-02-22 19:55:05 +09001106#define SMC_GET_INT_MASK(lp) \
Magnus Damm3e947942008-02-22 19:55:15 +09001107 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001108 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001109
Magnus Dammcfdfa862008-02-22 19:55:05 +09001110#define SMC_SET_INT_MASK(lp, x) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001111 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001112 if (SMC_8BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001113 SMC_outb(x, ioaddr, IM_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001114 else \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001115 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001116 } while (0)
1117
Magnus Dammcfdfa862008-02-22 19:55:05 +09001118#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
Nicolas Pitre09779c62006-03-20 11:54:27 -05001119
Magnus Dammcfdfa862008-02-22 19:55:05 +09001120#define SMC_SELECT_BANK(lp, x) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001121 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001122 if (SMC_MUST_ALIGN_WRITE(lp)) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001123 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1124 else \
1125 SMC_outw(x, ioaddr, BANK_SELECT); \
1126 } while (0)
1127
Magnus Dammcfdfa862008-02-22 19:55:05 +09001128#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001129
Magnus Dammcfdfa862008-02-22 19:55:05 +09001130#define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001131
Magnus Dammcfdfa862008-02-22 19:55:05 +09001132#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001133
Magnus Dammcfdfa862008-02-22 19:55:05 +09001134#define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001135
Magnus Dammcfdfa862008-02-22 19:55:05 +09001136#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001137
Magnus Dammcfdfa862008-02-22 19:55:05 +09001138#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001139
Magnus Dammcfdfa862008-02-22 19:55:05 +09001140#define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001141
Magnus Dammcfdfa862008-02-22 19:55:05 +09001142#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001143
Magnus Dammcfdfa862008-02-22 19:55:05 +09001144#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001145
Magnus Dammcfdfa862008-02-22 19:55:05 +09001146#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001147
Magnus Dammcfdfa862008-02-22 19:55:05 +09001148#define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001149
Magnus Dammcfdfa862008-02-22 19:55:05 +09001150#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001151
Magnus Dammcfdfa862008-02-22 19:55:05 +09001152#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001153
Magnus Dammcfdfa862008-02-22 19:55:05 +09001154#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001155
Magnus Dammcfdfa862008-02-22 19:55:05 +09001156#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001157
Magnus Dammcfdfa862008-02-22 19:55:05 +09001158#define SMC_SET_PTR(lp, x) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001159 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001160 if (SMC_MUST_ALIGN_WRITE(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001161 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001162 else \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001163 SMC_outw(x, ioaddr, PTR_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001164 } while (0)
1165
Magnus Dammcfdfa862008-02-22 19:55:05 +09001166#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001167
Magnus Dammcfdfa862008-02-22 19:55:05 +09001168#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001169
Magnus Dammcfdfa862008-02-22 19:55:05 +09001170#define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001171
Magnus Dammcfdfa862008-02-22 19:55:05 +09001172#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001173
Magnus Dammcfdfa862008-02-22 19:55:05 +09001174#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001175
Magnus Dammcfdfa862008-02-22 19:55:05 +09001176#define SMC_SET_RPC(lp, x) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001177 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001178 if (SMC_MUST_ALIGN_WRITE(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001179 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001180 else \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001181 SMC_outw(x, ioaddr, RPC_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001182 } while (0)
1183
Magnus Dammcfdfa862008-02-22 19:55:05 +09001184#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
Nicolas Pitre09779c62006-03-20 11:54:27 -05001185
Magnus Dammcfdfa862008-02-22 19:55:05 +09001186#define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001187
1188#ifndef SMC_GET_MAC_ADDR
Magnus Dammcfdfa862008-02-22 19:55:05 +09001189#define SMC_GET_MAC_ADDR(lp, addr) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190 do { \
1191 unsigned int __v; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001192 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193 addr[0] = __v; addr[1] = __v >> 8; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001194 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001195 addr[2] = __v; addr[3] = __v >> 8; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001196 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197 addr[4] = __v; addr[5] = __v >> 8; \
1198 } while (0)
1199#endif
1200
Magnus Dammcfdfa862008-02-22 19:55:05 +09001201#define SMC_SET_MAC_ADDR(lp, addr) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001202 do { \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001203 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1204 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1205 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001206 } while (0)
1207
Magnus Dammcfdfa862008-02-22 19:55:05 +09001208#define SMC_SET_MCAST(lp, x) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001209 do { \
1210 const unsigned char *mt = (x); \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001211 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1212 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1213 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1214 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215 } while (0)
1216
Magnus Dammcfdfa862008-02-22 19:55:05 +09001217#define SMC_PUT_PKT_HDR(lp, status, length) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001219 if (SMC_32BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001220 SMC_outl((status) | (length)<<16, ioaddr, \
1221 DATA_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001222 else { \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001223 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1224 SMC_outw(length, ioaddr, DATA_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001225 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226 } while (0)
Nicolas Pitre09779c62006-03-20 11:54:27 -05001227
Magnus Dammcfdfa862008-02-22 19:55:05 +09001228#define SMC_GET_PKT_HDR(lp, status, length) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001230 if (SMC_32BIT(lp)) { \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001231 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001232 (status) = __val & 0xffff; \
1233 (length) = __val >> 16; \
1234 } else { \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001235 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1236 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237 } \
1238 } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239
Magnus Dammcfdfa862008-02-22 19:55:05 +09001240#define SMC_PUSH_DATA(lp, p, l) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001241 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001242 if (SMC_32BIT(lp)) { \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001243 void *__ptr = (p); \
1244 int __len = (l); \
Al Virofbd81972006-05-30 23:58:25 -04001245 void __iomem *__ioaddr = ioaddr; \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001246 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1247 __len -= 2; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001248 SMC_outw(*(u16 *)__ptr, ioaddr, \
1249 DATA_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001250 __ptr += 2; \
1251 } \
1252 if (SMC_CAN_USE_DATACS && lp->datacs) \
1253 __ioaddr = lp->datacs; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001254 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001255 if (__len & 2) { \
1256 __ptr += (__len & ~3); \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001257 SMC_outw(*((u16 *)__ptr), ioaddr, \
1258 DATA_REG(lp)); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001259 } \
Magnus Damm3e947942008-02-22 19:55:15 +09001260 } else if (SMC_16BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001261 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
Magnus Damm3e947942008-02-22 19:55:15 +09001262 else if (SMC_8BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001263 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001264 } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001265
Magnus Dammcfdfa862008-02-22 19:55:05 +09001266#define SMC_PULL_DATA(lp, p, l) \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001267 do { \
Magnus Damm3e947942008-02-22 19:55:15 +09001268 if (SMC_32BIT(lp)) { \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001269 void *__ptr = (p); \
1270 int __len = (l); \
Al Virofbd81972006-05-30 23:58:25 -04001271 void __iomem *__ioaddr = ioaddr; \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001272 if ((unsigned long)__ptr & 2) { \
1273 /* \
1274 * We want 32bit alignment here. \
1275 * Since some buses perform a full \
1276 * 32bit fetch even for 16bit data \
1277 * we can't use SMC_inw() here. \
1278 * Back both source (on-chip) and \
1279 * destination pointers of 2 bytes. \
1280 * This is possible since the call to \
1281 * SMC_GET_PKT_HDR() already advanced \
1282 * the source pointer of 4 bytes, and \
1283 * the skb_reserve(skb, 2) advanced \
1284 * the destination pointer of 2 bytes. \
1285 */ \
1286 __ptr -= 2; \
1287 __len += 2; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001288 SMC_SET_PTR(lp, \
1289 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001290 } \
1291 if (SMC_CAN_USE_DATACS && lp->datacs) \
1292 __ioaddr = lp->datacs; \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001293 __len += 2; \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001294 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
Magnus Damm3e947942008-02-22 19:55:15 +09001295 } else if (SMC_16BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001296 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
Magnus Damm3e947942008-02-22 19:55:15 +09001297 else if (SMC_8BIT(lp)) \
Magnus Dammcfdfa862008-02-22 19:55:05 +09001298 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
Nicolas Pitre09779c62006-03-20 11:54:27 -05001299 } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300
1301#endif /* _SMC91X_H_ */