blob: 76ac70a385459940e7a26205d53dd05cfb8b1334 [file] [log] [blame]
Kristian Høgsberged568912006-12-19 19:58:35 -05001/* -*- c-basic-offset: 8 -*-
2 *
3 * fw-ohci.c - Driver for OHCI 1394 boards
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/poll.h>
Andrew Mortoncf3e72f2006-12-27 14:36:37 -080028#include <linux/dma-mapping.h>
29
Kristian Høgsberged568912006-12-19 19:58:35 -050030#include <asm/uaccess.h>
31#include <asm/semaphore.h>
32
33#include "fw-transaction.h"
34#include "fw-ohci.h"
35
36#define descriptor_output_more 0
37#define descriptor_output_last (1 << 12)
38#define descriptor_input_more (2 << 12)
39#define descriptor_input_last (3 << 12)
40#define descriptor_status (1 << 11)
41#define descriptor_key_immediate (2 << 8)
42#define descriptor_ping (1 << 7)
43#define descriptor_yy (1 << 6)
44#define descriptor_no_irq (0 << 4)
45#define descriptor_irq_error (1 << 4)
46#define descriptor_irq_always (3 << 4)
47#define descriptor_branch_always (3 << 2)
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -050048#define descriptor_wait (3 << 0)
Kristian Høgsberged568912006-12-19 19:58:35 -050049
50struct descriptor {
51 __le16 req_count;
52 __le16 control;
53 __le32 data_address;
54 __le32 branch_address;
55 __le16 res_count;
56 __le16 transfer_status;
57} __attribute__((aligned(16)));
58
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -050059struct db_descriptor {
60 __le16 first_size;
61 __le16 control;
62 __le16 second_req_count;
63 __le16 first_req_count;
64 __le32 branch_address;
65 __le16 second_res_count;
66 __le16 first_res_count;
67 __le32 reserved0;
68 __le32 first_buffer;
69 __le32 second_buffer;
70 __le32 reserved1;
71} __attribute__((aligned(16)));
72
Kristian Høgsberg72e318e2007-02-06 14:49:31 -050073#define control_set(regs) (regs)
74#define control_clear(regs) ((regs) + 4)
75#define command_ptr(regs) ((regs) + 12)
76#define context_match(regs) ((regs) + 16)
77
Kristian Høgsberg32b46092007-02-06 14:49:30 -050078struct ar_buffer {
79 struct descriptor descriptor;
80 struct ar_buffer *next;
81 __le32 data[0];
82};
83
Kristian Høgsberged568912006-12-19 19:58:35 -050084struct ar_context {
85 struct fw_ohci *ohci;
Kristian Høgsberg32b46092007-02-06 14:49:30 -050086 struct ar_buffer *current_buffer;
87 struct ar_buffer *last_buffer;
88 void *pointer;
Kristian Høgsberg72e318e2007-02-06 14:49:31 -050089 u32 regs;
Kristian Høgsberged568912006-12-19 19:58:35 -050090 struct tasklet_struct tasklet;
91};
92
Kristian Høgsberg30200732007-02-16 17:34:39 -050093struct context;
94
95typedef int (*descriptor_callback_t)(struct context *ctx,
96 struct descriptor *d,
97 struct descriptor *last);
98struct context {
99 struct fw_ohci *ohci;
100 u32 regs;
101
102 struct descriptor *buffer;
103 dma_addr_t buffer_bus;
104 size_t buffer_size;
105 struct descriptor *head_descriptor;
106 struct descriptor *tail_descriptor;
107 struct descriptor *tail_descriptor_last;
108 struct descriptor *prev_descriptor;
109
110 descriptor_callback_t callback;
111
112 struct tasklet_struct tasklet;
113};
114
115
116
Kristian Høgsberged568912006-12-19 19:58:35 -0500117struct at_context {
118 struct fw_ohci *ohci;
119 dma_addr_t descriptor_bus;
120 dma_addr_t buffer_bus;
Kristian Høgsberg730c32f2007-02-06 14:49:32 -0500121 struct fw_packet *current_packet;
Kristian Høgsberged568912006-12-19 19:58:35 -0500122
123 struct list_head list;
124
125 struct {
126 struct descriptor more;
127 __le32 header[4];
128 struct descriptor last;
129 } d;
130
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500131 u32 regs;
Kristian Høgsberged568912006-12-19 19:58:35 -0500132
133 struct tasklet_struct tasklet;
134};
135
136#define it_header_sy(v) ((v) << 0)
137#define it_header_tcode(v) ((v) << 4)
138#define it_header_channel(v) ((v) << 8)
139#define it_header_tag(v) ((v) << 14)
140#define it_header_speed(v) ((v) << 16)
141#define it_header_data_length(v) ((v) << 16)
142
143struct iso_context {
144 struct fw_iso_context base;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500145 struct context context;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -0500146 void *header;
147 size_t header_length;
Kristian Høgsberged568912006-12-19 19:58:35 -0500148};
149
150#define CONFIG_ROM_SIZE 1024
151
152struct fw_ohci {
153 struct fw_card card;
154
155 __iomem char *registers;
156 dma_addr_t self_id_bus;
157 __le32 *self_id_cpu;
158 struct tasklet_struct bus_reset_tasklet;
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500159 int node_id;
Kristian Høgsberged568912006-12-19 19:58:35 -0500160 int generation;
161 int request_generation;
162
163 /* Spinlock for accessing fw_ohci data. Never call out of
164 * this driver with this lock held. */
165 spinlock_t lock;
166 u32 self_id_buffer[512];
167
168 /* Config rom buffers */
169 __be32 *config_rom;
170 dma_addr_t config_rom_bus;
171 __be32 *next_config_rom;
172 dma_addr_t next_config_rom_bus;
173 u32 next_header;
174
175 struct ar_context ar_request_ctx;
176 struct ar_context ar_response_ctx;
177 struct at_context at_request_ctx;
178 struct at_context at_response_ctx;
179
180 u32 it_context_mask;
181 struct iso_context *it_context_list;
182 u32 ir_context_mask;
183 struct iso_context *ir_context_list;
184};
185
Adrian Bunk95688e92007-01-22 19:17:37 +0100186static inline struct fw_ohci *fw_ohci(struct fw_card *card)
Kristian Høgsberged568912006-12-19 19:58:35 -0500187{
188 return container_of(card, struct fw_ohci, card);
189}
190
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -0500191#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
192#define IR_CONTEXT_BUFFER_FILL 0x80000000
193#define IR_CONTEXT_ISOCH_HEADER 0x40000000
194#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
195#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
196#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
Kristian Høgsberged568912006-12-19 19:58:35 -0500197
198#define CONTEXT_RUN 0x8000
199#define CONTEXT_WAKE 0x1000
200#define CONTEXT_DEAD 0x0800
201#define CONTEXT_ACTIVE 0x0400
202
203#define OHCI1394_MAX_AT_REQ_RETRIES 0x2
204#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
205#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
206
207#define FW_OHCI_MAJOR 240
208#define OHCI1394_REGISTER_SIZE 0x800
209#define OHCI_LOOP_COUNT 500
210#define OHCI1394_PCI_HCI_Control 0x40
211#define SELF_ID_BUF_SIZE 0x800
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500212#define OHCI_TCODE_PHY_PACKET 0x0e
Kristian Høgsberg0edeefd2007-01-26 00:38:49 -0500213
Kristian Høgsberged568912006-12-19 19:58:35 -0500214static char ohci_driver_name[] = KBUILD_MODNAME;
215
Adrian Bunk95688e92007-01-22 19:17:37 +0100216static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
Kristian Høgsberged568912006-12-19 19:58:35 -0500217{
218 writel(data, ohci->registers + offset);
219}
220
Adrian Bunk95688e92007-01-22 19:17:37 +0100221static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
Kristian Høgsberged568912006-12-19 19:58:35 -0500222{
223 return readl(ohci->registers + offset);
224}
225
Adrian Bunk95688e92007-01-22 19:17:37 +0100226static inline void flush_writes(const struct fw_ohci *ohci)
Kristian Høgsberged568912006-12-19 19:58:35 -0500227{
228 /* Do a dummy read to flush writes. */
229 reg_read(ohci, OHCI1394_Version);
230}
231
232static int
233ohci_update_phy_reg(struct fw_card *card, int addr,
234 int clear_bits, int set_bits)
235{
236 struct fw_ohci *ohci = fw_ohci(card);
237 u32 val, old;
238
239 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
240 msleep(2);
241 val = reg_read(ohci, OHCI1394_PhyControl);
242 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
243 fw_error("failed to set phy reg bits.\n");
244 return -EBUSY;
245 }
246
247 old = OHCI1394_PhyControl_ReadData(val);
248 old = (old & ~clear_bits) | set_bits;
249 reg_write(ohci, OHCI1394_PhyControl,
250 OHCI1394_PhyControl_Write(addr, old));
251
252 return 0;
253}
254
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500255static int ar_context_add_page(struct ar_context *ctx)
Kristian Høgsberged568912006-12-19 19:58:35 -0500256{
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500257 struct device *dev = ctx->ohci->card.device;
258 struct ar_buffer *ab;
259 dma_addr_t ab_bus;
260 size_t offset;
261
262 ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC);
263 if (ab == NULL)
264 return -ENOMEM;
265
266 ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL);
267 if (dma_mapping_error(ab_bus)) {
268 free_page((unsigned long) ab);
269 return -ENOMEM;
270 }
271
272 memset(&ab->descriptor, 0, sizeof ab->descriptor);
273 ab->descriptor.control = cpu_to_le16(descriptor_input_more |
274 descriptor_status |
275 descriptor_branch_always);
276 offset = offsetof(struct ar_buffer, data);
277 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
278 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
279 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
280 ab->descriptor.branch_address = 0;
281
282 dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
283
284 ctx->last_buffer->descriptor.branch_address = ab_bus | 1;
285 ctx->last_buffer->next = ab;
286 ctx->last_buffer = ab;
287
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500288 reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE);
Kristian Høgsberged568912006-12-19 19:58:35 -0500289 flush_writes(ctx->ohci);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500290
291 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -0500292}
293
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500294static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
Kristian Høgsberged568912006-12-19 19:58:35 -0500295{
Kristian Høgsberged568912006-12-19 19:58:35 -0500296 struct fw_ohci *ohci = ctx->ohci;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500297 struct fw_packet p;
298 u32 status, length, tcode;
Kristian Høgsberg0edeefd2007-01-26 00:38:49 -0500299
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500300 p.header[0] = le32_to_cpu(buffer[0]);
301 p.header[1] = le32_to_cpu(buffer[1]);
302 p.header[2] = le32_to_cpu(buffer[2]);
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500303
304 tcode = (p.header[0] >> 4) & 0x0f;
305 switch (tcode) {
306 case TCODE_WRITE_QUADLET_REQUEST:
307 case TCODE_READ_QUADLET_RESPONSE:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500308 p.header[3] = (__force __u32) buffer[3];
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500309 p.header_length = 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500310 p.payload_length = 0;
311 break;
312
313 case TCODE_READ_BLOCK_REQUEST :
314 p.header[3] = le32_to_cpu(buffer[3]);
315 p.header_length = 16;
316 p.payload_length = 0;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500317 break;
318
319 case TCODE_WRITE_BLOCK_REQUEST:
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500320 case TCODE_READ_BLOCK_RESPONSE:
321 case TCODE_LOCK_REQUEST:
322 case TCODE_LOCK_RESPONSE:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500323 p.header[3] = le32_to_cpu(buffer[3]);
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500324 p.header_length = 16;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500325 p.payload_length = p.header[3] >> 16;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500326 break;
327
328 case TCODE_WRITE_RESPONSE:
329 case TCODE_READ_QUADLET_REQUEST:
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500330 case OHCI_TCODE_PHY_PACKET:
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500331 p.header_length = 12;
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500332 p.payload_length = 0;
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500333 break;
334 }
335
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500336 p.payload = (void *) buffer + p.header_length;
337
338 /* FIXME: What to do about evt_* errors? */
339 length = (p.header_length + p.payload_length + 3) / 4;
340 status = le32_to_cpu(buffer[length]);
341
342 p.ack = ((status >> 16) & 0x1f) - 16;
343 p.speed = (status >> 21) & 0x7;
344 p.timestamp = status & 0xffff;
345 p.generation = ohci->request_generation;
Kristian Høgsberged568912006-12-19 19:58:35 -0500346
347 /* The OHCI bus reset handler synthesizes a phy packet with
348 * the new generation number when a bus reset happens (see
349 * section 8.4.2.3). This helps us determine when a request
350 * was received and make sure we send the response in the same
351 * generation. We only need this for requests; for responses
352 * we use the unique tlabel for finding the matching
353 * request. */
354
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500355 if (p.ack + 16 == 0x09)
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500356 ohci->request_generation = (buffer[2] >> 16) & 0xff;
Kristian Høgsberged568912006-12-19 19:58:35 -0500357 else if (ctx == &ohci->ar_request_ctx)
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500358 fw_core_handle_request(&ohci->card, &p);
Kristian Høgsberged568912006-12-19 19:58:35 -0500359 else
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500360 fw_core_handle_response(&ohci->card, &p);
Kristian Høgsberged568912006-12-19 19:58:35 -0500361
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500362 return buffer + length + 1;
363}
Kristian Høgsberged568912006-12-19 19:58:35 -0500364
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500365static void ar_context_tasklet(unsigned long data)
366{
367 struct ar_context *ctx = (struct ar_context *)data;
368 struct fw_ohci *ohci = ctx->ohci;
369 struct ar_buffer *ab;
370 struct descriptor *d;
371 void *buffer, *end;
Kristian Høgsberged568912006-12-19 19:58:35 -0500372
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500373 ab = ctx->current_buffer;
374 d = &ab->descriptor;
Kristian Høgsberged568912006-12-19 19:58:35 -0500375
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500376 if (d->res_count == 0) {
377 size_t size, rest, offset;
378
379 /* This descriptor is finished and we may have a
380 * packet split across this and the next buffer. We
381 * reuse the page for reassembling the split packet. */
382
383 offset = offsetof(struct ar_buffer, data);
384 dma_unmap_single(ohci->card.device,
385 ab->descriptor.data_address - offset,
386 PAGE_SIZE, DMA_BIDIRECTIONAL);
387
388 buffer = ab;
389 ab = ab->next;
390 d = &ab->descriptor;
391 size = buffer + PAGE_SIZE - ctx->pointer;
392 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
393 memmove(buffer, ctx->pointer, size);
394 memcpy(buffer + size, ab->data, rest);
395 ctx->current_buffer = ab;
396 ctx->pointer = (void *) ab->data + rest;
397 end = buffer + size + rest;
398
399 while (buffer < end)
400 buffer = handle_ar_packet(ctx, buffer);
401
402 free_page((unsigned long)buffer);
403 ar_context_add_page(ctx);
404 } else {
405 buffer = ctx->pointer;
406 ctx->pointer = end =
407 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
408
409 while (buffer < end)
410 buffer = handle_ar_packet(ctx, buffer);
411 }
Kristian Høgsberged568912006-12-19 19:58:35 -0500412}
413
414static int
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500415ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
Kristian Høgsberged568912006-12-19 19:58:35 -0500416{
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500417 struct ar_buffer ab;
Kristian Høgsberged568912006-12-19 19:58:35 -0500418
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500419 ctx->regs = regs;
420 ctx->ohci = ohci;
421 ctx->last_buffer = &ab;
Kristian Høgsberged568912006-12-19 19:58:35 -0500422 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
423
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500424 ar_context_add_page(ctx);
425 ar_context_add_page(ctx);
426 ctx->current_buffer = ab.next;
427 ctx->pointer = ctx->current_buffer->data;
428
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500429 reg_write(ctx->ohci, command_ptr(ctx->regs), ab.descriptor.branch_address);
430 reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_RUN);
Kristian Høgsberg32b46092007-02-06 14:49:30 -0500431 flush_writes(ctx->ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -0500432
433 return 0;
434}
Kristian Høgsberg30200732007-02-16 17:34:39 -0500435
436static void context_tasklet(unsigned long data)
437{
438 struct context *ctx = (struct context *) data;
439 struct fw_ohci *ohci = ctx->ohci;
440 struct descriptor *d, *last;
441 u32 address;
442 int z;
443
444 dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
445 ctx->buffer_size, DMA_TO_DEVICE);
446
447 d = ctx->tail_descriptor;
448 last = ctx->tail_descriptor_last;
449
450 while (last->branch_address != 0) {
451 address = le32_to_cpu(last->branch_address);
452 z = address & 0xf;
453 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d;
454 last = (z == 2) ? d : d + z - 1;
455
456 if (!ctx->callback(ctx, d, last))
457 break;
458
459 ctx->tail_descriptor = d;
460 ctx->tail_descriptor_last = last;
461 }
462}
463
464static int
465context_init(struct context *ctx, struct fw_ohci *ohci,
466 size_t buffer_size, u32 regs,
467 descriptor_callback_t callback)
468{
469 ctx->ohci = ohci;
470 ctx->regs = regs;
471 ctx->buffer_size = buffer_size;
472 ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);
473 if (ctx->buffer == NULL)
474 return -ENOMEM;
475
476 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
477 ctx->callback = callback;
478
479 ctx->buffer_bus =
480 dma_map_single(ohci->card.device, ctx->buffer,
481 buffer_size, DMA_TO_DEVICE);
482 if (dma_mapping_error(ctx->buffer_bus)) {
483 kfree(ctx->buffer);
484 return -ENOMEM;
485 }
486
487 ctx->head_descriptor = ctx->buffer;
488 ctx->prev_descriptor = ctx->buffer;
489 ctx->tail_descriptor = ctx->buffer;
490 ctx->tail_descriptor_last = ctx->buffer;
491
492 /* We put a dummy descriptor in the buffer that has a NULL
493 * branch address and looks like it's been sent. That way we
494 * have a descriptor to append DMA programs to. Also, the
495 * ring buffer invariant is that it always has at least one
496 * element so that head == tail means buffer full. */
497
498 memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
499 ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last);
500 ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
501 ctx->head_descriptor++;
502
503 return 0;
504}
505
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -0500506static void
Kristian Høgsberg30200732007-02-16 17:34:39 -0500507context_release(struct context *ctx)
508{
509 struct fw_card *card = &ctx->ohci->card;
510
511 dma_unmap_single(card->device, ctx->buffer_bus,
512 ctx->buffer_size, DMA_TO_DEVICE);
513 kfree(ctx->buffer);
514}
515
516static struct descriptor *
517context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
518{
519 struct descriptor *d, *tail, *end;
520
521 d = ctx->head_descriptor;
522 tail = ctx->tail_descriptor;
523 end = ctx->buffer + ctx->buffer_size / sizeof(struct descriptor);
524
525 if (d + z <= tail) {
526 goto has_space;
527 } else if (d > tail && d + z <= end) {
528 goto has_space;
529 } else if (d > tail && ctx->buffer + z <= tail) {
530 d = ctx->buffer;
531 goto has_space;
532 }
533
534 return NULL;
535
536 has_space:
537 memset(d, 0, z * sizeof *d);
538 *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
539
540 return d;
541}
542
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -0500543static void context_run(struct context *ctx, u32 extra)
Kristian Høgsberg30200732007-02-16 17:34:39 -0500544{
545 struct fw_ohci *ohci = ctx->ohci;
546
547 reg_write(ohci, command_ptr(ctx->regs),
548 le32_to_cpu(ctx->tail_descriptor_last->branch_address));
549 reg_write(ohci, control_clear(ctx->regs), ~0);
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -0500550 reg_write(ohci, control_set(ctx->regs), CONTEXT_RUN | extra);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500551 flush_writes(ohci);
552}
553
554static void context_append(struct context *ctx,
555 struct descriptor *d, int z, int extra)
556{
557 dma_addr_t d_bus;
558
559 d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
560
561 ctx->head_descriptor = d + z + extra;
562 ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
563 ctx->prev_descriptor = z == 2 ? d : d + z - 1;
564
565 dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
566 ctx->buffer_size, DMA_TO_DEVICE);
567
568 reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE);
569 flush_writes(ctx->ohci);
570}
571
572static void context_stop(struct context *ctx)
573{
574 u32 reg;
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500575 int i;
Kristian Høgsberg30200732007-02-16 17:34:39 -0500576
577 reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN);
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500578 flush_writes(ctx->ohci);
Kristian Høgsberg30200732007-02-16 17:34:39 -0500579
Kristian Høgsbergb8295662007-02-16 17:34:42 -0500580 for (i = 0; i < 10; i++) {
581 reg = reg_read(ctx->ohci, control_set(ctx->regs));
582 if ((reg & CONTEXT_ACTIVE) == 0)
583 break;
584
585 fw_notify("context_stop: still active (0x%08x)\n", reg);
586 msleep(1);
587 }
Kristian Høgsberg30200732007-02-16 17:34:39 -0500588}
Kristian Høgsberged568912006-12-19 19:58:35 -0500589
590static void
591do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list)
592{
593 struct fw_packet *p, *next;
594
595 list_for_each_entry_safe(p, next, list, link)
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500596 p->callback(p, &ohci->card, p->ack);
Kristian Høgsberged568912006-12-19 19:58:35 -0500597}
598
599static void
600complete_transmission(struct fw_packet *packet,
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500601 int ack, struct list_head *list)
Kristian Høgsberged568912006-12-19 19:58:35 -0500602{
603 list_move_tail(&packet->link, list);
Kristian Høgsberg2639a6f2007-01-26 00:37:57 -0500604 packet->ack = ack;
Kristian Høgsberged568912006-12-19 19:58:35 -0500605}
606
607/* This function prepares the first packet in the context queue for
608 * transmission. Must always be called with the ochi->lock held to
609 * ensure proper generation handling and locking around packet queue
610 * manipulation. */
611static void
612at_context_setup_packet(struct at_context *ctx, struct list_head *list)
613{
614 struct fw_packet *packet;
615 struct fw_ohci *ohci = ctx->ohci;
616 int z, tcode;
617
618 packet = fw_packet(ctx->list.next);
619
620 memset(&ctx->d, 0, sizeof ctx->d);
621 if (packet->payload_length > 0) {
622 packet->payload_bus = dma_map_single(ohci->card.device,
623 packet->payload,
624 packet->payload_length,
625 DMA_TO_DEVICE);
Kristian Høgsberg82eff9d2007-02-06 14:49:40 -0500626 if (dma_mapping_error(packet->payload_bus)) {
Kristian Høgsberge5f49c32007-01-26 00:38:34 -0500627 complete_transmission(packet, RCODE_SEND_ERROR, list);
Kristian Høgsberged568912006-12-19 19:58:35 -0500628 return;
629 }
630
631 ctx->d.more.control =
632 cpu_to_le16(descriptor_output_more |
633 descriptor_key_immediate);
634 ctx->d.more.req_count = cpu_to_le16(packet->header_length);
635 ctx->d.more.res_count = cpu_to_le16(packet->timestamp);
636 ctx->d.last.control =
637 cpu_to_le16(descriptor_output_last |
638 descriptor_irq_always |
639 descriptor_branch_always);
640 ctx->d.last.req_count = cpu_to_le16(packet->payload_length);
641 ctx->d.last.data_address = cpu_to_le32(packet->payload_bus);
642 z = 3;
643 } else {
644 ctx->d.more.control =
645 cpu_to_le16(descriptor_output_last |
646 descriptor_key_immediate |
647 descriptor_irq_always |
648 descriptor_branch_always);
649 ctx->d.more.req_count = cpu_to_le16(packet->header_length);
650 ctx->d.more.res_count = cpu_to_le16(packet->timestamp);
651 z = 2;
652 }
653
654 /* The DMA format for asyncronous link packets is different
655 * from the IEEE1394 layout, so shift the fields around
656 * accordingly. If header_length is 8, it's a PHY packet, to
657 * which we need to prepend an extra quadlet. */
658 if (packet->header_length > 8) {
659 ctx->d.header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
660 (packet->speed << 16));
661 ctx->d.header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
662 (packet->header[0] & 0xffff0000));
663 ctx->d.header[2] = cpu_to_le32(packet->header[2]);
664
665 tcode = (packet->header[0] >> 4) & 0x0f;
666 if (TCODE_IS_BLOCK_PACKET(tcode))
667 ctx->d.header[3] = cpu_to_le32(packet->header[3]);
668 else
669 ctx->d.header[3] = packet->header[3];
670 } else {
671 ctx->d.header[0] =
672 cpu_to_le32((OHCI1394_phy_tcode << 4) |
673 (packet->speed << 16));
674 ctx->d.header[1] = cpu_to_le32(packet->header[0]);
675 ctx->d.header[2] = cpu_to_le32(packet->header[1]);
676 ctx->d.more.req_count = cpu_to_le16(12);
677 }
678
679 /* FIXME: Document how the locking works. */
680 if (ohci->generation == packet->generation) {
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500681 reg_write(ctx->ohci, command_ptr(ctx->regs),
Kristian Høgsberged568912006-12-19 19:58:35 -0500682 ctx->descriptor_bus | z);
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500683 reg_write(ctx->ohci, control_set(ctx->regs),
Kristian Høgsberged568912006-12-19 19:58:35 -0500684 CONTEXT_RUN | CONTEXT_WAKE);
Kristian Høgsberg730c32f2007-02-06 14:49:32 -0500685 ctx->current_packet = packet;
Kristian Høgsberged568912006-12-19 19:58:35 -0500686 } else {
687 /* We dont return error codes from this function; all
688 * transmission errors are reported through the
689 * callback. */
Kristian Høgsberge5f49c32007-01-26 00:38:34 -0500690 complete_transmission(packet, RCODE_GENERATION, list);
Kristian Høgsberged568912006-12-19 19:58:35 -0500691 }
692}
693
694static void at_context_stop(struct at_context *ctx)
695{
696 u32 reg;
697
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500698 reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN);
Kristian Høgsberged568912006-12-19 19:58:35 -0500699
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500700 reg = reg_read(ctx->ohci, control_set(ctx->regs));
Kristian Høgsberged568912006-12-19 19:58:35 -0500701 if (reg & CONTEXT_ACTIVE)
702 fw_notify("Tried to stop context, but it is still active "
703 "(0x%08x).\n", reg);
704}
705
706static void at_context_tasklet(unsigned long data)
707{
708 struct at_context *ctx = (struct at_context *)data;
709 struct fw_ohci *ohci = ctx->ohci;
710 struct fw_packet *packet;
711 LIST_HEAD(list);
712 unsigned long flags;
713 int evt;
714
715 spin_lock_irqsave(&ohci->lock, flags);
716
717 packet = fw_packet(ctx->list.next);
718
719 at_context_stop(ctx);
720
Kristian Høgsberg730c32f2007-02-06 14:49:32 -0500721 /* If the head of the list isn't the packet that just got
722 * transmitted, the packet got cancelled before we finished
723 * transmitting it. */
724 if (ctx->current_packet != packet)
725 goto skip_to_next;
726
Kristian Høgsberged568912006-12-19 19:58:35 -0500727 if (packet->payload_length > 0) {
728 dma_unmap_single(ohci->card.device, packet->payload_bus,
729 packet->payload_length, DMA_TO_DEVICE);
730 evt = le16_to_cpu(ctx->d.last.transfer_status) & 0x1f;
731 packet->timestamp = le16_to_cpu(ctx->d.last.res_count);
732 }
733 else {
734 evt = le16_to_cpu(ctx->d.more.transfer_status) & 0x1f;
735 packet->timestamp = le16_to_cpu(ctx->d.more.res_count);
736 }
737
738 if (evt < 16) {
739 switch (evt) {
740 case OHCI1394_evt_timeout:
741 /* Async response transmit timed out. */
Kristian Høgsberge5f49c32007-01-26 00:38:34 -0500742 complete_transmission(packet, RCODE_CANCELLED, &list);
Kristian Høgsberged568912006-12-19 19:58:35 -0500743 break;
744
745 case OHCI1394_evt_flushed:
746 /* The packet was flushed should give same
747 * error as when we try to use a stale
748 * generation count. */
Kristian Høgsberge5f49c32007-01-26 00:38:34 -0500749 complete_transmission(packet,
750 RCODE_GENERATION, &list);
Kristian Høgsberged568912006-12-19 19:58:35 -0500751 break;
752
753 case OHCI1394_evt_missing_ack:
Kristian Høgsberge5f49c32007-01-26 00:38:34 -0500754 /* Using a valid (current) generation count,
755 * but the node is not on the bus or not
756 * sending acks. */
757 complete_transmission(packet, RCODE_NO_ACK, &list);
Kristian Høgsberged568912006-12-19 19:58:35 -0500758 break;
759
760 default:
Kristian Høgsberge5f49c32007-01-26 00:38:34 -0500761 complete_transmission(packet, RCODE_SEND_ERROR, &list);
Kristian Høgsberged568912006-12-19 19:58:35 -0500762 break;
763 }
764 } else
765 complete_transmission(packet, evt - 16, &list);
766
Kristian Høgsberg730c32f2007-02-06 14:49:32 -0500767 skip_to_next:
Kristian Høgsberged568912006-12-19 19:58:35 -0500768 /* If more packets are queued, set up the next one. */
769 if (!list_empty(&ctx->list))
770 at_context_setup_packet(ctx, &list);
771
772 spin_unlock_irqrestore(&ohci->lock, flags);
773
774 do_packet_callbacks(ohci, &list);
775}
776
777static int
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500778at_context_init(struct at_context *ctx, struct fw_ohci *ohci, u32 regs)
Kristian Høgsberged568912006-12-19 19:58:35 -0500779{
780 INIT_LIST_HEAD(&ctx->list);
781
782 ctx->descriptor_bus =
783 dma_map_single(ohci->card.device, &ctx->d,
784 sizeof ctx->d, DMA_TO_DEVICE);
Kristian Høgsberg82eff9d2007-02-06 14:49:40 -0500785 if (dma_mapping_error(ctx->descriptor_bus))
Kristian Høgsberged568912006-12-19 19:58:35 -0500786 return -ENOMEM;
787
Kristian Høgsberg72e318e2007-02-06 14:49:31 -0500788 ctx->regs = regs;
789 ctx->ohci = ohci;
Kristian Høgsberged568912006-12-19 19:58:35 -0500790
791 tasklet_init(&ctx->tasklet, at_context_tasklet, (unsigned long)ctx);
792
793 return 0;
794}
795
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500796#define header_get_destination(q) (((q) >> 16) & 0xffff)
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500797#define header_get_tcode(q) (((q) >> 4) & 0x0f)
798#define header_get_offset_high(q) (((q) >> 0) & 0xffff)
799#define header_get_data_length(q) (((q) >> 16) & 0xffff)
800#define header_get_extended_tcode(q) (((q) >> 0) & 0xffff)
801
802static void
803handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
804{
805 struct fw_packet response;
806 int tcode, length, i;
807
808 tcode = header_get_tcode(packet->header[0]);
809 if (TCODE_IS_BLOCK_PACKET(tcode))
810 length = header_get_data_length(packet->header[3]);
811 else
812 length = 4;
813
814 i = csr - CSR_CONFIG_ROM;
815 if (i + length > CONFIG_ROM_SIZE) {
816 fw_fill_response(&response, packet->header,
817 RCODE_ADDRESS_ERROR, NULL, 0);
818 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
819 fw_fill_response(&response, packet->header,
820 RCODE_TYPE_ERROR, NULL, 0);
821 } else {
822 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
823 (void *) ohci->config_rom + i, length);
824 }
825
826 fw_core_handle_response(&ohci->card, &response);
827}
828
829static void
830handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
831{
832 struct fw_packet response;
833 int tcode, length, ext_tcode, sel;
834 __be32 *payload, lock_old;
835 u32 lock_arg, lock_data;
836
837 tcode = header_get_tcode(packet->header[0]);
838 length = header_get_data_length(packet->header[3]);
839 payload = packet->payload;
840 ext_tcode = header_get_extended_tcode(packet->header[3]);
841
842 if (tcode == TCODE_LOCK_REQUEST &&
843 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
844 lock_arg = be32_to_cpu(payload[0]);
845 lock_data = be32_to_cpu(payload[1]);
846 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
847 lock_arg = 0;
848 lock_data = 0;
849 } else {
850 fw_fill_response(&response, packet->header,
851 RCODE_TYPE_ERROR, NULL, 0);
852 goto out;
853 }
854
855 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
856 reg_write(ohci, OHCI1394_CSRData, lock_data);
857 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
858 reg_write(ohci, OHCI1394_CSRControl, sel);
859
860 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
861 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
862 else
863 fw_notify("swap not done yet\n");
864
865 fw_fill_response(&response, packet->header,
866 RCODE_COMPLETE, &lock_old, sizeof lock_old);
867 out:
868 fw_core_handle_response(&ohci->card, &response);
869}
870
871static void
872handle_local_request(struct at_context *ctx, struct fw_packet *packet)
873{
874 u64 offset;
875 u32 csr;
876
877 packet->ack = ACK_PENDING;
878 packet->callback(packet, &ctx->ohci->card, packet->ack);
879
880 offset =
881 ((unsigned long long)
882 header_get_offset_high(packet->header[1]) << 32) |
883 packet->header[2];
884 csr = offset - CSR_REGISTER_BASE;
885
886 /* Handle config rom reads. */
887 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
888 handle_local_rom(ctx->ohci, packet, csr);
889 else switch (csr) {
890 case CSR_BUS_MANAGER_ID:
891 case CSR_BANDWIDTH_AVAILABLE:
892 case CSR_CHANNELS_AVAILABLE_HI:
893 case CSR_CHANNELS_AVAILABLE_LO:
894 handle_local_lock(ctx->ohci, packet, csr);
895 break;
896 default:
897 if (ctx == &ctx->ohci->at_request_ctx)
898 fw_core_handle_request(&ctx->ohci->card, packet);
899 else
900 fw_core_handle_response(&ctx->ohci->card, packet);
901 break;
902 }
903}
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500904
Kristian Høgsberged568912006-12-19 19:58:35 -0500905static void
906at_context_transmit(struct at_context *ctx, struct fw_packet *packet)
907{
908 LIST_HEAD(list);
909 unsigned long flags;
Kristian Høgsberged568912006-12-19 19:58:35 -0500910
911 spin_lock_irqsave(&ctx->ohci->lock, flags);
912
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500913 if (header_get_destination(packet->header[0]) == ctx->ohci->node_id &&
914 ctx->ohci->generation == packet->generation) {
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500915 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
916 handle_local_request(ctx, packet);
917 return;
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500918 }
Kristian Høgsberged568912006-12-19 19:58:35 -0500919
Kristian Høgsberg93c4cce2007-01-26 00:38:26 -0500920 list_add_tail(&packet->link, &ctx->list);
921 if (ctx->list.next == &packet->link)
922 at_context_setup_packet(ctx, &list);
923
Kristian Høgsberged568912006-12-19 19:58:35 -0500924 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
925
926 do_packet_callbacks(ctx->ohci, &list);
927}
928
929static void bus_reset_tasklet(unsigned long data)
930{
931 struct fw_ohci *ohci = (struct fw_ohci *)data;
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500932 int self_id_count, i, j, reg;
Kristian Høgsberged568912006-12-19 19:58:35 -0500933 int generation, new_generation;
934 unsigned long flags;
935
936 reg = reg_read(ohci, OHCI1394_NodeID);
937 if (!(reg & OHCI1394_NodeID_idValid)) {
938 fw_error("node ID not valid, new bus reset in progress\n");
939 return;
940 }
Kristian Høgsberge636fe22007-01-26 00:38:04 -0500941 ohci->node_id = reg & 0xffff;
Kristian Høgsberged568912006-12-19 19:58:35 -0500942
943 /* The count in the SelfIDCount register is the number of
944 * bytes in the self ID receive buffer. Since we also receive
945 * the inverted quadlets and a header quadlet, we shift one
946 * bit extra to get the actual number of self IDs. */
947
948 self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
949 generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
950
951 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
952 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
953 fw_error("inconsistent self IDs\n");
954 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
955 }
956
957 /* Check the consistency of the self IDs we just read. The
958 * problem we face is that a new bus reset can start while we
959 * read out the self IDs from the DMA buffer. If this happens,
960 * the DMA buffer will be overwritten with new self IDs and we
961 * will read out inconsistent data. The OHCI specification
962 * (section 11.2) recommends a technique similar to
963 * linux/seqlock.h, where we remember the generation of the
964 * self IDs in the buffer before reading them out and compare
965 * it to the current generation after reading them out. If
966 * the two generations match we know we have a consistent set
967 * of self IDs. */
968
969 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
970 if (new_generation != generation) {
971 fw_notify("recursive bus reset detected, "
972 "discarding self ids\n");
973 return;
974 }
975
976 /* FIXME: Document how the locking works. */
977 spin_lock_irqsave(&ohci->lock, flags);
978
979 ohci->generation = generation;
980 at_context_stop(&ohci->at_request_ctx);
981 at_context_stop(&ohci->at_response_ctx);
982 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
983
984 /* This next bit is unrelated to the AT context stuff but we
985 * have to do it under the spinlock also. If a new config rom
986 * was set up before this reset, the old one is now no longer
987 * in use and we can free it. Update the config rom pointers
988 * to point to the current config rom and clear the
989 * next_config_rom pointer so a new udpate can take place. */
990
991 if (ohci->next_config_rom != NULL) {
992 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
993 ohci->config_rom, ohci->config_rom_bus);
994 ohci->config_rom = ohci->next_config_rom;
995 ohci->config_rom_bus = ohci->next_config_rom_bus;
996 ohci->next_config_rom = NULL;
997
998 /* Restore config_rom image and manually update
999 * config_rom registers. Writing the header quadlet
1000 * will indicate that the config rom is ready, so we
1001 * do that last. */
1002 reg_write(ohci, OHCI1394_BusOptions,
1003 be32_to_cpu(ohci->config_rom[2]));
1004 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1005 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1006 }
1007
1008 spin_unlock_irqrestore(&ohci->lock, flags);
1009
Kristian Høgsberge636fe22007-01-26 00:38:04 -05001010 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
Kristian Høgsberged568912006-12-19 19:58:35 -05001011 self_id_count, ohci->self_id_buffer);
1012}
1013
1014static irqreturn_t irq_handler(int irq, void *data)
1015{
1016 struct fw_ohci *ohci = data;
1017 u32 event, iso_event;
1018 int i;
1019
1020 event = reg_read(ohci, OHCI1394_IntEventClear);
1021
1022 if (!event)
1023 return IRQ_NONE;
1024
1025 reg_write(ohci, OHCI1394_IntEventClear, event);
1026
1027 if (event & OHCI1394_selfIDComplete)
1028 tasklet_schedule(&ohci->bus_reset_tasklet);
1029
1030 if (event & OHCI1394_RQPkt)
1031 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1032
1033 if (event & OHCI1394_RSPkt)
1034 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1035
1036 if (event & OHCI1394_reqTxComplete)
1037 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1038
1039 if (event & OHCI1394_respTxComplete)
1040 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1041
Kristian Høgsbergc8894752007-02-16 17:34:36 -05001042 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
Kristian Høgsberged568912006-12-19 19:58:35 -05001043 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1044
1045 while (iso_event) {
1046 i = ffs(iso_event) - 1;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001047 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001048 iso_event &= ~(1 << i);
1049 }
1050
Kristian Høgsbergc8894752007-02-16 17:34:36 -05001051 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
Kristian Høgsberged568912006-12-19 19:58:35 -05001052 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1053
1054 while (iso_event) {
1055 i = ffs(iso_event) - 1;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001056 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
Kristian Høgsberged568912006-12-19 19:58:35 -05001057 iso_event &= ~(1 << i);
1058 }
1059
1060 return IRQ_HANDLED;
1061}
1062
1063static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1064{
1065 struct fw_ohci *ohci = fw_ohci(card);
1066 struct pci_dev *dev = to_pci_dev(card->device);
1067
1068 /* When the link is not yet enabled, the atomic config rom
1069 * update mechanism described below in ohci_set_config_rom()
1070 * is not active. We have to update ConfigRomHeader and
1071 * BusOptions manually, and the write to ConfigROMmap takes
1072 * effect immediately. We tie this to the enabling of the
1073 * link, so we have a valid config rom before enabling - the
1074 * OHCI requires that ConfigROMhdr and BusOptions have valid
1075 * values before enabling.
1076 *
1077 * However, when the ConfigROMmap is written, some controllers
1078 * always read back quadlets 0 and 2 from the config rom to
1079 * the ConfigRomHeader and BusOptions registers on bus reset.
1080 * They shouldn't do that in this initial case where the link
1081 * isn't enabled. This means we have to use the same
1082 * workaround here, setting the bus header to 0 and then write
1083 * the right values in the bus reset tasklet.
1084 */
1085
1086 ohci->next_config_rom =
1087 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1088 &ohci->next_config_rom_bus, GFP_KERNEL);
1089 if (ohci->next_config_rom == NULL)
1090 return -ENOMEM;
1091
1092 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1093 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1094
1095 ohci->next_header = config_rom[0];
1096 ohci->next_config_rom[0] = 0;
1097 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1098 reg_write(ohci, OHCI1394_BusOptions, config_rom[2]);
1099 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1100
1101 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1102
1103 if (request_irq(dev->irq, irq_handler,
1104 SA_SHIRQ, ohci_driver_name, ohci)) {
1105 fw_error("Failed to allocate shared interrupt %d.\n",
1106 dev->irq);
1107 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1108 ohci->config_rom, ohci->config_rom_bus);
1109 return -EIO;
1110 }
1111
1112 reg_write(ohci, OHCI1394_HCControlSet,
1113 OHCI1394_HCControl_linkEnable |
1114 OHCI1394_HCControl_BIBimageValid);
1115 flush_writes(ohci);
1116
1117 /* We are ready to go, initiate bus reset to finish the
1118 * initialization. */
1119
1120 fw_core_initiate_bus_reset(&ohci->card, 1);
1121
1122 return 0;
1123}
1124
1125static int
1126ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1127{
1128 struct fw_ohci *ohci;
1129 unsigned long flags;
1130 int retval = 0;
1131 __be32 *next_config_rom;
1132 dma_addr_t next_config_rom_bus;
1133
1134 ohci = fw_ohci(card);
1135
1136 /* When the OHCI controller is enabled, the config rom update
1137 * mechanism is a bit tricky, but easy enough to use. See
1138 * section 5.5.6 in the OHCI specification.
1139 *
1140 * The OHCI controller caches the new config rom address in a
1141 * shadow register (ConfigROMmapNext) and needs a bus reset
1142 * for the changes to take place. When the bus reset is
1143 * detected, the controller loads the new values for the
1144 * ConfigRomHeader and BusOptions registers from the specified
1145 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1146 * shadow register. All automatically and atomically.
1147 *
1148 * Now, there's a twist to this story. The automatic load of
1149 * ConfigRomHeader and BusOptions doesn't honor the
1150 * noByteSwapData bit, so with a be32 config rom, the
1151 * controller will load be32 values in to these registers
1152 * during the atomic update, even on litte endian
1153 * architectures. The workaround we use is to put a 0 in the
1154 * header quadlet; 0 is endian agnostic and means that the
1155 * config rom isn't ready yet. In the bus reset tasklet we
1156 * then set up the real values for the two registers.
1157 *
1158 * We use ohci->lock to avoid racing with the code that sets
1159 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1160 */
1161
1162 next_config_rom =
1163 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1164 &next_config_rom_bus, GFP_KERNEL);
1165 if (next_config_rom == NULL)
1166 return -ENOMEM;
1167
1168 spin_lock_irqsave(&ohci->lock, flags);
1169
1170 if (ohci->next_config_rom == NULL) {
1171 ohci->next_config_rom = next_config_rom;
1172 ohci->next_config_rom_bus = next_config_rom_bus;
1173
1174 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1175 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1176 length * 4);
1177
1178 ohci->next_header = config_rom[0];
1179 ohci->next_config_rom[0] = 0;
1180
1181 reg_write(ohci, OHCI1394_ConfigROMmap,
1182 ohci->next_config_rom_bus);
1183 } else {
1184 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1185 next_config_rom, next_config_rom_bus);
1186 retval = -EBUSY;
1187 }
1188
1189 spin_unlock_irqrestore(&ohci->lock, flags);
1190
1191 /* Now initiate a bus reset to have the changes take
1192 * effect. We clean up the old config rom memory and DMA
1193 * mappings in the bus reset tasklet, since the OHCI
1194 * controller could need to access it before the bus reset
1195 * takes effect. */
1196 if (retval == 0)
1197 fw_core_initiate_bus_reset(&ohci->card, 1);
1198
1199 return retval;
1200}
1201
1202static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1203{
1204 struct fw_ohci *ohci = fw_ohci(card);
1205
1206 at_context_transmit(&ohci->at_request_ctx, packet);
1207}
1208
1209static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1210{
1211 struct fw_ohci *ohci = fw_ohci(card);
1212
1213 at_context_transmit(&ohci->at_response_ctx, packet);
1214}
1215
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001216static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1217{
1218 struct fw_ohci *ohci = fw_ohci(card);
1219 LIST_HEAD(list);
1220 unsigned long flags;
1221
1222 spin_lock_irqsave(&ohci->lock, flags);
1223
1224 if (packet->ack == 0) {
1225 fw_notify("cancelling packet %p (header[0]=%08x)\n",
1226 packet, packet->header[0]);
1227
1228 complete_transmission(packet, RCODE_CANCELLED, &list);
1229 }
1230
1231 spin_unlock_irqrestore(&ohci->lock, flags);
1232
1233 do_packet_callbacks(ohci, &list);
1234
1235 /* Return success if we actually cancelled something. */
1236 return list_empty(&list) ? -ENOENT : 0;
1237}
1238
Kristian Høgsberged568912006-12-19 19:58:35 -05001239static int
1240ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1241{
1242 struct fw_ohci *ohci = fw_ohci(card);
1243 unsigned long flags;
Stefan Richter907293d2007-01-23 21:11:43 +01001244 int n, retval = 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001245
Stefan Richter907293d2007-01-23 21:11:43 +01001246 /* FIXME: Make sure this bitmask is cleared when we clear the busReset
1247 * interrupt bit. Clear physReqResourceAllBuses on bus reset. */
Kristian Høgsberged568912006-12-19 19:58:35 -05001248
1249 spin_lock_irqsave(&ohci->lock, flags);
1250
1251 if (ohci->generation != generation) {
1252 retval = -ESTALE;
1253 goto out;
1254 }
1255
Stefan Richter907293d2007-01-23 21:11:43 +01001256 /* NOTE, if the node ID contains a non-local bus ID, physical DMA is
1257 * enabled for _all_ nodes on remote buses. */
1258
1259 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1260 if (n < 32)
1261 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1262 else
1263 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1264
Kristian Høgsberged568912006-12-19 19:58:35 -05001265 flush_writes(ohci);
Kristian Høgsberged568912006-12-19 19:58:35 -05001266 out:
Stefan Richter6cad95f2007-01-21 20:46:45 +01001267 spin_unlock_irqrestore(&ohci->lock, flags);
Kristian Høgsberged568912006-12-19 19:58:35 -05001268 return retval;
1269}
1270
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001271static int handle_ir_packet(struct context *context,
1272 struct descriptor *d,
1273 struct descriptor *last)
Kristian Høgsberged568912006-12-19 19:58:35 -05001274{
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001275 struct iso_context *ctx =
1276 container_of(context, struct iso_context, context);
1277 struct db_descriptor *db = (struct db_descriptor *) d;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001278 size_t header_length;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001279
1280 if (db->first_res_count > 0 && db->second_res_count > 0)
1281 /* This descriptor isn't done yet, stop iteration. */
1282 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001283
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001284 header_length = db->first_req_count - db->first_res_count;
1285 if (ctx->header_length + header_length <= PAGE_SIZE)
1286 memcpy(ctx->header + ctx->header_length, db + 1, header_length);
1287 ctx->header_length += header_length;
1288
1289 if (le16_to_cpu(db->control) & descriptor_irq_always) {
1290 ctx->base.callback(&ctx->base, 0,
1291 ctx->header_length, ctx->header,
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001292 ctx->base.callback_data);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001293 ctx->header_length = 0;
1294 }
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001295
1296 return 1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001297}
1298
1299#define ISO_BUFFER_SIZE (64 * 1024)
1300
Kristian Høgsberg30200732007-02-16 17:34:39 -05001301static int handle_it_packet(struct context *context,
1302 struct descriptor *d,
1303 struct descriptor *last)
Kristian Høgsberged568912006-12-19 19:58:35 -05001304{
Kristian Høgsberg30200732007-02-16 17:34:39 -05001305 struct iso_context *ctx =
1306 container_of(context, struct iso_context, context);
1307
1308 if (last->transfer_status == 0)
1309 /* This descriptor isn't done yet, stop iteration. */
1310 return 0;
Kristian Høgsberged568912006-12-19 19:58:35 -05001311
Kristian Høgsberg30200732007-02-16 17:34:39 -05001312 if (le16_to_cpu(last->control) & descriptor_irq_always)
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001313 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1314 0, NULL, ctx->base.callback_data);
Kristian Høgsberged568912006-12-19 19:58:35 -05001315
Kristian Høgsberg30200732007-02-16 17:34:39 -05001316 return 1;
Kristian Høgsberged568912006-12-19 19:58:35 -05001317}
1318
Kristian Høgsberg30200732007-02-16 17:34:39 -05001319static struct fw_iso_context *
1320ohci_allocate_iso_context(struct fw_card *card, int type)
Kristian Høgsberged568912006-12-19 19:58:35 -05001321{
1322 struct fw_ohci *ohci = fw_ohci(card);
1323 struct iso_context *ctx, *list;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001324 descriptor_callback_t callback;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001325 u32 *mask, regs;
Kristian Høgsberged568912006-12-19 19:58:35 -05001326 unsigned long flags;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001327 int index, retval = -ENOMEM;
Kristian Høgsberged568912006-12-19 19:58:35 -05001328
1329 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1330 mask = &ohci->it_context_mask;
1331 list = ohci->it_context_list;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001332 callback = handle_it_packet;
Kristian Høgsberged568912006-12-19 19:58:35 -05001333 } else {
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001334 mask = &ohci->ir_context_mask;
1335 list = ohci->ir_context_list;
1336 callback = handle_ir_packet;
Kristian Høgsberged568912006-12-19 19:58:35 -05001337 }
1338
1339 spin_lock_irqsave(&ohci->lock, flags);
1340 index = ffs(*mask) - 1;
1341 if (index >= 0)
1342 *mask &= ~(1 << index);
1343 spin_unlock_irqrestore(&ohci->lock, flags);
1344
1345 if (index < 0)
1346 return ERR_PTR(-EBUSY);
1347
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001348 if (type == FW_ISO_CONTEXT_TRANSMIT)
1349 regs = OHCI1394_IsoXmitContextBase(index);
1350 else
1351 regs = OHCI1394_IsoRcvContextBase(index);
1352
Kristian Høgsberged568912006-12-19 19:58:35 -05001353 ctx = &list[index];
1354 memset(ctx, 0, sizeof *ctx);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001355 ctx->header_length = 0;
1356 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1357 if (ctx->header == NULL)
1358 goto out;
1359
Kristian Høgsberg30200732007-02-16 17:34:39 -05001360 retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE,
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001361 regs, callback);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001362 if (retval < 0)
1363 goto out_with_header;
Kristian Høgsberged568912006-12-19 19:58:35 -05001364
1365 return &ctx->base;
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001366
1367 out_with_header:
1368 free_page((unsigned long)ctx->header);
1369 out:
1370 spin_lock_irqsave(&ohci->lock, flags);
1371 *mask |= 1 << index;
1372 spin_unlock_irqrestore(&ohci->lock, flags);
1373
1374 return ERR_PTR(retval);
Kristian Høgsberged568912006-12-19 19:58:35 -05001375}
1376
Kristian Høgsberg69cdb722007-02-16 17:34:41 -05001377static int ohci_start_iso(struct fw_iso_context *base, s32 cycle)
Kristian Høgsberged568912006-12-19 19:58:35 -05001378{
Kristian Høgsberg30200732007-02-16 17:34:39 -05001379 struct iso_context *ctx = container_of(base, struct iso_context, base);
1380 struct fw_ohci *ohci = ctx->context.ohci;
Kristian Høgsberged568912006-12-19 19:58:35 -05001381 u32 cycle_match = 0;
1382 int index;
1383
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001384 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1385 index = ctx - ohci->it_context_list;
1386 if (cycle > 0)
1387 cycle_match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1388 (cycle & 0x7fff) << 16;
1389
1390 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1391 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1392 context_run(&ctx->context, cycle_match);
1393 } else {
1394 index = ctx - ohci->ir_context_list;
Kristian Høgsberged568912006-12-19 19:58:35 -05001395
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001396 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1397 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1398 reg_write(ohci, context_match(ctx->context.regs),
1399 0xf0000000 | ctx->base.channel);
1400 context_run(&ctx->context, IR_CONTEXT_DUAL_BUFFER_MODE);
1401 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001402
1403 return 0;
1404}
1405
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001406static int ohci_stop_iso(struct fw_iso_context *base)
1407{
1408 struct fw_ohci *ohci = fw_ohci(base->card);
1409 struct iso_context *ctx = container_of(base, struct iso_context, base);
1410 int index;
1411
1412 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1413 index = ctx - ohci->it_context_list;
1414 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1415 } else {
1416 index = ctx - ohci->ir_context_list;
1417 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1418 }
1419 flush_writes(ohci);
1420 context_stop(&ctx->context);
1421
1422 return 0;
1423}
1424
Kristian Høgsberged568912006-12-19 19:58:35 -05001425static void ohci_free_iso_context(struct fw_iso_context *base)
1426{
1427 struct fw_ohci *ohci = fw_ohci(base->card);
Kristian Høgsberg30200732007-02-16 17:34:39 -05001428 struct iso_context *ctx = container_of(base, struct iso_context, base);
Kristian Høgsberged568912006-12-19 19:58:35 -05001429 unsigned long flags;
1430 int index;
1431
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001432 ohci_stop_iso(base);
1433 context_release(&ctx->context);
Kristian Høgsberg9b32d5f2007-02-16 17:34:44 -05001434 free_page((unsigned long)ctx->header);
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001435
Kristian Høgsberged568912006-12-19 19:58:35 -05001436 spin_lock_irqsave(&ohci->lock, flags);
1437
1438 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1439 index = ctx - ohci->it_context_list;
Kristian Høgsberged568912006-12-19 19:58:35 -05001440 ohci->it_context_mask |= 1 << index;
1441 } else {
1442 index = ctx - ohci->ir_context_list;
Kristian Høgsberged568912006-12-19 19:58:35 -05001443 ohci->ir_context_mask |= 1 << index;
1444 }
Kristian Høgsberged568912006-12-19 19:58:35 -05001445
1446 spin_unlock_irqrestore(&ohci->lock, flags);
1447}
1448
1449static int
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001450ohci_queue_iso_transmit(struct fw_iso_context *base,
1451 struct fw_iso_packet *packet,
1452 struct fw_iso_buffer *buffer,
1453 unsigned long payload)
Kristian Høgsberged568912006-12-19 19:58:35 -05001454{
Kristian Høgsberg30200732007-02-16 17:34:39 -05001455 struct iso_context *ctx = container_of(base, struct iso_context, base);
1456 struct descriptor *d, *last, *pd;
Kristian Høgsberged568912006-12-19 19:58:35 -05001457 struct fw_iso_packet *p;
1458 __le32 *header;
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05001459 dma_addr_t d_bus, page_bus;
Kristian Høgsberged568912006-12-19 19:58:35 -05001460 u32 z, header_z, payload_z, irq;
1461 u32 payload_index, payload_end_index, next_page_index;
Kristian Høgsberg30200732007-02-16 17:34:39 -05001462 int page, end_page, i, length, offset;
Kristian Høgsberged568912006-12-19 19:58:35 -05001463
1464 /* FIXME: Cycle lost behavior should be configurable: lose
1465 * packet, retransmit or terminate.. */
1466
1467 p = packet;
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05001468 payload_index = payload;
Kristian Høgsberged568912006-12-19 19:58:35 -05001469
1470 if (p->skip)
1471 z = 1;
1472 else
1473 z = 2;
1474 if (p->header_length > 0)
1475 z++;
1476
1477 /* Determine the first page the payload isn't contained in. */
1478 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1479 if (p->payload_length > 0)
1480 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1481 else
1482 payload_z = 0;
1483
1484 z += payload_z;
1485
1486 /* Get header size in number of descriptors. */
1487 header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
1488
Kristian Høgsberg30200732007-02-16 17:34:39 -05001489 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1490 if (d == NULL)
1491 return -ENOMEM;
Kristian Høgsberged568912006-12-19 19:58:35 -05001492
1493 if (!p->skip) {
1494 d[0].control = cpu_to_le16(descriptor_key_immediate);
1495 d[0].req_count = cpu_to_le16(8);
1496
1497 header = (__le32 *) &d[1];
1498 header[0] = cpu_to_le32(it_header_sy(p->sy) |
1499 it_header_tag(p->tag) |
1500 it_header_tcode(TCODE_STREAM_DATA) |
1501 it_header_channel(ctx->base.channel) |
1502 it_header_speed(ctx->base.speed));
1503 header[1] =
1504 cpu_to_le32(it_header_data_length(p->header_length +
1505 p->payload_length));
1506 }
1507
1508 if (p->header_length > 0) {
1509 d[2].req_count = cpu_to_le16(p->header_length);
1510 d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d);
1511 memcpy(&d[z], p->header, p->header_length);
1512 }
1513
1514 pd = d + z - payload_z;
1515 payload_end_index = payload_index + p->payload_length;
1516 for (i = 0; i < payload_z; i++) {
1517 page = payload_index >> PAGE_SHIFT;
1518 offset = payload_index & ~PAGE_MASK;
1519 next_page_index = (page + 1) << PAGE_SHIFT;
1520 length =
1521 min(next_page_index, payload_end_index) - payload_index;
1522 pd[i].req_count = cpu_to_le16(length);
Kristian Høgsberg9aad8122007-02-16 17:34:38 -05001523
1524 page_bus = page_private(buffer->pages[page]);
1525 pd[i].data_address = cpu_to_le32(page_bus + offset);
Kristian Høgsberged568912006-12-19 19:58:35 -05001526
1527 payload_index += length;
1528 }
1529
Kristian Høgsberged568912006-12-19 19:58:35 -05001530 if (p->interrupt)
1531 irq = descriptor_irq_always;
1532 else
1533 irq = descriptor_no_irq;
1534
Kristian Høgsberg30200732007-02-16 17:34:39 -05001535 last = z == 2 ? d : d + z - 1;
Kristian Høgsbergcbb59da2007-02-16 17:34:35 -05001536 last->control |= cpu_to_le16(descriptor_output_last |
1537 descriptor_status |
1538 descriptor_branch_always |
1539 irq);
Kristian Høgsberged568912006-12-19 19:58:35 -05001540
Kristian Høgsberg30200732007-02-16 17:34:39 -05001541 context_append(&ctx->context, d, z, header_z);
Kristian Høgsberged568912006-12-19 19:58:35 -05001542
1543 return 0;
1544}
1545
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001546static int
1547ohci_queue_iso_receive(struct fw_iso_context *base,
1548 struct fw_iso_packet *packet,
1549 struct fw_iso_buffer *buffer,
1550 unsigned long payload)
1551{
1552 struct iso_context *ctx = container_of(base, struct iso_context, base);
1553 struct db_descriptor *db = NULL;
1554 struct descriptor *d;
1555 struct fw_iso_packet *p;
1556 dma_addr_t d_bus, page_bus;
1557 u32 z, header_z, length, rest;
1558 int page, offset;
1559
1560 /* FIXME: Cycle lost behavior should be configurable: lose
1561 * packet, retransmit or terminate.. */
1562
1563 p = packet;
1564 z = 2;
1565
1566 /* Get header size in number of descriptors. */
1567 header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
1568 page = payload >> PAGE_SHIFT;
1569 offset = payload & ~PAGE_MASK;
1570 rest = p->payload_length;
1571
1572 /* FIXME: OHCI 1.0 doesn't support dual buffer receive */
1573 /* FIXME: handle descriptor_wait */
1574 /* FIXME: make packet-per-buffer/dual-buffer a context option */
1575 while (rest > 0) {
1576 d = context_get_descriptors(&ctx->context,
1577 z + header_z, &d_bus);
1578 if (d == NULL)
1579 return -ENOMEM;
1580
1581 db = (struct db_descriptor *) d;
1582 db->control = cpu_to_le16(descriptor_status |
1583 descriptor_branch_always);
1584 db->first_size = cpu_to_le16(ctx->base.header_size);
1585 db->first_req_count = cpu_to_le16(p->header_length);
Kristian Høgsberg1e1d1962007-02-16 17:34:45 -05001586 db->first_res_count = db->first_req_count;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001587 db->first_buffer = cpu_to_le32(d_bus + sizeof *db);
1588
1589 if (offset + rest < PAGE_SIZE)
1590 length = rest;
1591 else
1592 length = PAGE_SIZE - offset;
1593
Kristian Høgsberg1e1d1962007-02-16 17:34:45 -05001594 db->second_req_count = cpu_to_le16(length);
1595 db->second_res_count = db->second_req_count;
Kristian Høgsberg295e3fe2007-02-16 17:34:40 -05001596 page_bus = page_private(buffer->pages[page]);
1597 db->second_buffer = cpu_to_le32(page_bus + offset);
1598
1599 context_append(&ctx->context, d, z, header_z);
1600 offset = (offset + length) & ~PAGE_MASK;
1601 rest -= length;
1602 page++;
1603 }
1604
1605 if (p->interrupt)
1606 db->control |= cpu_to_le16(descriptor_irq_always);
1607
1608 return 0;
1609 }
1610
1611static int
1612ohci_queue_iso(struct fw_iso_context *base,
1613 struct fw_iso_packet *packet,
1614 struct fw_iso_buffer *buffer,
1615 unsigned long payload)
1616{
1617 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
1618 return ohci_queue_iso_transmit(base, packet, buffer, payload);
1619 else
1620 return ohci_queue_iso_receive(base, packet, buffer, payload);
1621}
1622
Stefan Richter21ebcd12007-01-14 15:29:07 +01001623static const struct fw_card_driver ohci_driver = {
Kristian Høgsberged568912006-12-19 19:58:35 -05001624 .name = ohci_driver_name,
1625 .enable = ohci_enable,
1626 .update_phy_reg = ohci_update_phy_reg,
1627 .set_config_rom = ohci_set_config_rom,
1628 .send_request = ohci_send_request,
1629 .send_response = ohci_send_response,
Kristian Høgsberg730c32f2007-02-06 14:49:32 -05001630 .cancel_packet = ohci_cancel_packet,
Kristian Høgsberged568912006-12-19 19:58:35 -05001631 .enable_phys_dma = ohci_enable_phys_dma,
1632
1633 .allocate_iso_context = ohci_allocate_iso_context,
1634 .free_iso_context = ohci_free_iso_context,
1635 .queue_iso = ohci_queue_iso,
Kristian Høgsberg69cdb722007-02-16 17:34:41 -05001636 .start_iso = ohci_start_iso,
Kristian Høgsbergb8295662007-02-16 17:34:42 -05001637 .stop_iso = ohci_stop_iso,
Kristian Høgsberged568912006-12-19 19:58:35 -05001638};
1639
1640static int software_reset(struct fw_ohci *ohci)
1641{
1642 int i;
1643
1644 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1645
1646 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1647 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1648 OHCI1394_HCControl_softReset) == 0)
1649 return 0;
1650 msleep(1);
1651 }
1652
1653 return -EBUSY;
1654}
1655
1656/* ---------- pci subsystem interface ---------- */
1657
1658enum {
1659 CLEANUP_SELF_ID,
1660 CLEANUP_REGISTERS,
1661 CLEANUP_IOMEM,
1662 CLEANUP_DISABLE,
1663 CLEANUP_PUT_CARD,
1664};
1665
1666static int cleanup(struct fw_ohci *ohci, int stage, int code)
1667{
1668 struct pci_dev *dev = to_pci_dev(ohci->card.device);
1669
1670 switch (stage) {
1671 case CLEANUP_SELF_ID:
1672 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1673 ohci->self_id_cpu, ohci->self_id_bus);
1674 case CLEANUP_REGISTERS:
1675 kfree(ohci->it_context_list);
1676 kfree(ohci->ir_context_list);
1677 pci_iounmap(dev, ohci->registers);
1678 case CLEANUP_IOMEM:
1679 pci_release_region(dev, 0);
1680 case CLEANUP_DISABLE:
1681 pci_disable_device(dev);
1682 case CLEANUP_PUT_CARD:
1683 fw_card_put(&ohci->card);
1684 }
1685
1686 return code;
1687}
1688
1689static int __devinit
1690pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1691{
1692 struct fw_ohci *ohci;
Kristian Høgsberg500be722007-02-16 17:34:43 -05001693 u32 bus_options, max_receive, link_speed, version;
Kristian Høgsberged568912006-12-19 19:58:35 -05001694 u64 guid;
1695 int error_code;
1696 size_t size;
1697
1698 ohci = kzalloc(sizeof *ohci, GFP_KERNEL);
1699 if (ohci == NULL) {
1700 fw_error("Could not malloc fw_ohci data.\n");
1701 return -ENOMEM;
1702 }
1703
1704 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1705
1706 if (pci_enable_device(dev)) {
1707 fw_error("Failed to enable OHCI hardware.\n");
1708 return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV);
1709 }
1710
1711 pci_set_master(dev);
1712 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1713 pci_set_drvdata(dev, ohci);
1714
1715 spin_lock_init(&ohci->lock);
1716
1717 tasklet_init(&ohci->bus_reset_tasklet,
1718 bus_reset_tasklet, (unsigned long)ohci);
1719
1720 if (pci_request_region(dev, 0, ohci_driver_name)) {
1721 fw_error("MMIO resource unavailable\n");
1722 return cleanup(ohci, CLEANUP_DISABLE, -EBUSY);
1723 }
1724
1725 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1726 if (ohci->registers == NULL) {
1727 fw_error("Failed to remap registers\n");
1728 return cleanup(ohci, CLEANUP_IOMEM, -ENXIO);
1729 }
1730
1731 if (software_reset(ohci)) {
1732 fw_error("Failed to reset ohci card.\n");
1733 return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY);
1734 }
1735
1736 /* Now enable LPS, which we need in order to start accessing
1737 * most of the registers. In fact, on some cards (ALI M5251),
1738 * accessing registers in the SClk domain without LPS enabled
1739 * will lock up the machine. Wait 50msec to make sure we have
1740 * full link enabled. */
1741 reg_write(ohci, OHCI1394_HCControlSet,
1742 OHCI1394_HCControl_LPS |
1743 OHCI1394_HCControl_postedWriteEnable);
1744 flush_writes(ohci);
1745 msleep(50);
1746
1747 reg_write(ohci, OHCI1394_HCControlClear,
1748 OHCI1394_HCControl_noByteSwapData);
1749
1750 reg_write(ohci, OHCI1394_LinkControlSet,
1751 OHCI1394_LinkControl_rcvSelfID |
1752 OHCI1394_LinkControl_cycleTimerEnable |
1753 OHCI1394_LinkControl_cycleMaster);
1754
1755 ar_context_init(&ohci->ar_request_ctx, ohci,
1756 OHCI1394_AsReqRcvContextControlSet);
1757
1758 ar_context_init(&ohci->ar_response_ctx, ohci,
1759 OHCI1394_AsRspRcvContextControlSet);
1760
1761 at_context_init(&ohci->at_request_ctx, ohci,
1762 OHCI1394_AsReqTrContextControlSet);
1763
1764 at_context_init(&ohci->at_response_ctx, ohci,
1765 OHCI1394_AsRspTrContextControlSet);
1766
1767 reg_write(ohci, OHCI1394_ATRetries,
1768 OHCI1394_MAX_AT_REQ_RETRIES |
1769 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1770 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1771
1772 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
1773 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
1774 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
1775 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
1776 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
1777
1778 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
1779 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
1780 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
1781 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
1782 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
1783
1784 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
1785 fw_error("Out of memory for it/ir contexts.\n");
1786 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1787 }
1788
1789 /* self-id dma buffer allocation */
1790 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
1791 SELF_ID_BUF_SIZE,
1792 &ohci->self_id_bus,
1793 GFP_KERNEL);
1794 if (ohci->self_id_cpu == NULL) {
1795 fw_error("Out of memory for self ID buffer.\n");
1796 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1797 }
1798
1799 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1800 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1801 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1802 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1803 reg_write(ohci, OHCI1394_IntMaskSet,
1804 OHCI1394_selfIDComplete |
1805 OHCI1394_RQPkt | OHCI1394_RSPkt |
1806 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1807 OHCI1394_isochRx | OHCI1394_isochTx |
1808 OHCI1394_masterIntEnable);
1809
1810 bus_options = reg_read(ohci, OHCI1394_BusOptions);
1811 max_receive = (bus_options >> 12) & 0xf;
1812 link_speed = bus_options & 0x7;
1813 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
1814 reg_read(ohci, OHCI1394_GUIDLo);
1815
1816 error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid);
1817 if (error_code < 0)
1818 return cleanup(ohci, CLEANUP_SELF_ID, error_code);
1819
Kristian Høgsberg500be722007-02-16 17:34:43 -05001820 version = reg_read(ohci, OHCI1394_Version);
1821 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
1822 dev->dev.bus_id, (version >> 16) & 0xff, version & 0xff);
Kristian Høgsberged568912006-12-19 19:58:35 -05001823
1824 return 0;
1825}
1826
1827static void pci_remove(struct pci_dev *dev)
1828{
1829 struct fw_ohci *ohci;
1830
1831 ohci = pci_get_drvdata(dev);
1832 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_masterIntEnable);
1833 fw_core_remove_card(&ohci->card);
1834
1835 /* FIXME: Fail all pending packets here, now that the upper
1836 * layers can't queue any more. */
1837
1838 software_reset(ohci);
1839 free_irq(dev->irq, ohci);
1840 cleanup(ohci, CLEANUP_SELF_ID, 0);
1841
1842 fw_notify("Removed fw-ohci device.\n");
1843}
1844
1845static struct pci_device_id pci_table[] = {
1846 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
1847 { }
1848};
1849
1850MODULE_DEVICE_TABLE(pci, pci_table);
1851
1852static struct pci_driver fw_ohci_pci_driver = {
1853 .name = ohci_driver_name,
1854 .id_table = pci_table,
1855 .probe = pci_probe,
1856 .remove = pci_remove,
1857};
1858
1859MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1860MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1861MODULE_LICENSE("GPL");
1862
1863static int __init fw_ohci_init(void)
1864{
1865 return pci_register_driver(&fw_ohci_pci_driver);
1866}
1867
1868static void __exit fw_ohci_cleanup(void)
1869{
1870 pci_unregister_driver(&fw_ohci_pci_driver);
1871}
1872
1873module_init(fw_ohci_init);
1874module_exit(fw_ohci_cleanup);