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Sascha Hauer8c25c362009-06-04 11:32:12 +02001#ifndef __MACH_MX25_H__
2#define __MACH_MX25_H__
3
Uwe Kleine-Königc8e5db02009-11-12 21:51:55 +01004#define MX25_AIPS1_BASE_ADDR 0x43f00000
Sascha Hauer8c25c362009-06-04 11:32:12 +02005#define MX25_AIPS1_SIZE SZ_1M
Uwe Kleine-Königc8e5db02009-11-12 21:51:55 +01006#define MX25_AIPS2_BASE_ADDR 0x53f00000
Sascha Hauer8c25c362009-06-04 11:32:12 +02007#define MX25_AIPS2_SIZE SZ_1M
8#define MX25_AVIC_BASE_ADDR 0x68000000
Sascha Hauer8c25c362009-06-04 11:32:12 +02009#define MX25_AVIC_SIZE SZ_1M
10
Uwe Kleine-Königa8ff0452010-06-16 14:55:07 +020011#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
12#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
Marc Kleine-Buddec3f6a342010-07-22 11:41:56 +020013#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
14#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
Uwe Kleine-Königa8ff0452010-06-16 14:55:07 +020015#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
Uwe Kleine-König63ddc5b2010-06-21 17:34:58 +020016#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
Sascha Hauer8c25c362009-06-04 11:32:12 +020017#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
18
19#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
20#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
Uwe Kleine-Königcf3a6ab2010-10-25 15:54:58 +020021#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
Uwe Kleine-König5f3d1092010-11-10 22:15:45 +010022#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
Uwe Kleine-Königcf3a6ab2010-10-25 15:54:58 +020023#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
Uwe Kleine-König5f3d1092010-11-10 22:15:45 +010024#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
25#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
Uwe Kleine-Königcf3a6ab2010-10-25 15:54:58 +020026#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
27#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
Sascha Hauer8c25c362009-06-04 11:32:12 +020028#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
Uwe Kleine-König5f3d1092010-11-10 22:15:45 +010029#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
Sascha Hauer8c25c362009-06-04 11:32:12 +020030
Uwe Kleine-König66ac2f22010-01-25 17:55:16 +010031#define MX25_UART1_BASE_ADDR 0x43f90000
32#define MX25_UART2_BASE_ADDR 0x43f94000
Eric Bénard8402ed32010-06-08 11:03:00 +020033#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
Uwe Kleine-König7cc3c842010-06-24 15:20:44 +020034#define MX25_UART3_BASE_ADDR 0x5000c000
35#define MX25_UART4_BASE_ADDR 0x50008000
36#define MX25_UART5_BASE_ADDR 0x5002c000
Sascha Hauer8c25c362009-06-04 11:32:12 +020037
Uwe Kleine-König63ddc5b2010-06-21 17:34:58 +020038#define MX25_CSPI3_BASE_ADDR 0x50004000
39#define MX25_CSPI2_BASE_ADDR 0x50010000
Baruch Siacha7595442009-12-21 13:44:31 +020040#define MX25_FEC_BASE_ADDR 0x50038000
Eric Bénard8402ed32010-06-08 11:03:00 +020041#define MX25_SSI2_BASE_ADDR 0x50014000
42#define MX25_SSI1_BASE_ADDR 0x50034000
Baruch Siach27f59022010-01-14 11:24:14 +020043#define MX25_NFC_BASE_ADDR 0xbb000000
Jason Liu6132ae82011-08-29 21:13:44 +080044#define MX25_IIM_BASE_ADDR 0x53ff0000
Baruch Siachdcbabbc2010-01-27 15:00:48 +020045#define MX25_DRYICE_BASE_ADDR 0x53ffc000
Eric Bénardf5e40c22010-10-02 17:15:28 +020046#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
47#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
Baruch Siach04a03e52010-02-17 12:33:24 +020048#define MX25_LCDC_BASE_ADDR 0x53fbc000
Baruch Siach49535a92010-05-26 15:12:10 +030049#define MX25_KPP_BASE_ADDR 0x43fa8000
Eric Bénardec4aac22010-10-12 14:08:42 +020050#define MX25_SDMA_BASE_ADDR 0x53fd4000
Uwe Kleine-König2c20b9f2010-11-10 21:27:55 +010051#define MX25_USB_BASE_ADDR 0x53ff4000
52#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
Uwe Kleine-König4c6c32b2010-11-29 08:58:14 +010053/*
54 * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
55 * for the host controller. Early documentation drafts specified 0x400 and
56 * Freescale internal sources confirm only the latter value to work.
57 */
58#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
Baruch Siachf7478472010-06-21 08:16:00 +030059#define MX25_CSI_BASE_ADDR 0x53ff8000
Baruch Siacha7595442009-12-21 13:44:31 +020060
Uwe Kleine-Königa9963142010-10-25 15:44:25 +020061#define MX25_IO_P2V(x) IMX_IO_P2V(x)
62#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
63
Shawn Guo8842a9e2012-06-14 11:16:14 +080064/*
65 * Interrupt numbers
66 */
67#include <asm/irq.h>
68#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
69#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
70#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
71#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
72#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
73#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
74#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
75#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
76#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
77#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
78#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
79#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
80#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
81#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
82#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
83#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
84#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
85#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
86#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
87#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
88#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
89#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
90#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
91#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
92#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
93#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
94#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
95#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
96#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
97#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
98#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
99#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
100#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
Sascha Hauer42a3f892012-09-18 10:05:31 +0200101#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54)
Shawn Guo8842a9e2012-06-14 11:16:14 +0800102#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
Baruch Siacha7595442009-12-21 13:44:31 +0200103
Uwe Kleine-König4697bb92010-08-25 17:37:45 +0200104#define MX25_DMA_REQ_SSI2_RX1 22
105#define MX25_DMA_REQ_SSI2_TX1 23
106#define MX25_DMA_REQ_SSI2_RX0 24
107#define MX25_DMA_REQ_SSI2_TX0 25
108#define MX25_DMA_REQ_SSI1_RX1 26
109#define MX25_DMA_REQ_SSI1_TX1 27
110#define MX25_DMA_REQ_SSI1_RX0 28
111#define MX25_DMA_REQ_SSI1_TX0 29
112
Jason Liud27536c2011-08-26 13:35:19 +0800113#ifndef __ASSEMBLY__
114extern int mx25_revision(void);
115#endif
116
Uwe Kleine-König3cdd5442010-01-08 16:02:30 +0100117#endif /* ifndef __MACH_MX25_H__ */