blob: 845025a57240ac3517c7401c3bbe7c0f7c4ebe8a [file] [log] [blame]
Rabin Vincent03f822f2010-07-02 16:52:09 +05301/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
Rabin Vincent03f822f2010-07-02 16:52:09 +053013#include <linux/interrupt.h>
Vipul Kumar Samar86605cf2012-11-26 17:06:51 +053014#include <linux/of.h>
Rabin Vincent03f822f2010-07-02 16:52:09 +053015#include <linux/mfd/stmpe.h>
16
17/*
18 * These registers are modified under the irq bus lock and cached to avoid
19 * unnecessary writes in bus_sync_unlock.
20 */
21enum { REG_RE, REG_FE, REG_IE };
22
23#define CACHE_NR_REGS 3
Linus Walleij9e9dc7d2014-05-08 23:16:34 +020024/* No variant has more than 24 GPIOs */
25#define CACHE_NR_BANKS (24 / 8)
Rabin Vincent03f822f2010-07-02 16:52:09 +053026
27struct stmpe_gpio {
28 struct gpio_chip chip;
29 struct stmpe *stmpe;
30 struct device *dev;
31 struct mutex irq_lock;
Wolfram Sangb8e9cf02010-08-16 17:14:44 +020032 unsigned norequest_mask;
Rabin Vincent03f822f2010-07-02 16:52:09 +053033 /* Caches of interrupt control registers for bus_lock */
34 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
35 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
36};
37
38static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
39{
40 return container_of(chip, struct stmpe_gpio, chip);
41}
42
43static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
44{
45 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
46 struct stmpe *stmpe = stmpe_gpio->stmpe;
47 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
48 u8 mask = 1 << (offset % 8);
49 int ret;
50
51 ret = stmpe_reg_read(stmpe, reg);
52 if (ret < 0)
53 return ret;
54
Bhupesh Sharma7535b8b2012-02-27 11:19:43 +053055 return !!(ret & mask);
Rabin Vincent03f822f2010-07-02 16:52:09 +053056}
57
58static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
59{
60 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
61 struct stmpe *stmpe = stmpe_gpio->stmpe;
62 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
63 u8 reg = stmpe->regs[which] - (offset / 8);
64 u8 mask = 1 << (offset % 8);
65
Viresh Kumarcccdceb2011-12-14 09:28:27 +053066 /*
67 * Some variants have single register for gpio set/clear functionality.
68 * For them we need to write 0 to clear and 1 to set.
69 */
70 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
71 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
72 else
73 stmpe_reg_write(stmpe, reg, mask);
Rabin Vincent03f822f2010-07-02 16:52:09 +053074}
75
76static int stmpe_gpio_direction_output(struct gpio_chip *chip,
77 unsigned offset, int val)
78{
79 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
80 struct stmpe *stmpe = stmpe_gpio->stmpe;
81 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
82 u8 mask = 1 << (offset % 8);
83
84 stmpe_gpio_set(chip, offset, val);
85
86 return stmpe_set_bits(stmpe, reg, mask, mask);
87}
88
89static int stmpe_gpio_direction_input(struct gpio_chip *chip,
90 unsigned offset)
91{
92 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
93 struct stmpe *stmpe = stmpe_gpio->stmpe;
94 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
95 u8 mask = 1 << (offset % 8);
96
97 return stmpe_set_bits(stmpe, reg, mask, 0);
98}
99
Rabin Vincent03f822f2010-07-02 16:52:09 +0530100static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
101{
102 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
103 struct stmpe *stmpe = stmpe_gpio->stmpe;
104
Wolfram Sangb8e9cf02010-08-16 17:14:44 +0200105 if (stmpe_gpio->norequest_mask & (1 << offset))
106 return -EINVAL;
107
Rabin Vincent03f822f2010-07-02 16:52:09 +0530108 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
109}
110
111static struct gpio_chip template_chip = {
112 .label = "stmpe",
113 .owner = THIS_MODULE,
114 .direction_input = stmpe_gpio_direction_input,
115 .get = stmpe_gpio_get,
116 .direction_output = stmpe_gpio_direction_output,
117 .set = stmpe_gpio_set,
Rabin Vincent03f822f2010-07-02 16:52:09 +0530118 .request = stmpe_gpio_request,
Linus Walleij9fb1f392013-12-04 14:42:46 +0100119 .can_sleep = true,
Rabin Vincent03f822f2010-07-02 16:52:09 +0530120};
121
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800122static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530123{
Linus Walleijfe44e702014-04-15 23:38:56 +0200124 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
125 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
Lee Jonesfc13d5a2012-12-10 10:07:54 +0000126 int offset = d->hwirq;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530127 int regoffset = offset / 8;
128 int mask = 1 << (offset % 8);
129
130 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
131 return -EINVAL;
132
Viresh Kumarcccdceb2011-12-14 09:28:27 +0530133 /* STMPE801 doesn't have RE and FE registers */
134 if (stmpe_gpio->stmpe->partnum == STMPE801)
135 return 0;
136
Rabin Vincent03f822f2010-07-02 16:52:09 +0530137 if (type == IRQ_TYPE_EDGE_RISING)
138 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
139 else
140 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
141
142 if (type == IRQ_TYPE_EDGE_FALLING)
143 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
144 else
145 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
146
147 return 0;
148}
149
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800150static void stmpe_gpio_irq_lock(struct irq_data *d)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530151{
Linus Walleijfe44e702014-04-15 23:38:56 +0200152 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
153 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530154
155 mutex_lock(&stmpe_gpio->irq_lock);
156}
157
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800158static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530159{
Linus Walleijfe44e702014-04-15 23:38:56 +0200160 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
161 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530162 struct stmpe *stmpe = stmpe_gpio->stmpe;
163 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
164 static const u8 regmap[] = {
165 [REG_RE] = STMPE_IDX_GPRER_LSB,
166 [REG_FE] = STMPE_IDX_GPFER_LSB,
167 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
168 };
169 int i, j;
170
171 for (i = 0; i < CACHE_NR_REGS; i++) {
Viresh Kumarcccdceb2011-12-14 09:28:27 +0530172 /* STMPE801 doesn't have RE and FE registers */
173 if ((stmpe->partnum == STMPE801) &&
174 (i != REG_IE))
175 continue;
176
Rabin Vincent03f822f2010-07-02 16:52:09 +0530177 for (j = 0; j < num_banks; j++) {
178 u8 old = stmpe_gpio->oldregs[i][j];
179 u8 new = stmpe_gpio->regs[i][j];
180
181 if (new == old)
182 continue;
183
184 stmpe_gpio->oldregs[i][j] = new;
185 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
186 }
187 }
188
189 mutex_unlock(&stmpe_gpio->irq_lock);
190}
191
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800192static void stmpe_gpio_irq_mask(struct irq_data *d)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530193{
Linus Walleijfe44e702014-04-15 23:38:56 +0200194 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
195 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
Lee Jonesfc13d5a2012-12-10 10:07:54 +0000196 int offset = d->hwirq;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530197 int regoffset = offset / 8;
198 int mask = 1 << (offset % 8);
199
200 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
201}
202
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800203static void stmpe_gpio_irq_unmask(struct irq_data *d)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530204{
Linus Walleijfe44e702014-04-15 23:38:56 +0200205 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
206 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
Lee Jonesfc13d5a2012-12-10 10:07:54 +0000207 int offset = d->hwirq;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530208 int regoffset = offset / 8;
209 int mask = 1 << (offset % 8);
210
211 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
212}
213
214static struct irq_chip stmpe_gpio_irq_chip = {
215 .name = "stmpe-gpio",
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800216 .irq_bus_lock = stmpe_gpio_irq_lock,
217 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
218 .irq_mask = stmpe_gpio_irq_mask,
219 .irq_unmask = stmpe_gpio_irq_unmask,
220 .irq_set_type = stmpe_gpio_irq_set_type,
Rabin Vincent03f822f2010-07-02 16:52:09 +0530221};
222
223static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
224{
225 struct stmpe_gpio *stmpe_gpio = dev;
226 struct stmpe *stmpe = stmpe_gpio->stmpe;
227 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
228 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
229 u8 status[num_banks];
230 int ret;
231 int i;
232
233 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
234 if (ret < 0)
235 return IRQ_NONE;
236
237 for (i = 0; i < num_banks; i++) {
238 int bank = num_banks - i - 1;
239 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
240 unsigned int stat = status[i];
241
242 stat &= enabled;
243 if (!stat)
244 continue;
245
246 while (stat) {
247 int bit = __ffs(stat);
248 int line = bank * 8 + bit;
Linus Walleijfe44e702014-04-15 23:38:56 +0200249 int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
Linus Walleijed05e202013-10-11 19:51:38 +0200250 line);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530251
Linus Walleijed05e202013-10-11 19:51:38 +0200252 handle_nested_irq(child_irq);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530253 stat &= ~(1 << bit);
254 }
255
256 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
Viresh Kumarcccdceb2011-12-14 09:28:27 +0530257
258 /* Edge detect register is not present on 801 */
259 if (stmpe->partnum != STMPE801)
260 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
261 + i, status[i]);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530262 }
263
264 return IRQ_HANDLED;
265}
266
Bill Pemberton38363092012-11-19 13:22:34 -0500267static int stmpe_gpio_probe(struct platform_device *pdev)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530268{
269 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
Vipul Kumar Samar86605cf2012-11-26 17:06:51 +0530270 struct device_node *np = pdev->dev.of_node;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530271 struct stmpe_gpio_platform_data *pdata;
272 struct stmpe_gpio *stmpe_gpio;
273 int ret;
Chris Blair38040c82012-01-26 22:17:15 +0100274 int irq = 0;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530275
276 pdata = stmpe->pdata->gpio;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530277
278 irq = platform_get_irq(pdev, 0);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530279
280 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
281 if (!stmpe_gpio)
282 return -ENOMEM;
283
284 mutex_init(&stmpe_gpio->irq_lock);
285
286 stmpe_gpio->dev = &pdev->dev;
287 stmpe_gpio->stmpe = stmpe;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530288 stmpe_gpio->chip = template_chip;
289 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
290 stmpe_gpio->chip.dev = &pdev->dev;
Gabriel Fernandez9afd9b72013-03-18 11:45:05 +0100291#ifdef CONFIG_OF
292 stmpe_gpio->chip.of_node = np;
293#endif
Linus Walleij9e9dc7d2014-05-08 23:16:34 +0200294 stmpe_gpio->chip.base = -1;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530295
Vipul Kumar Samar86605cf2012-11-26 17:06:51 +0530296 if (pdata)
297 stmpe_gpio->norequest_mask = pdata->norequest_mask;
298 else if (np)
299 of_property_read_u32(np, "st,norequest-mask",
300 &stmpe_gpio->norequest_mask);
301
Linus Walleij9e9dc7d2014-05-08 23:16:34 +0200302 if (irq < 0)
Chris Blair38040c82012-01-26 22:17:15 +0100303 dev_info(&pdev->dev,
Linus Walleijfe44e702014-04-15 23:38:56 +0200304 "device configured in no-irq mode: "
Chris Blair38040c82012-01-26 22:17:15 +0100305 "irqs are not available\n");
Rabin Vincent03f822f2010-07-02 16:52:09 +0530306
307 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
308 if (ret)
Vasiliy Kulikov02bf0742010-09-12 22:57:19 +0400309 goto out_free;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530310
Linus Walleijfe44e702014-04-15 23:38:56 +0200311 if (irq > 0) {
312 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
313 stmpe_gpio_irq, IRQF_ONESHOT,
314 "stmpe-gpio", stmpe_gpio);
Chris Blair38040c82012-01-26 22:17:15 +0100315 if (ret) {
316 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
Lee Jonesfc13d5a2012-12-10 10:07:54 +0000317 goto out_disable;
Chris Blair38040c82012-01-26 22:17:15 +0100318 }
Linus Walleijfe44e702014-04-15 23:38:56 +0200319 ret = gpiochip_irqchip_add(&stmpe_gpio->chip,
320 &stmpe_gpio_irq_chip,
321 0,
322 handle_simple_irq,
323 IRQ_TYPE_NONE);
324 if (ret) {
325 dev_err(&pdev->dev,
326 "could not connect irqchip to gpiochip\n");
327 return ret;
328 }
Rabin Vincent03f822f2010-07-02 16:52:09 +0530329 }
330
331 ret = gpiochip_add(&stmpe_gpio->chip);
332 if (ret) {
333 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
Linus Walleijfe44e702014-04-15 23:38:56 +0200334 goto out_disable;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530335 }
336
337 if (pdata && pdata->setup)
338 pdata->setup(stmpe, stmpe_gpio->chip.base);
339
340 platform_set_drvdata(pdev, stmpe_gpio);
341
342 return 0;
343
Vasiliy Kulikov02bf0742010-09-12 22:57:19 +0400344out_disable:
345 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530346out_free:
347 kfree(stmpe_gpio);
348 return ret;
349}
350
Bill Pemberton206210c2012-11-19 13:25:50 -0500351static int stmpe_gpio_remove(struct platform_device *pdev)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530352{
353 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
354 struct stmpe *stmpe = stmpe_gpio->stmpe;
355 struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530356
357 if (pdata && pdata->remove)
358 pdata->remove(stmpe, stmpe_gpio->chip.base);
359
abdoulaye berthe9f5132a2014-07-12 22:30:12 +0200360 gpiochip_remove(&stmpe_gpio->chip);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530361
362 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
363
Rabin Vincent03f822f2010-07-02 16:52:09 +0530364 kfree(stmpe_gpio);
365
366 return 0;
367}
368
369static struct platform_driver stmpe_gpio_driver = {
370 .driver.name = "stmpe-gpio",
371 .driver.owner = THIS_MODULE,
372 .probe = stmpe_gpio_probe,
Bill Pemberton8283c4f2012-11-19 13:20:08 -0500373 .remove = stmpe_gpio_remove,
Rabin Vincent03f822f2010-07-02 16:52:09 +0530374};
375
376static int __init stmpe_gpio_init(void)
377{
378 return platform_driver_register(&stmpe_gpio_driver);
379}
380subsys_initcall(stmpe_gpio_init);
381
382static void __exit stmpe_gpio_exit(void)
383{
384 platform_driver_unregister(&stmpe_gpio_driver);
385}
386module_exit(stmpe_gpio_exit);
387
388MODULE_LICENSE("GPL v2");
389MODULE_DESCRIPTION("STMPExxxx GPIO driver");
390MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");