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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/************************************************************************
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -07002 * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
Ramkrishna Vepa0c61ed52007-03-09 18:28:32 -08003 * Copyright(c) 2002-2007 Neterion Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07004
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _REGS_H
14#define _REGS_H
15
16#define TBD 0
17
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050018struct XENA_dev_config {
Linus Torvalds1da177e2005-04-16 15:20:36 -070019/* Convention: mHAL_XXX is mask, vHAL_XXX is value */
20
21/* General Control-Status Registers */
22 u64 general_int_status;
Jiri Slabyb7b5a122007-10-18 23:40:29 -070023#define GEN_INTR_TXPIC s2BIT(0)
24#define GEN_INTR_TXDMA s2BIT(1)
25#define GEN_INTR_TXMAC s2BIT(2)
26#define GEN_INTR_TXXGXS s2BIT(3)
27#define GEN_INTR_TXTRAFFIC s2BIT(8)
28#define GEN_INTR_RXPIC s2BIT(32)
29#define GEN_INTR_RXDMA s2BIT(33)
30#define GEN_INTR_RXMAC s2BIT(34)
31#define GEN_INTR_MC s2BIT(35)
32#define GEN_INTR_RXXGXS s2BIT(36)
33#define GEN_INTR_RXTRAFFIC s2BIT(40)
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
35 GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
36 GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
37 GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
38 GEN_INTR_MC
39
40 u64 general_int_mask;
41
42 u8 unused0[0x100 - 0x10];
43
44 u64 sw_reset;
45/* XGXS must be removed from reset only once. */
46#define SW_RESET_XENA vBIT(0xA5,0,8)
47#define SW_RESET_FLASH vBIT(0xA5,8,8)
48#define SW_RESET_EOI vBIT(0xA5,16,8)
49#define SW_RESET_ALL (SW_RESET_XENA | \
50 SW_RESET_FLASH | \
51 SW_RESET_EOI)
52/* The SW_RESET register must read this value after a successful reset. */
53#define SW_RESET_RAW_VAL 0xA5000000
54
55
56 u64 adapter_status;
Jiri Slabyb7b5a122007-10-18 23:40:29 -070057#define ADAPTER_STATUS_TDMA_READY s2BIT(0)
58#define ADAPTER_STATUS_RDMA_READY s2BIT(1)
59#define ADAPTER_STATUS_PFC_READY s2BIT(2)
60#define ADAPTER_STATUS_TMAC_BUF_EMPTY s2BIT(3)
61#define ADAPTER_STATUS_PIC_QUIESCENT s2BIT(5)
62#define ADAPTER_STATUS_RMAC_REMOTE_FAULT s2BIT(6)
63#define ADAPTER_STATUS_RMAC_LOCAL_FAULT s2BIT(7)
Linus Torvalds1da177e2005-04-16 15:20:36 -070064#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
raghavendra.koushik@neterion.com5e25b9d2005-08-03 12:27:09 -070065#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8)
Linus Torvalds1da177e2005-04-16 15:20:36 -070066#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
Jiri Slabyb7b5a122007-10-18 23:40:29 -070067#define ADAPTER_STATUS_MC_DRAM_READY s2BIT(24)
68#define ADAPTER_STATUS_MC_QUEUES_READY s2BIT(25)
Sreenivasa Honnur79620242007-12-05 23:59:28 -050069#define ADAPTER_STATUS_RIC_RUNNING s2BIT(26)
Jiri Slabyb7b5a122007-10-18 23:40:29 -070070#define ADAPTER_STATUS_M_PLL_LOCK s2BIT(30)
71#define ADAPTER_STATUS_P_PLL_LOCK s2BIT(31)
Linus Torvalds1da177e2005-04-16 15:20:36 -070072
73 u64 adapter_control;
Jiri Slabyb7b5a122007-10-18 23:40:29 -070074#define ADAPTER_CNTL_EN s2BIT(7)
75#define ADAPTER_EOI_TX_ON s2BIT(15)
76#define ADAPTER_LED_ON s2BIT(23)
Linus Torvalds1da177e2005-04-16 15:20:36 -070077#define ADAPTER_UDPI(val) vBIT(val,36,4)
Jiri Slabyb7b5a122007-10-18 23:40:29 -070078#define ADAPTER_WAIT_INT s2BIT(48)
79#define ADAPTER_ECC_EN s2BIT(55)
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
81 u64 serr_source;
Jiri Slabyb7b5a122007-10-18 23:40:29 -070082#define SERR_SOURCE_PIC s2BIT(0)
83#define SERR_SOURCE_TXDMA s2BIT(1)
84#define SERR_SOURCE_RXDMA s2BIT(2)
85#define SERR_SOURCE_MAC s2BIT(3)
86#define SERR_SOURCE_MC s2BIT(4)
87#define SERR_SOURCE_XGXS s2BIT(5)
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070088#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
89 SERR_SOURCE_TXDMA | \
90 SERR_SOURCE_RXDMA | \
91 SERR_SOURCE_MAC | \
92 SERR_SOURCE_MC | \
93 SERR_SOURCE_XGXS)
Linus Torvalds1da177e2005-04-16 15:20:36 -070094
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -070095 u64 pci_mode;
96#define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60)
97#define PCI_MODE_PCI_33 0
98#define PCI_MODE_PCI_66 0x1
99#define PCI_MODE_PCIX_M1_66 0x2
100#define PCI_MODE_PCIX_M1_100 0x3
101#define PCI_MODE_PCIX_M1_133 0x4
102#define PCI_MODE_PCIX_M2_66 0x5
103#define PCI_MODE_PCIX_M2_100 0x6
104#define PCI_MODE_PCIX_M2_133 0x7
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700105#define PCI_MODE_UNSUPPORTED s2BIT(0)
106#define PCI_MODE_32_BITS s2BIT(8)
107#define PCI_MODE_UNKNOWN_MODE s2BIT(9)
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700108
109 u8 unused_0[0x800 - 0x128];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
111/* PCI-X Controller registers */
112 u64 pic_int_status;
113 u64 pic_int_mask;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700114#define PIC_INT_TX s2BIT(0)
115#define PIC_INT_FLSH s2BIT(1)
116#define PIC_INT_MDIO s2BIT(2)
117#define PIC_INT_IIC s2BIT(3)
118#define PIC_INT_GPIO s2BIT(4)
119#define PIC_INT_RX s2BIT(32)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120
121 u64 txpic_int_reg;
122 u64 txpic_int_mask;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700123#define PCIX_INT_REG_ECC_SG_ERR s2BIT(0)
124#define PCIX_INT_REG_ECC_DB_ERR s2BIT(1)
125#define PCIX_INT_REG_FLASHR_R_FSM_ERR s2BIT(8)
126#define PCIX_INT_REG_FLASHR_W_FSM_ERR s2BIT(9)
127#define PCIX_INT_REG_INI_TX_FSM_SERR s2BIT(10)
128#define PCIX_INT_REG_INI_TXO_FSM_ERR s2BIT(11)
129#define PCIX_INT_REG_TRT_FSM_SERR s2BIT(13)
130#define PCIX_INT_REG_SRT_FSM_SERR s2BIT(14)
131#define PCIX_INT_REG_PIFR_FSM_SERR s2BIT(15)
132#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR s2BIT(21)
133#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR s2BIT(23)
134#define PCIX_INT_REG_INI_RX_FSM_SERR s2BIT(48)
135#define PCIX_INT_REG_RA_RX_FSM_SERR s2BIT(50)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136/*
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700137#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR s2BIT(52)
138#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR s2BIT(54)
139#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR s2BIT(58)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140*/
141 u64 txpic_alarms;
142 u64 rxpic_int_reg;
143 u64 rxpic_int_mask;
144 u64 rxpic_alarms;
145
146 u64 flsh_int_reg;
147 u64 flsh_int_mask;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700148#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR s2BIT(63)
149#define PIC_FLSH_INT_REG_ERR s2BIT(62)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150 u64 flash_alarms;
151
152 u64 mdio_int_reg;
153 u64 mdio_int_mask;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700154#define MDIO_INT_REG_MDIO_BUS_ERR s2BIT(0)
155#define MDIO_INT_REG_DTX_BUS_ERR s2BIT(8)
156#define MDIO_INT_REG_LASI s2BIT(39)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157 u64 mdio_alarms;
158
159 u64 iic_int_reg;
160 u64 iic_int_mask;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700161#define IIC_INT_REG_BUS_FSM_ERR s2BIT(4)
162#define IIC_INT_REG_BIT_FSM_ERR s2BIT(5)
163#define IIC_INT_REG_CYCLE_FSM_ERR s2BIT(6)
164#define IIC_INT_REG_REQ_FSM_ERR s2BIT(7)
165#define IIC_INT_REG_ACK_ERR s2BIT(8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 u64 iic_alarms;
167
168 u8 unused4[0x08];
169
170 u64 gpio_int_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700171#define GPIO_INT_REG_DP_ERR_INT s2BIT(0)
172#define GPIO_INT_REG_LINK_DOWN s2BIT(1)
173#define GPIO_INT_REG_LINK_UP s2BIT(2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174 u64 gpio_int_mask;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700175#define GPIO_INT_MASK_LINK_DOWN s2BIT(1)
176#define GPIO_INT_MASK_LINK_UP s2BIT(2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 u64 gpio_alarms;
178
179 u8 unused5[0x38];
180
181 u64 tx_traffic_int;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700182#define TX_TRAFFIC_INT_n(n) s2BIT(n)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183 u64 tx_traffic_mask;
184
185 u64 rx_traffic_int;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700186#define RX_TRAFFIC_INT_n(n) s2BIT(n)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187 u64 rx_traffic_mask;
188
189/* PIC Control registers */
190 u64 pic_control;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700191#define PIC_CNTL_RX_ALARM_MAP_1 s2BIT(0)
Ananda Raju863c11a2006-04-21 19:03:13 -0400192#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193
194 u64 swapper_ctrl;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700195#define SWAPPER_CTRL_PIF_R_FE s2BIT(0)
196#define SWAPPER_CTRL_PIF_R_SE s2BIT(1)
197#define SWAPPER_CTRL_PIF_W_FE s2BIT(8)
198#define SWAPPER_CTRL_PIF_W_SE s2BIT(9)
199#define SWAPPER_CTRL_TXP_FE s2BIT(16)
200#define SWAPPER_CTRL_TXP_SE s2BIT(17)
201#define SWAPPER_CTRL_TXD_R_FE s2BIT(18)
202#define SWAPPER_CTRL_TXD_R_SE s2BIT(19)
203#define SWAPPER_CTRL_TXD_W_FE s2BIT(20)
204#define SWAPPER_CTRL_TXD_W_SE s2BIT(21)
205#define SWAPPER_CTRL_TXF_R_FE s2BIT(22)
206#define SWAPPER_CTRL_TXF_R_SE s2BIT(23)
207#define SWAPPER_CTRL_RXD_R_FE s2BIT(32)
208#define SWAPPER_CTRL_RXD_R_SE s2BIT(33)
209#define SWAPPER_CTRL_RXD_W_FE s2BIT(34)
210#define SWAPPER_CTRL_RXD_W_SE s2BIT(35)
211#define SWAPPER_CTRL_RXF_W_FE s2BIT(36)
212#define SWAPPER_CTRL_RXF_W_SE s2BIT(37)
213#define SWAPPER_CTRL_XMSI_FE s2BIT(40)
214#define SWAPPER_CTRL_XMSI_SE s2BIT(41)
215#define SWAPPER_CTRL_STATS_FE s2BIT(48)
216#define SWAPPER_CTRL_STATS_SE s2BIT(49)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217
218 u64 pif_rd_swapper_fb;
219#define IF_RD_SWAPPER_FB 0x0123456789ABCDEF
220
221 u64 scheduled_int_ctrl;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700222#define SCHED_INT_CTRL_TIMER_EN s2BIT(0)
223#define SCHED_INT_CTRL_ONE_SHOT s2BIT(1)
Sivakumar Subramani8abc4d52007-09-15 13:11:34 -0700224#define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225#define SCHED_INT_PERIOD TBD
226
227 u64 txreqtimeout;
228#define TXREQTO_VAL(val) vBIT(val,0,32)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700229#define TXREQTO_EN s2BIT(63)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230
231 u64 statsreqtimeout;
232#define STATREQTO_VAL(n) TBD
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700233#define STATREQTO_EN s2BIT(63)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234
235 u64 read_retry_delay;
236 u64 read_retry_acceleration;
237 u64 write_retry_delay;
238 u64 write_retry_acceleration;
239
240 u64 xmsi_control;
241 u64 xmsi_access;
242 u64 xmsi_address;
243 u64 xmsi_data;
244
245 u64 rx_mat;
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700246#define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247
248 u8 unused6[0x8];
249
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700250 u64 tx_mat0_n[0x8];
251#define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252
Sreenivasa Honnurf61e0a32008-05-12 13:42:17 -0400253 u64 xmsi_mask_reg;
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700254 u64 stat_byte_cnt;
255#define STAT_BC(n) vBIT(n,4,12)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256
257 /* Automated statistics collection */
258 u64 stat_cfg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700259#define STAT_CFG_STAT_EN s2BIT(0)
260#define STAT_CFG_ONE_SHOT_EN s2BIT(1)
261#define STAT_CFG_STAT_NS_EN s2BIT(8)
262#define STAT_CFG_STAT_RO s2BIT(9)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263#define STAT_TRSF_PER(n) TBD
264#define PER_SEC 0x208d5
265#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
raghavendra.koushik@neterion.com5e25b9d2005-08-03 12:27:09 -0700266#define SET_UPDT_CLICKS(val) vBIT(val, 32, 32)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267
268 u64 stat_addr;
269
270 /* General Configuration */
271 u64 mdio_control;
Ananda Rajubd1034f2006-04-21 19:20:22 -0400272#define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16)
273#define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5)
274#define MDIO_MMD_PMA_DEV_ADDR 0x1
275#define MDIO_MMD_PMD_DEV_ADDR 0x1
276#define MDIO_MMD_WIS_DEV_ADDR 0x2
277#define MDIO_MMD_PCS_DEV_ADDR 0x3
278#define MDIO_MMD_PHYXS_DEV_ADDR 0x4
279#define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5)
280#define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4)
281#define MDIO_OP(val) vBIT(val, 60, 2)
282#define MDIO_OP_ADDR_TRANS 0x0
283#define MDIO_OP_WRITE_TRANS 0x1
284#define MDIO_OP_READ_POST_INC_TRANS 0x2
285#define MDIO_OP_READ_TRANS 0x3
286#define MDIO_MDIO_DATA(val) vBIT(val, 32, 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287
288 u64 dtx_control;
289
290 u64 i2c_control;
291#define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
292#define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
293#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700294#define I2C_CONTROL_READ s2BIT(24)
295#define I2C_CONTROL_NACK s2BIT(25)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296#define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
297#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
298#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
299#define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
300
301 u64 gpio_control;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700302#define GPIO_CTRL_GPIO_0 s2BIT(8)
raghavendra.koushik@neterion.coma371a072005-08-03 12:38:59 -0700303 u64 misc_control;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700304#define FAULT_BEHAVIOUR s2BIT(0)
305#define EXT_REQ_EN s2BIT(1)
raghavendra.koushik@neterion.coma371a072005-08-03 12:38:59 -0700306#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307
Ananda Raju863c11a2006-04-21 19:03:13 -0400308 u8 unused7_1[0x230 - 0x208];
309
310 u64 pic_control2;
311 u64 ini_dperr_ctrl;
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700312
313 u64 wreq_split_mask;
314#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
315
316 u8 unused7_2[0x800 - 0x248];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317
318/* TxDMA registers */
319 u64 txdma_int_status;
320 u64 txdma_int_mask;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700321#define TXDMA_PFC_INT s2BIT(0)
322#define TXDMA_TDA_INT s2BIT(1)
323#define TXDMA_PCC_INT s2BIT(2)
324#define TXDMA_TTI_INT s2BIT(3)
325#define TXDMA_LSO_INT s2BIT(4)
326#define TXDMA_TPA_INT s2BIT(5)
327#define TXDMA_SM_INT s2BIT(6)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328 u64 pfc_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700329#define PFC_ECC_SG_ERR s2BIT(7)
330#define PFC_ECC_DB_ERR s2BIT(15)
331#define PFC_SM_ERR_ALARM s2BIT(23)
332#define PFC_MISC_0_ERR s2BIT(31)
333#define PFC_MISC_1_ERR s2BIT(32)
334#define PFC_PCIX_ERR s2BIT(39)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 u64 pfc_err_mask;
336 u64 pfc_err_alarm;
337
338 u64 tda_err_reg;
Sivakumar Subramani9caab452007-09-06 06:21:54 -0400339#define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8)
340#define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700341#define TDA_SM0_ERR_ALARM s2BIT(22)
342#define TDA_SM1_ERR_ALARM s2BIT(23)
343#define TDA_PCIX_ERR s2BIT(39)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344 u64 tda_err_mask;
345 u64 tda_err_alarm;
346
347 u64 pcc_err_reg;
Sivakumar Subramani9caab452007-09-06 06:21:54 -0400348#define PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8)
349#define PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8)
350#define PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8)
351#define PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8)
352#define PCC_SM_ERR_ALARM vBIT(0xff,32,8)
353#define PCC_WR_ERR_ALARM vBIT(0xff,40,8)
354#define PCC_N_SERR vBIT(0xff,48,8)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700355#define PCC_6_COF_OV_ERR s2BIT(56)
356#define PCC_7_COF_OV_ERR s2BIT(57)
357#define PCC_6_LSO_OV_ERR s2BIT(58)
358#define PCC_7_LSO_OV_ERR s2BIT(59)
raghavendra.koushik@neterion.com5e25b9d2005-08-03 12:27:09 -0700359#define PCC_ENABLE_FOUR vBIT(0x0F,0,8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360 u64 pcc_err_mask;
361 u64 pcc_err_alarm;
362
363 u64 tti_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700364#define TTI_ECC_SG_ERR s2BIT(7)
365#define TTI_ECC_DB_ERR s2BIT(15)
366#define TTI_SM_ERR_ALARM s2BIT(23)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 u64 tti_err_mask;
368 u64 tti_err_alarm;
369
370 u64 lso_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700371#define LSO6_SEND_OFLOW s2BIT(12)
372#define LSO7_SEND_OFLOW s2BIT(13)
373#define LSO6_ABORT s2BIT(14)
374#define LSO7_ABORT s2BIT(15)
375#define LSO6_SM_ERR_ALARM s2BIT(22)
376#define LSO7_SM_ERR_ALARM s2BIT(23)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377 u64 lso_err_mask;
378 u64 lso_err_alarm;
379
380 u64 tpa_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700381#define TPA_TX_FRM_DROP s2BIT(7)
382#define TPA_SM_ERR_ALARM s2BIT(23)
Sivakumar Subramani9caab452007-09-06 06:21:54 -0400383
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384 u64 tpa_err_mask;
385 u64 tpa_err_alarm;
386
387 u64 sm_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700388#define SM_SM_ERR_ALARM s2BIT(15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389 u64 sm_err_mask;
390 u64 sm_err_alarm;
391
392 u8 unused8[0x100 - 0xB8];
393
394/* TxDMA arbiter */
395 u64 tx_dma_wrap_stat;
396
397/* Tx FIFO controller */
398#define X_MAX_FIFOS 8
399#define X_FIFO_MAX_LEN 0x1FFF /*8191 */
400 u64 tx_fifo_partition_0;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700401#define TX_FIFO_PARTITION_EN s2BIT(0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700402#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
403#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
404#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
405#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
406
407 u64 tx_fifo_partition_1;
408#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
409#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
410#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
411#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
412
413 u64 tx_fifo_partition_2;
414#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
415#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
416#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
417#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
418
419 u64 tx_fifo_partition_3;
420#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
421#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
422#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
423#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
424
425#define TX_FIFO_PARTITION_PRI_0 0 /* highest */
426#define TX_FIFO_PARTITION_PRI_1 1
427#define TX_FIFO_PARTITION_PRI_2 2
428#define TX_FIFO_PARTITION_PRI_3 3
429#define TX_FIFO_PARTITION_PRI_4 4
430#define TX_FIFO_PARTITION_PRI_5 5
431#define TX_FIFO_PARTITION_PRI_6 6
432#define TX_FIFO_PARTITION_PRI_7 7 /* lowest */
433
434 u64 tx_w_round_robin_0;
435 u64 tx_w_round_robin_1;
436 u64 tx_w_round_robin_2;
437 u64 tx_w_round_robin_3;
438 u64 tx_w_round_robin_4;
439
440 u64 tti_command_mem;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700441#define TTI_CMD_MEM_WE s2BIT(7)
442#define TTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
443#define TTI_CMD_MEM_STROBE_BEING_EXECUTED s2BIT(15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444#define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
445
446 u64 tti_data1_mem;
447#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
448#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700449#define TTI_DATA1_MEM_TX_TIMER_AC_EN s2BIT(38)
450#define TTI_DATA1_MEM_TX_TIMER_CI_EN s2BIT(39)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
452#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
453#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
454
455 u64 tti_data2_mem;
456#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
457#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
458#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
459#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
460
461/* Tx Protocol assist */
462 u64 tx_pa_cfg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700463#define TX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
464#define TX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)
465#define TX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)
466#define TX_PA_CFG_IGNORE_L2_ERR s2BIT(6)
467#define RX_PA_CFG_STRIP_VLAN_TAG s2BIT(15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468
469/* Recent add, used only debug purposes. */
470 u64 pcc_enable;
471
472 u8 unused9[0x700 - 0x178];
473
474 u64 txdma_debug_ctrl;
475
476 u8 unused10[0x1800 - 0x1708];
477
478/* RxDMA Registers */
479 u64 rxdma_int_status;
480 u64 rxdma_int_mask;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700481#define RXDMA_INT_RC_INT_M s2BIT(0)
482#define RXDMA_INT_RPA_INT_M s2BIT(1)
483#define RXDMA_INT_RDA_INT_M s2BIT(2)
484#define RXDMA_INT_RTI_INT_M s2BIT(3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485
486 u64 rda_err_reg;
Sivakumar Subramani9caab452007-09-06 06:21:54 -0400487#define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8)
488#define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700489#define RDA_FRM_ECC_SG_ERR s2BIT(23)
490#define RDA_FRM_ECC_DB_N_AERR s2BIT(31)
491#define RDA_SM1_ERR_ALARM s2BIT(38)
492#define RDA_SM0_ERR_ALARM s2BIT(39)
493#define RDA_MISC_ERR s2BIT(47)
494#define RDA_PCIX_ERR s2BIT(55)
495#define RDA_RXD_ECC_DB_SERR s2BIT(63)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496 u64 rda_err_mask;
497 u64 rda_err_alarm;
498
499 u64 rc_err_reg;
Sivakumar Subramani9caab452007-09-06 06:21:54 -0400500#define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8)
501#define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700502#define RC_FTC_ECC_SG_ERR s2BIT(23)
503#define RC_FTC_ECC_DB_ERR s2BIT(31)
Sivakumar Subramani9caab452007-09-06 06:21:54 -0400504#define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700505#define RC_FTC_SM_ERR_ALARM s2BIT(47)
Sivakumar Subramani9caab452007-09-06 06:21:54 -0400506#define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507 u64 rc_err_mask;
508 u64 rc_err_alarm;
509
510 u64 prc_pcix_err_reg;
Sivakumar Subramani9caab452007-09-06 06:21:54 -0400511#define PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8)
512#define PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8)
513#define PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8)
514#define PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8)
515#define PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8)
516#define PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517 u64 prc_pcix_err_mask;
518 u64 prc_pcix_err_alarm;
519
520 u64 rpa_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700521#define RPA_ECC_SG_ERR s2BIT(7)
522#define RPA_ECC_DB_ERR s2BIT(15)
523#define RPA_FLUSH_REQUEST s2BIT(22)
524#define RPA_SM_ERR_ALARM s2BIT(23)
525#define RPA_CREDIT_ERR s2BIT(31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526 u64 rpa_err_mask;
527 u64 rpa_err_alarm;
528
529 u64 rti_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700530#define RTI_ECC_SG_ERR s2BIT(7)
531#define RTI_ECC_DB_ERR s2BIT(15)
532#define RTI_SM_ERR_ALARM s2BIT(23)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 u64 rti_err_mask;
534 u64 rti_err_alarm;
535
536 u8 unused11[0x100 - 0x88];
537
538/* DMA arbiter */
539 u64 rx_queue_priority;
540#define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
541#define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
542#define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
543#define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
544#define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
545#define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
546#define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
547#define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
548
549#define RX_QUEUE_PRI_0 0 /* highest */
550#define RX_QUEUE_PRI_1 1
551#define RX_QUEUE_PRI_2 2
552#define RX_QUEUE_PRI_3 3
553#define RX_QUEUE_PRI_4 4
554#define RX_QUEUE_PRI_5 5
555#define RX_QUEUE_PRI_6 6
556#define RX_QUEUE_PRI_7 7 /* lowest */
557
558 u64 rx_w_round_robin_0;
559 u64 rx_w_round_robin_1;
560 u64 rx_w_round_robin_2;
561 u64 rx_w_round_robin_3;
562 u64 rx_w_round_robin_4;
563
564 /* Per-ring controller regs */
565#define RX_MAX_RINGS 8
566#if 0
567#define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */
568#define RX_MIN_RINGS_SZ 0x3F /* 63 */
569#endif
570 u64 prc_rxd0_n[RX_MAX_RINGS];
571 u64 prc_ctrl_n[RX_MAX_RINGS];
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700572#define PRC_CTRL_RC_ENABLED s2BIT(7)
573#define PRC_CTRL_RING_MODE (s2BIT(14)|s2BIT(15))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574#define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
575#define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
576#define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
577#define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700578#define PRC_CTRL_NO_SNOOP (s2BIT(22)|s2BIT(23))
579#define PRC_CTRL_NO_SNOOP_DESC s2BIT(22)
580#define PRC_CTRL_NO_SNOOP_BUFF s2BIT(23)
581#define PRC_CTRL_BIMODAL_INTERRUPT s2BIT(37)
582#define PRC_CTRL_GROUP_READS s2BIT(38)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
584
585 u64 prc_alarm_action;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700586#define PRC_ALARM_ACTION_RR_R0_STOP s2BIT(3)
587#define PRC_ALARM_ACTION_RW_R0_STOP s2BIT(7)
588#define PRC_ALARM_ACTION_RR_R1_STOP s2BIT(11)
589#define PRC_ALARM_ACTION_RW_R1_STOP s2BIT(15)
590#define PRC_ALARM_ACTION_RR_R2_STOP s2BIT(19)
591#define PRC_ALARM_ACTION_RW_R2_STOP s2BIT(23)
592#define PRC_ALARM_ACTION_RR_R3_STOP s2BIT(27)
593#define PRC_ALARM_ACTION_RW_R3_STOP s2BIT(31)
594#define PRC_ALARM_ACTION_RR_R4_STOP s2BIT(35)
595#define PRC_ALARM_ACTION_RW_R4_STOP s2BIT(39)
596#define PRC_ALARM_ACTION_RR_R5_STOP s2BIT(43)
597#define PRC_ALARM_ACTION_RW_R5_STOP s2BIT(47)
598#define PRC_ALARM_ACTION_RR_R6_STOP s2BIT(51)
599#define PRC_ALARM_ACTION_RW_R6_STOP s2BIT(55)
600#define PRC_ALARM_ACTION_RR_R7_STOP s2BIT(59)
601#define PRC_ALARM_ACTION_RW_R7_STOP s2BIT(63)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700602
603/* Receive traffic interrupts */
604 u64 rti_command_mem;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700605#define RTI_CMD_MEM_WE s2BIT(7)
606#define RTI_CMD_MEM_STROBE s2BIT(15)
607#define RTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
608#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED s2BIT(15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609#define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
610
611 u64 rti_data1_mem;
612#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700613#define RTI_DATA1_MEM_RX_TIMER_AC_EN s2BIT(38)
614#define RTI_DATA1_MEM_RX_TIMER_CI_EN s2BIT(39)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
616#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
617#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
618
619 u64 rti_data2_mem;
620#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
621#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
622#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
623#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
624
625 u64 rx_pa_cfg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700626#define RX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
627#define RX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)
628#define RX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)
629#define RX_PA_CFG_IGNORE_L2_ERR s2BIT(6)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630
Ananda Rajubd1034f2006-04-21 19:20:22 -0400631 u64 unused_11_1;
632
633 u64 ring_bump_counter1;
634 u64 ring_bump_counter2;
635
636 u8 unused12[0x700 - 0x1F0];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637
638 u64 rxdma_debug_ctrl;
639
640 u8 unused13[0x2000 - 0x1f08];
641
642/* Media Access Controller Register */
643 u64 mac_int_status;
644 u64 mac_int_mask;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700645#define MAC_INT_STATUS_TMAC_INT s2BIT(0)
646#define MAC_INT_STATUS_RMAC_INT s2BIT(1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647
648 u64 mac_tmac_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700649#define TMAC_ECC_SG_ERR s2BIT(7)
650#define TMAC_ECC_DB_ERR s2BIT(15)
651#define TMAC_TX_BUF_OVRN s2BIT(23)
652#define TMAC_TX_CRI_ERR s2BIT(31)
653#define TMAC_TX_SM_ERR s2BIT(39)
654#define TMAC_DESC_ECC_SG_ERR s2BIT(47)
655#define TMAC_DESC_ECC_DB_ERR s2BIT(55)
Sivakumar Subramani9caab452007-09-06 06:21:54 -0400656
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 u64 mac_tmac_err_mask;
658 u64 mac_tmac_err_alarm;
659
660 u64 mac_rmac_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700661#define RMAC_RX_BUFF_OVRN s2BIT(0)
662#define RMAC_FRM_RCVD_INT s2BIT(1)
663#define RMAC_UNUSED_INT s2BIT(2)
664#define RMAC_RTS_PNUM_ECC_SG_ERR s2BIT(5)
665#define RMAC_RTS_DS_ECC_SG_ERR s2BIT(6)
666#define RMAC_RD_BUF_ECC_SG_ERR s2BIT(7)
667#define RMAC_RTH_MAP_ECC_SG_ERR s2BIT(8)
668#define RMAC_RTH_SPDM_ECC_SG_ERR s2BIT(9)
669#define RMAC_RTS_VID_ECC_SG_ERR s2BIT(10)
670#define RMAC_DA_SHADOW_ECC_SG_ERR s2BIT(11)
671#define RMAC_RTS_PNUM_ECC_DB_ERR s2BIT(13)
672#define RMAC_RTS_DS_ECC_DB_ERR s2BIT(14)
673#define RMAC_RD_BUF_ECC_DB_ERR s2BIT(15)
674#define RMAC_RTH_MAP_ECC_DB_ERR s2BIT(16)
675#define RMAC_RTH_SPDM_ECC_DB_ERR s2BIT(17)
676#define RMAC_RTS_VID_ECC_DB_ERR s2BIT(18)
677#define RMAC_DA_SHADOW_ECC_DB_ERR s2BIT(19)
678#define RMAC_LINK_STATE_CHANGE_INT s2BIT(31)
679#define RMAC_RX_SM_ERR s2BIT(39)
680#define RMAC_SINGLE_ECC_ERR (s2BIT(5) | s2BIT(6) | s2BIT(7) |\
681 s2BIT(8) | s2BIT(9) | s2BIT(10)|\
682 s2BIT(11))
683#define RMAC_DOUBLE_ECC_ERR (s2BIT(13) | s2BIT(14) | s2BIT(15) |\
684 s2BIT(16) | s2BIT(17) | s2BIT(18)|\
685 s2BIT(19))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686 u64 mac_rmac_err_mask;
687 u64 mac_rmac_err_alarm;
688
689 u8 unused14[0x100 - 0x40];
690
691 u64 mac_cfg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700692#define MAC_CFG_TMAC_ENABLE s2BIT(0)
693#define MAC_CFG_RMAC_ENABLE s2BIT(1)
694#define MAC_CFG_LAN_NOT_WAN s2BIT(2)
695#define MAC_CFG_TMAC_LOOPBACK s2BIT(3)
696#define MAC_CFG_TMAC_APPEND_PAD s2BIT(4)
697#define MAC_CFG_RMAC_STRIP_FCS s2BIT(5)
698#define MAC_CFG_RMAC_STRIP_PAD s2BIT(6)
699#define MAC_CFG_RMAC_PROM_ENABLE s2BIT(7)
700#define MAC_RMAC_DISCARD_PFRM s2BIT(8)
701#define MAC_RMAC_BCAST_ENABLE s2BIT(9)
702#define MAC_RMAC_ALL_ADDR_ENABLE s2BIT(10)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
704
705 u64 tmac_avg_ipg;
706#define TMAC_AVG_IPG(val) vBIT(val,0,8)
707
708 u64 rmac_max_pyld_len;
709#define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
710#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
711#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
712
713 u64 rmac_err_cfg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700714#define RMAC_ERR_FCS s2BIT(0)
715#define RMAC_ERR_FCS_ACCEPT s2BIT(1)
716#define RMAC_ERR_TOO_LONG s2BIT(1)
717#define RMAC_ERR_TOO_LONG_ACCEPT s2BIT(1)
718#define RMAC_ERR_RUNT s2BIT(2)
719#define RMAC_ERR_RUNT_ACCEPT s2BIT(2)
720#define RMAC_ERR_LEN_MISMATCH s2BIT(3)
721#define RMAC_ERR_LEN_MISMATCH_ACCEPT s2BIT(3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722
723 u64 rmac_cfg_key;
724#define RMAC_CFG_KEY(val) vBIT(val,0,16)
725
Sreenivasa Honnurfaa4f792008-01-24 01:45:43 -0800726#define S2IO_MAC_ADDR_START_OFFSET 0
727
728#define S2IO_XENA_MAX_MC_ADDRESSES 64 /* multicast addresses */
729#define S2IO_HERC_MAX_MC_ADDRESSES 256
730
731#define S2IO_XENA_MAX_MAC_ADDRESSES 16
732#define S2IO_HERC_MAX_MAC_ADDRESSES 64
733
734#define S2IO_XENA_MC_ADDR_START_OFFSET 16
735#define S2IO_HERC_MC_ADDR_START_OFFSET 64
736
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737 u64 rmac_addr_cmd_mem;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700738#define RMAC_ADDR_CMD_MEM_WE s2BIT(7)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739#define RMAC_ADDR_CMD_MEM_RD 0
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700740#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
741#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING s2BIT(15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
743
744 u64 rmac_addr_data0_mem;
745#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700746#define RMAC_ADDR_DATA0_MEM_USER s2BIT(48)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747
748 u64 rmac_addr_data1_mem;
749#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
750
751 u8 unused15[0x8];
752
753/*
754 u64 rmac_addr_cfg;
755#define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
756#define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400757#define RMAC_ADDR_BCAST_EN vBIT(0)_48
758#define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759*/
760 u64 tmac_ipg_cfg;
761
762 u64 rmac_pause_cfg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700763#define RMAC_PAUSE_GEN s2BIT(0)
764#define RMAC_PAUSE_GEN_ENABLE s2BIT(0)
765#define RMAC_PAUSE_RX s2BIT(1)
766#define RMAC_PAUSE_RX_ENABLE s2BIT(1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
768#define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
769
770 u64 rmac_red_cfg;
771
772 u64 rmac_red_rate_q0q3;
773 u64 rmac_red_rate_q4q7;
774
775 u64 mac_link_util;
776#define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
777#define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
778#define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
779#define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
780#define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
781#define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
782
783#define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \
784 MAC_RX_LINK_UTIL_DISABLE
785
786 u64 rmac_invalid_ipg;
787
788/* rx traffic steering */
789#define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
790 u64 rts_frm_len_n[8];
791
792 u64 rts_qos_steering;
793
794#define MAX_DIX_MAP 4
795 u64 rts_dix_map_n[MAX_DIX_MAP];
796#define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700797#define RTS_DIX_MAP_SCW(val) s2BIT(val,21)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798
799 u64 rts_q_alternates;
800 u64 rts_default_q;
801
802 u64 rts_ctrl;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700803#define RTS_CTRL_IGNORE_SNAP_OUI s2BIT(2)
804#define RTS_CTRL_IGNORE_LLC_CTRL s2BIT(3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805
806 u64 rts_pn_cam_ctrl;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700807#define RTS_PN_CAM_CTRL_WE s2BIT(7)
808#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD s2BIT(15)
809#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED s2BIT(15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
811 u64 rts_pn_cam_data;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700812#define RTS_PN_CAM_DATA_TCP_SELECT s2BIT(7)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813#define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
814#define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
815
816 u64 rts_ds_mem_ctrl;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700817#define RTS_DS_MEM_CTRL_WE s2BIT(7)
818#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD s2BIT(15)
819#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED s2BIT(15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
821 u64 rts_ds_mem_data;
822#define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
823
824 u8 unused16[0x700 - 0x220];
825
826 u64 mac_debug_ctrl;
827#define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
828
829 u8 unused17[0x2800 - 0x2708];
830
831/* memory controller registers */
832 u64 mc_int_status;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700833#define MC_INT_STATUS_MC_INT s2BIT(0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834 u64 mc_int_mask;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700835#define MC_INT_MASK_MC_INT s2BIT(0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836
837 u64 mc_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700838#define MC_ERR_REG_ECC_DB_ERR_L s2BIT(14)
839#define MC_ERR_REG_ECC_DB_ERR_U s2BIT(15)
840#define MC_ERR_REG_MIRI_ECC_DB_ERR_0 s2BIT(18)
841#define MC_ERR_REG_MIRI_ECC_DB_ERR_1 s2BIT(20)
842#define MC_ERR_REG_MIRI_CRI_ERR_0 s2BIT(22)
843#define MC_ERR_REG_MIRI_CRI_ERR_1 s2BIT(23)
844#define MC_ERR_REG_SM_ERR s2BIT(31)
845#define MC_ERR_REG_ECC_ALL_SNG (s2BIT(2) | s2BIT(3) | s2BIT(4) | s2BIT(5) |\
846 s2BIT(17) | s2BIT(19))
847#define MC_ERR_REG_ECC_ALL_DBL (s2BIT(10) | s2BIT(11) | s2BIT(12) |\
848 s2BIT(13) | s2BIT(18) | s2BIT(20))
849#define PLL_LOCK_N s2BIT(39)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 u64 mc_err_mask;
851 u64 mc_err_alarm;
852
853 u8 unused18[0x100 - 0x28];
854
855/* MC configuration */
856 u64 rx_queue_cfg;
857#define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
858#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
859#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
860#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
861#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
862#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
863#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
864#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
865
866 u64 mc_rldram_mrs;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700867#define MC_RLDRAM_QUEUE_SIZE_ENABLE s2BIT(39)
868#define MC_RLDRAM_MRS_ENABLE s2BIT(47)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869
870 u64 mc_rldram_interleave;
871
872 u64 mc_pause_thresh_q0q3;
873 u64 mc_pause_thresh_q4q7;
874
875 u64 mc_red_thresh_q[8];
876
877 u8 unused19[0x200 - 0x168];
878 u64 mc_rldram_ref_per;
879 u8 unused20[0x220 - 0x208];
880 u64 mc_rldram_test_ctrl;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700881#define MC_RLDRAM_TEST_MODE s2BIT(47)
882#define MC_RLDRAM_TEST_WRITE s2BIT(7)
883#define MC_RLDRAM_TEST_GO s2BIT(15)
884#define MC_RLDRAM_TEST_DONE s2BIT(23)
885#define MC_RLDRAM_TEST_PASS s2BIT(31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886
887 u8 unused21[0x240 - 0x228];
888 u64 mc_rldram_test_add;
889 u8 unused22[0x260 - 0x248];
890 u64 mc_rldram_test_d0;
891 u8 unused23[0x280 - 0x268];
892 u64 mc_rldram_test_d1;
893 u8 unused24[0x300 - 0x288];
894 u64 mc_rldram_test_d2;
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700895
896 u8 unused24_1[0x360 - 0x308];
897 u64 mc_rldram_ctrl;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700898#define MC_RLDRAM_ENABLE_ODT s2BIT(7)
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700899
900 u8 unused24_2[0x640 - 0x368];
901 u64 mc_rldram_ref_per_herc;
902#define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16)
903
904 u8 unused24_3[0x660 - 0x648];
905 u64 mc_rldram_mrs_herc;
906
907 u8 unused25[0x700 - 0x668];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700908 u64 mc_debug_ctrl;
909
910 u8 unused26[0x3000 - 0x2f08];
911
912/* XGXG */
913 /* XGXS control registers */
914
915 u64 xgxs_int_status;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700916#define XGXS_INT_STATUS_TXGXS s2BIT(0)
917#define XGXS_INT_STATUS_RXGXS s2BIT(1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918 u64 xgxs_int_mask;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700919#define XGXS_INT_MASK_TXGXS s2BIT(0)
920#define XGXS_INT_MASK_RXGXS s2BIT(1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921
922 u64 xgxs_txgxs_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700923#define TXGXS_ECC_SG_ERR s2BIT(7)
924#define TXGXS_ECC_DB_ERR s2BIT(15)
925#define TXGXS_ESTORE_UFLOW s2BIT(31)
926#define TXGXS_TX_SM_ERR s2BIT(39)
Sivakumar Subramani9caab452007-09-06 06:21:54 -0400927
Linus Torvalds1da177e2005-04-16 15:20:36 -0700928 u64 xgxs_txgxs_err_mask;
929 u64 xgxs_txgxs_err_alarm;
930
931 u64 xgxs_rxgxs_err_reg;
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700932#define RXGXS_ESTORE_OFLOW s2BIT(7)
933#define RXGXS_RX_SM_ERR s2BIT(39)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934 u64 xgxs_rxgxs_err_mask;
935 u64 xgxs_rxgxs_err_alarm;
936
937 u8 unused27[0x100 - 0x40];
938
939 u64 xgxs_cfg;
940 u64 xgxs_status;
941
942 u64 xgxs_cfg_key;
943 u64 xgxs_efifo_cfg; /* CHANGED */
944 u64 rxgxs_ber_0; /* CHANGED */
945 u64 rxgxs_ber_1; /* CHANGED */
946
ravinandan.arakali@neterion.comad4ebed2005-10-17 18:26:20 -0700947 u64 spi_control;
948#define SPI_CONTROL_KEY(key) vBIT(key,0,4)
949#define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3)
950#define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8)
951#define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24)
Jiri Slabyb7b5a122007-10-18 23:40:29 -0700952#define SPI_CONTROL_SEL1 s2BIT(4)
953#define SPI_CONTROL_REQ s2BIT(7)
954#define SPI_CONTROL_NACK s2BIT(5)
955#define SPI_CONTROL_DONE s2BIT(6)
ravinandan.arakali@neterion.comad4ebed2005-10-17 18:26:20 -0700956 u64 spi_data;
957#define SPI_DATA_WRITE(data,len) vBIT(data,0,len)
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500958};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500960#define XENA_REG_SPACE sizeof(struct XENA_dev_config)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961#define XENA_EEPROM_SPACE (0x01 << 11)
962
963#endif /* _REGS_H */