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Sathya Perla6b7c5b92009-03-11 23:32:03 -07001/*
Ajit Khaparde294aedc2010-02-19 13:54:58 +00002 * Copyright (C) 2005 - 2010 ServerEngines
Sathya Perla6b7c5b92009-03-11 23:32:03 -07003 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18/********* Mailbox door bell *************/
19/* Used for driver communication with the FW.
20 * The software must write this register twice to post any command. First,
21 * it writes the register with hi=1 and the upper bits of the physical address
22 * for the MAILBOX structure. Software must poll the ready bit until this
23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24 * bits in the address. It must poll the ready bit until the command is
25 * complete. Upon completion, the MAILBOX will contain a valid completion
26 * queue entry.
27 */
28#define MPU_MAILBOX_DB_OFFSET 0x160
29#define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
30#define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
31
32#define MPU_EP_CONTROL 0
33
34/********** MPU semphore ******************/
35#define MPU_EP_SEMAPHORE_OFFSET 0xac
36#define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
37#define EP_SEMAPHORE_POST_ERR_MASK 0x1
38#define EP_SEMAPHORE_POST_ERR_SHIFT 31
39/* MPU semphore POST stage values */
40#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
41#define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
42#define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
43#define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
44
45/********* Memory BAR register ************/
46#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
47/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
48 * Disable" may still globally block interrupts in addition to individual
49 * interrupt masks; a mechanism for the device driver to block all interrupts
50 * atomically without having to arbitrate for the PCI Interrupt Disable bit
51 * with the OS.
52 */
53#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
Sathya Perla6b7c5b92009-03-11 23:32:03 -070054
Uwe Kleine-König65155b32010-06-11 12:17:01 +020055/********* Power management (WOL) **********/
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +000056#define PCICFG_PM_CONTROL_OFFSET 0x44
57#define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
58
Ajit Khaparde7c185272010-07-29 06:16:33 +000059/********* Online Control Registers *******/
60#define PCICFG_ONLINE0 0xB0
61#define PCICFG_ONLINE1 0xB4
62
63/********* UE Status and Mask Registers ***/
64#define PCICFG_UE_STATUS_LOW 0xA0
65#define PCICFG_UE_STATUS_HIGH 0xA4
66#define PCICFG_UE_STATUS_LOW_MASK 0xA8
67#define PCICFG_UE_STATUS_HI_MASK 0xAC
68
Sathya Perlac001c212009-07-01 01:06:07 +000069/********* ISR0 Register offset **********/
70#define CEV_ISR0_OFFSET 0xC18
71#define CEV_ISR_SIZE 4
72
Sathya Perla6b7c5b92009-03-11 23:32:03 -070073/********* Event Q door bell *************/
74#define DB_EQ_OFFSET DB_CQ_OFFSET
75#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
76/* Clear the interrupt for this eq */
77#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
78/* Must be 1 */
Sathya Perla5fb379e2009-06-18 00:02:59 +000079#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
Sathya Perla6b7c5b92009-03-11 23:32:03 -070080/* Number of event entries processed */
81#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
82/* Rearm bit */
83#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
84
85/********* Compl Q door bell *************/
86#define DB_CQ_OFFSET 0x120
87#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
88/* Number of event entries processed */
89#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
90/* Rearm bit */
91#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
92
93/********** TX ULP door bell *************/
94#define DB_TXULP1_OFFSET 0x60
95#define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
96/* Number of tx entries posted */
97#define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
98#define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
99
100/********** RQ(erx) door bell ************/
101#define DB_RQ_OFFSET 0x100
102#define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
103/* Number of rx frags posted */
104#define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
105
Sathya Perla5fb379e2009-06-18 00:02:59 +0000106/********** MCC door bell ************/
107#define DB_MCCQ_OFFSET 0x140
108#define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
109/* Number of entries posted */
110#define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
111
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000112/********** SRIOV VF PCICFG OFFSET ********/
113#define SRIOV_VF_PCICFG_OFFSET (4096)
114
Ajit Khaparde3f0d4562010-02-09 01:30:35 +0000115/* Flashrom related descriptors */
116#define IMAGE_TYPE_FIRMWARE 160
117#define IMAGE_TYPE_BOOTCODE 224
118#define IMAGE_TYPE_OPTIONROM 32
119
120#define NUM_FLASHDIR_ENTRIES 32
121
122#define IMG_TYPE_ISCSI_ACTIVE 0
123#define IMG_TYPE_REDBOOT 1
124#define IMG_TYPE_BIOS 2
125#define IMG_TYPE_PXE_BIOS 3
126#define IMG_TYPE_FCOE_BIOS 8
127#define IMG_TYPE_ISCSI_BACKUP 9
128#define IMG_TYPE_FCOE_FW_ACTIVE 10
129#define IMG_TYPE_FCOE_FW_BACKUP 11
Sarveshwar Bandi9fe96932010-03-02 22:37:28 +0000130#define IMG_TYPE_NCSI_FW 13
Ajit Khaparde3f0d4562010-02-09 01:30:35 +0000131
132#define FLASHROM_OPER_FLASH 1
133#define FLASHROM_OPER_SAVE 2
134#define FLASHROM_OPER_REPORT 4
135
136#define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image sz */
137#define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM img sz */
138#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */
139#define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max fw image size */
140#define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM img sz */
141#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */
Sarveshwar Bandi9fe96932010-03-02 22:37:28 +0000142#define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144) /* Max NSCI image sz */
Ajit Khaparde3f0d4562010-02-09 01:30:35 +0000143
144#define FLASH_NCSI_MAGIC (0x16032009)
145#define FLASH_NCSI_DISABLED (0)
146#define FLASH_NCSI_ENABLED (1)
147
148#define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000)
149
150/* Offsets for components on Flash. */
151#define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
152#define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296)
153#define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016)
154#define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736)
155#define FLASH_iSCSI_BIOS_START_g2 (7340032)
156#define FLASH_PXE_BIOS_START_g2 (7864320)
157#define FLASH_FCoE_BIOS_START_g2 (524288)
158#define FLASH_REDBOOT_START_g2 (0)
159
Sarveshwar Bandi9fe96932010-03-02 22:37:28 +0000160#define FLASH_NCSI_START_g3 (15990784)
Ajit Khaparde3f0d4562010-02-09 01:30:35 +0000161#define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
162#define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304)
163#define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456)
164#define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608)
165#define FLASH_iSCSI_BIOS_START_g3 (12582912)
166#define FLASH_PXE_BIOS_START_g3 (13107200)
167#define FLASH_FCoE_BIOS_START_g3 (13631488)
168#define FLASH_REDBOOT_START_g3 (262144)
169
Ajit Khaparde1ef78ab2010-09-03 06:17:10 +0000170/************* Rx Packet Type Encoding **************/
171#define BE_UNICAST_PACKET 0
172#define BE_MULTICAST_PACKET 1
173#define BE_BROADCAST_PACKET 2
174#define BE_RSVD_PACKET 3
Ajit Khaparde3f0d4562010-02-09 01:30:35 +0000175
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700176/*
177 * BE descriptors: host memory data structures whose formats
178 * are hardwired in BE silicon.
179 */
180/* Event Queue Descriptor */
181#define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
182#define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
183#define EQ_ENTRY_RES_ID_SHIFT 16
Ajit Khaparde3f0d4562010-02-09 01:30:35 +0000184
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700185struct be_eq_entry {
186 u32 evt;
187};
188
189/* TX Queue Descriptor */
190#define ETH_WRB_FRAG_LEN_MASK 0xFFFF
191struct be_eth_wrb {
192 u32 frag_pa_hi; /* dword 0 */
193 u32 frag_pa_lo; /* dword 1 */
194 u32 rsvd0; /* dword 2 */
195 u32 frag_len; /* dword 3: bits 0 - 15 */
196} __packed;
197
198/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
199 * actual structure is defined as a byte : used to calculate
200 * offset/shift/mask of each field */
201struct amap_eth_hdr_wrb {
202 u8 rsvd0[32]; /* dword 0 */
203 u8 rsvd1[32]; /* dword 1 */
204 u8 complete; /* dword 2 */
205 u8 event;
206 u8 crc;
207 u8 forward;
Ajit Khaparde49e4b8472010-06-14 04:56:07 +0000208 u8 lso6;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700209 u8 mgmt;
210 u8 ipcs;
211 u8 udpcs;
212 u8 tcpcs;
213 u8 lso;
214 u8 vlan;
215 u8 gso[2];
216 u8 num_wrb[5];
217 u8 lso_mss[14];
218 u8 len[16]; /* dword 3 */
219 u8 vlan_tag[16];
220} __packed;
221
222struct be_eth_hdr_wrb {
223 u32 dw[4];
224};
225
226/* TX Compl Queue Descriptor */
227
228/* Pseudo amap definition for eth_tx_compl in which each bit of the
229 * actual structure is defined as a byte: used to calculate
230 * offset/shift/mask of each field */
231struct amap_eth_tx_compl {
232 u8 wrb_index[16]; /* dword 0 */
233 u8 ct[2]; /* dword 0 */
234 u8 port[2]; /* dword 0 */
235 u8 rsvd0[8]; /* dword 0 */
236 u8 status[4]; /* dword 0 */
237 u8 user_bytes[16]; /* dword 1 */
238 u8 nwh_bytes[8]; /* dword 1 */
239 u8 lso; /* dword 1 */
240 u8 cast_enc[2]; /* dword 1 */
241 u8 rsvd1[5]; /* dword 1 */
242 u8 rsvd2[32]; /* dword 2 */
243 u8 pkts[16]; /* dword 3 */
244 u8 ringid[11]; /* dword 3 */
245 u8 hash_val[4]; /* dword 3 */
246 u8 valid; /* dword 3 */
247} __packed;
248
249struct be_eth_tx_compl {
250 u32 dw[4];
251};
252
253/* RX Queue Descriptor */
254struct be_eth_rx_d {
255 u32 fragpa_hi;
256 u32 fragpa_lo;
257};
258
259/* RX Compl Queue Descriptor */
260
261/* Pseudo amap definition for eth_rx_compl in which each bit of the
262 * actual structure is defined as a byte: used to calculate
263 * offset/shift/mask of each field */
264struct amap_eth_rx_compl {
265 u8 vlan_tag[16]; /* dword 0 */
266 u8 pktsize[14]; /* dword 0 */
267 u8 port; /* dword 0 */
268 u8 ip_opt; /* dword 0 */
269 u8 err; /* dword 1 */
270 u8 rsshp; /* dword 1 */
271 u8 ipf; /* dword 1 */
272 u8 tcpf; /* dword 1 */
273 u8 udpf; /* dword 1 */
274 u8 ipcksm; /* dword 1 */
275 u8 l4_cksm; /* dword 1 */
276 u8 ip_version; /* dword 1 */
277 u8 macdst[6]; /* dword 1 */
278 u8 vtp; /* dword 1 */
279 u8 rsvd0; /* dword 1 */
280 u8 fragndx[10]; /* dword 1 */
281 u8 ct[2]; /* dword 1 */
282 u8 sw; /* dword 1 */
283 u8 numfrags[3]; /* dword 1 */
284 u8 rss_flush; /* dword 2 */
285 u8 cast_enc[2]; /* dword 2 */
Ajit Khaparde84517482009-09-04 03:12:16 +0000286 u8 vtm; /* dword 2 */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700287 u8 rss_bank; /* dword 2 */
288 u8 rsvd1[23]; /* dword 2 */
289 u8 lro_pkt; /* dword 2 */
290 u8 rsvd2[2]; /* dword 2 */
291 u8 valid; /* dword 2 */
292 u8 rsshash[32]; /* dword 3 */
293} __packed;
294
295struct be_eth_rx_compl {
296 u32 dw[4];
297};
Ajit Khaparde84517482009-09-04 03:12:16 +0000298
Ajit Khaparde84517482009-09-04 03:12:16 +0000299struct controller_id {
300 u32 vendor;
301 u32 device;
302 u32 subvendor;
303 u32 subdevice;
304};
305
Ajit Khaparde3f0d4562010-02-09 01:30:35 +0000306struct flash_comp {
307 unsigned long offset;
308 int optype;
309 int size;
310};
311
312struct image_hdr {
313 u32 imageid;
314 u32 imageoffset;
315 u32 imagelength;
316 u32 image_checksum;
317 u8 image_version[32];
318};
319struct flash_file_hdr_g2 {
Ajit Khaparde84517482009-09-04 03:12:16 +0000320 u8 sign[32];
321 u32 cksum;
322 u32 antidote;
323 struct controller_id cont_id;
324 u32 file_len;
325 u32 chunk_num;
326 u32 total_chunks;
327 u32 num_imgs;
328 u8 build[24];
329};
330
Ajit Khaparde3f0d4562010-02-09 01:30:35 +0000331struct flash_file_hdr_g3 {
332 u8 sign[52];
333 u8 ufi_version[4];
334 u32 file_len;
335 u32 cksum;
336 u32 antidote;
337 u32 num_imgs;
338 u8 build[24];
339 u8 rsvd[32];
340};
341
Ajit Khaparde84517482009-09-04 03:12:16 +0000342struct flash_section_hdr {
343 u32 format_rev;
344 u32 cksum;
345 u32 antidote;
346 u32 build_no;
347 u8 id_string[64];
348 u32 active_entry_mask;
349 u32 valid_entry_mask;
350 u32 org_content_mask;
351 u32 rsvd0;
352 u32 rsvd1;
353 u32 rsvd2;
354 u32 rsvd3;
355 u32 rsvd4;
356};
357
358struct flash_section_entry {
359 u32 type;
360 u32 offset;
361 u32 pad_size;
362 u32 image_size;
363 u32 cksum;
364 u32 entry_point;
365 u32 rsvd0;
366 u32 rsvd1;
367 u8 ver_data[32];
368};
369
370struct flash_section_info {
371 u8 cookie[32];
372 struct flash_section_hdr fsec_hdr;
373 struct flash_section_entry fsec_entry[32];
374};