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Kwangwoo Lee1f26a8a2009-04-28 10:35:57 +09001/* linux/arch/arm/mach-s3c6410/mach-anw6410.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 * Copyright 2009 Kwangwoo Lee
8 * Kwangwoo Lee <kwangwoo.lee@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25#include <linux/i2c.h>
26#include <linux/fb.h>
27#include <linux/gpio.h>
28#include <linux/delay.h>
29#include <linux/dm9000.h>
30
31#include <video/platform_lcd.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/hardware.h>
38#include <mach/regs-fb.h>
39#include <mach/map.h>
40
41#include <asm/irq.h>
42#include <asm/mach-types.h>
43
44#include <plat/regs-serial.h>
45#include <plat/iic.h>
46#include <plat/fb.h>
47
48#include <plat/s3c6410.h>
49#include <plat/clock.h>
50#include <plat/devs.h>
51#include <plat/cpu.h>
52#include <plat/regs-gpio.h>
53#include <plat/regs-modem.h>
54
55/* DM9000 */
56#define ANW6410_PA_DM9000 (0x18000000)
57
58/* A hardware buffer to control external devices is mapped at 0x30000000.
59 * It can not be read. So current status must be kept in anw6410_extdev_status.
60 */
61#define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
62#define ANW6410_PA_EXTDEV (0x30000000)
63
64#define ANW6410_EN_DM9000 (1<<11)
65#define ANW6410_EN_LCD (1<<14)
66
67static __u32 anw6410_extdev_status;
68
69static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
70 [0] = {
71 .hwport = 0,
72 .flags = 0,
73 .ucon = 0x3c5,
74 .ulcon = 0x03,
75 .ufcon = 0x51,
76 },
77 [1] = {
78 .hwport = 1,
79 .flags = 0,
80 .ucon = 0x3c5,
81 .ulcon = 0x03,
82 .ufcon = 0x51,
83 },
84};
85
86/* framebuffer and LCD setup. */
87static void __init anw6410_lcd_mode_set(void)
88{
89 u32 tmp;
90
91 /* set the LCD type */
92 tmp = __raw_readl(S3C64XX_SPCON);
93 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
94 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
95 __raw_writel(tmp, S3C64XX_SPCON);
96
97 /* remove the LCD bypass */
98 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
99 tmp &= ~MIFPCON_LCD_BYPASS;
100 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
101}
102
103/* GPF1 = LCD panel power
104 * GPF4 = LCD backlight control
105 */
106static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
107 unsigned int power)
108{
109 if (power) {
110 anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
111 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
112
113 gpio_direction_output(S3C64XX_GPF(1), 1);
114 gpio_direction_output(S3C64XX_GPF(4), 1);
115 } else {
116 anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
117 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
118
119 gpio_direction_output(S3C64XX_GPF(1), 0);
120 gpio_direction_output(S3C64XX_GPF(4), 0);
121 }
122}
123
124static struct plat_lcd_data anw6410_lcd_power_data = {
125 .set_power = anw6410_lcd_power_set,
126};
127
128static struct platform_device anw6410_lcd_powerdev = {
129 .name = "platform-lcd",
130 .dev.parent = &s3c_device_fb.dev,
131 .dev.platform_data = &anw6410_lcd_power_data,
132};
133
134static struct s3c_fb_pd_win anw6410_fb_win0 = {
135 /* this is to ensure we use win0 */
136 .win_mode = {
137 .pixclock = 41094,
138 .left_margin = 8,
139 .right_margin = 13,
140 .upper_margin = 7,
141 .lower_margin = 5,
142 .hsync_len = 3,
143 .vsync_len = 1,
144 .xres = 800,
145 .yres = 480,
146 },
147 .max_bpp = 32,
148 .default_bpp = 16,
149};
150
151/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
152static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
153 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
154 .win[0] = &anw6410_fb_win0,
155 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
156 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
157};
158
159/* DM9000AEP 10/100 ethernet controller */
160static void __init anw6410_dm9000_enable(void)
161{
162 anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
163 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
164}
165
166static struct resource anw6410_dm9000_resource[] = {
167 [0] = {
168 .start = ANW6410_PA_DM9000,
169 .end = ANW6410_PA_DM9000 + 3,
170 .flags = IORESOURCE_MEM,
171 },
172 [1] = {
173 .start = ANW6410_PA_DM9000 + 4,
174 .end = ANW6410_PA_DM9000 + 4 + 500,
175 .flags = IORESOURCE_MEM,
176 },
177 [2] = {
178 .start = IRQ_EINT(15),
179 .end = IRQ_EINT(15),
180 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
181 },
182};
183
184static struct dm9000_plat_data anw6410_dm9000_pdata = {
185 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
186 /* dev_addr can be set to provide hwaddr. */
187};
188
189static struct platform_device anw6410_device_eth = {
190 .name = "dm9000",
191 .id = -1,
192 .num_resources = ARRAY_SIZE(anw6410_dm9000_resource),
193 .resource = anw6410_dm9000_resource,
194 .dev = {
195 .platform_data = &anw6410_dm9000_pdata,
196 },
197};
198
199static struct map_desc anw6410_iodesc[] __initdata = {
200 {
201 .virtual = (unsigned long)ANW6410_VA_EXTDEV,
202 .pfn = __phys_to_pfn(ANW6410_PA_EXTDEV),
203 .length = SZ_64K,
204 .type = MT_DEVICE,
205 },
206};
207
208static struct platform_device *anw6410_devices[] __initdata = {
209 &s3c_device_fb,
210 &anw6410_lcd_powerdev,
211 &anw6410_device_eth,
212};
213
214static void __init anw6410_map_io(void)
215{
216 s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
217 s3c24xx_init_clocks(12000000);
218 s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
219
220 anw6410_lcd_mode_set();
221}
222
223static void __init anw6410_machine_init(void)
224{
225 s3c_fb_set_platdata(&anw6410_lcd_pdata);
226
227 gpio_request(S3C64XX_GPF(1), "panel power");
228 gpio_request(S3C64XX_GPF(4), "LCD backlight");
229
230 anw6410_dm9000_enable();
231
232 platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
233}
234
235MACHINE_START(ANW6410, "A&W6410")
236 /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
237 .phys_io = S3C_PA_UART & 0xfff00000,
238 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
239 .boot_params = S3C64XX_PA_SDRAM + 0x100,
240
241 .init_irq = s3c6410_init_irq,
242 .map_io = anw6410_map_io,
243 .init_machine = anw6410_machine_init,
244 .timer = &s3c24xx_timer,
245MACHINE_END